CN106024634B - Power transistor with electrostatic discharge protection diode structure and manufacturing method thereof - Google Patents
Power transistor with electrostatic discharge protection diode structure and manufacturing method thereof Download PDFInfo
- Publication number
- CN106024634B CN106024634B CN201610528260.5A CN201610528260A CN106024634B CN 106024634 B CN106024634 B CN 106024634B CN 201610528260 A CN201610528260 A CN 201610528260A CN 106024634 B CN106024634 B CN 106024634B
- Authority
- CN
- China
- Prior art keywords
- region
- gate
- type doped
- polycrystalline silicon
- type
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 20
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 96
- 229920005591 polysilicon Polymers 0.000 claims abstract description 63
- 229910052751 metal Inorganic materials 0.000 claims abstract description 25
- 239000002184 metal Substances 0.000 claims abstract description 25
- 150000002500 ions Chemical class 0.000 claims description 20
- 238000002347 injection Methods 0.000 claims description 12
- 239000007924 injection Substances 0.000 claims description 12
- 238000000034 method Methods 0.000 claims description 10
- 239000000758 substrate Substances 0.000 claims description 9
- 238000000151 deposition Methods 0.000 claims description 6
- 238000005530 etching Methods 0.000 claims description 6
- 238000001259 photo etching Methods 0.000 claims description 4
- 238000009792 diffusion process Methods 0.000 claims description 3
- 238000004806 packaging method and process Methods 0.000 abstract description 9
- 239000010410 layer Substances 0.000 description 32
- 238000002513 implantation Methods 0.000 description 8
- 230000015556 catabolic process Effects 0.000 description 5
- 230000007704 transition Effects 0.000 description 4
- 239000012535 impurity Substances 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 238000011161 development Methods 0.000 description 2
- 230000002349 favourable effect Effects 0.000 description 2
- 238000001459 lithography Methods 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 238000002161 passivation Methods 0.000 description 2
- 239000005360 phosphosilicate glass Substances 0.000 description 2
- 208000033999 Device damage Diseases 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000004377 microelectronic Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- -1 phosphorus ion Chemical class 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 239000005368 silicate glass Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
Abstract
The invention relates to a power transistor with an electrostatic discharge protection diode structure and a manufacturing method thereof. The power transistor comprises a terminal area, an active area and a polycrystalline silicon gate area located between the terminal area and the active area, wherein the polycrystalline silicon gate area is separated from a polycrystalline silicon gate in the active area and comprises a gate and an electrostatic discharge protection diode structure on two sides of the gate, the gate and the electrostatic discharge protection diode structure are both made of polycrystalline silicon, the electrostatic discharge protection diode structure on two sides of the gate comprises a plurality of P-type doped areas and N-type doped areas, the P-type doped areas and the N-type doped areas are arranged at intervals in a first direction, first contact holes are formed in the outermost N-type doped areas on two sides of the polycrystalline silicon gate area, and second contact holes are formed in the gate. The polysilicon gate region is separated from the polysilicon gate in the active region to form an independent island structure, so that the gate is led out through the second contact hole to be connected with the gate metal, and batch packaging is facilitated.
Description
Technical Field
The invention relates to the field of semiconductor manufacturing, in particular to a power transistor with an electrostatic discharge protection diode structure and a manufacturing method of the power transistor with the electrostatic discharge protection diode structure.
Background
Electrostatic discharge is one of the most important reliability issues for power devices. ElectroStatic Discharge, ESD (ElectroStatic Discharge), is a phenomenon of rapid charge transfer between two objects, which is accompanied by a large electric field and current density. Electrostatic protection is too much to be prevented and is ubiquitous in the production, storage, transportation and use of power devices. Electrostatic discharge generates several kilovolts of discharge voltage across the power device, which is a significant cause of power device damage in power device applications and production. When the voltage across the device exceeds the breakdown voltage, any significant current flow causes significant power dissipation, resulting in a localized temperature rise of the device. If the temperature rise is large enough that the temperature reaches the intrinsic temperature, the resulting current may cause a hot surge, even if this occurs locally. With the increasing complexity of electromagnetic environment and the continuous reduction of the thickness of the gate oxide layer of the power device caused by the development of microelectronic technology, the protection of the ESD is increasingly important.
The development of the domestic integrated power transistor with anti-ESD protection is still in the initial stage, and has a large gap with the mature product with ESD protection of the overseas mainstream power transistor manufacturers. The ESD protection structure of the power device generally adopts three structures of PN junction, SCR (silicon controlled rectifier) and POLY (polysilicon) diode.
Disclosure of Invention
In view of the above, there is a need for a power transistor with esd protection diode structure that is easy to package.
A power transistor with an electrostatic discharge protection diode structure comprises a terminal region, an active region surrounded by the terminal region, and a polysilicon gate region located between the terminal region and the active region, wherein the polysilicon gate region is separated from a polysilicon gate in the active region, the polysilicon gate region comprises a gate and electrostatic discharge protection diode structures on two sides of the gate, the gate and the electrostatic discharge protection diode structures are both made of polysilicon, the electrostatic discharge protection diode structures on two sides of the gate comprise a plurality of P-type doped regions and N-type doped regions, the P-type doped regions and the N-type doped regions are arranged at intervals in a first direction, and the first direction is a direction in which the gate extends towards two sides; the P-type doped region or the N-type doped region positioned at the outermost positions on two sides of the polycrystalline silicon gate region is provided with a first contact hole, and the grid electrode is provided with a second contact hole.
In one embodiment, the doping type of the gate is N-type.
In one embodiment, the polysilicon gate region is surrounded by the active region and the termination region, wherein three sides of the polysilicon gate region are surrounded by the active region and the remaining one side is surrounded by the termination region.
In one embodiment, the P-type doped region and the N-type doped region have the same width, and the width is in a second direction perpendicular to the first direction.
In one embodiment, a first edge of the gate adjacent to the termination region protrudes outward such that a width of the gate is greater than widths of the P-type doped region and the N-type doped region.
In one embodiment, the second contact hole is disposed in a region where the first edge protrudes outward.
In one embodiment, the cross section of the first contact hole is a long strip extending along the second direction, and the cross section of the second contact hole is a long strip extending along the first direction.
In one embodiment, a doping concentration of each P-type doped region is less than a doping concentration of each N-type doped region, and a size of each P-type doped region in the first direction is greater than a size of each N-type doped region in the first direction.
According to the power transistor with the electrostatic discharge protection diode structure, the polycrystalline silicon grid region is separated from the polycrystalline silicon grid bars in the active region to form an independent island structure, the electrostatic discharge protection diode structure is arranged on two sides of the polycrystalline silicon grid region, the grid is arranged in the middle of the polycrystalline silicon grid region, the grid can be led out conveniently through the second contact hole to be connected with the grid metal, and batch packaging is facilitated.
It is also desirable to provide a method of manufacturing a power transistor with an esd protection diode structure.
A method for manufacturing a power transistor with an electrostatic discharge protection diode structure comprises the following steps: forming a field oxide layer and a gate oxide layer on a substrate; depositing polycrystalline silicon on the gate oxide layer and/or the field oxide layer to form a polycrystalline silicon gate; the polycrystalline silicon grid comprises a polycrystalline silicon grid bar of an active region and a polycrystalline silicon grid region positioned between the active region and a terminal region, and the polycrystalline silicon grid region is separated from the polycrystalline silicon grid bar in the active region; injecting P-type ions, forming a P well in the substrate, and forming a P-region in the polysilicon gate region due to the injection of the P-type ions; injecting N-type ions, forming an N + source region in the P well, forming a plurality of P-type doped regions and N-type doping on the P-region at two sides of a grid of a polycrystalline silicon grid region due to the injection of the N-type ions, arranging the P-type doped regions and the N-type doping at intervals in a first direction to form an electrostatic discharge protection diode structure, wherein the first direction is a direction in which the grid extends towards two sides; depositing a dielectric layer on the substrate and the polysilicon gate; carrying out contact hole photoetching and etching to form a contact hole; performing P + implantation on the P well through the contact hole; and forming a metal interconnection layer.
In one embodiment, before the step of implanting P-type ions, a step of performing N-type ion diffusion on the polysilicon gate is further included, and the doping type of the gate of the polysilicon gate region is N-type.
According to the manufacturing method of the power transistor with the electrostatic discharge protection diode structure, the second P + injection which is generally placed after the N + injection and before the dielectric layer is deposited in the traditional power device manufacturing process is adjusted to be performed after the contact hole is etched, so that the deposited dielectric layer can block the influence of the second P + injection on a P-type doped region in the electrostatic discharge protection diode structure and cannot be changed into the P + region, the Igss leakage can be greatly reduced, and the power device with low cost and high reliability can be manufactured.
Drawings
FIG. 1 is a schematic diagram of a planar structure of a power transistor with an ESD protection diode structure in one embodiment;
fig. 2 is a schematic plan view of a gate 31 according to an embodiment;
fig. 3 is a schematic plan view of a gate 31 in another embodiment;
fig. 4 is a schematic plan structure of the device after adding polysilicon gate bars 21 in the active region 2 on the basis of fig. 1;
fig. 5 is a flow chart of a method for manufacturing a power transistor with an esd protection diode structure according to an embodiment.
Detailed Description
To facilitate an understanding of the invention, the invention will now be described more fully with reference to the accompanying drawings. Preferred embodiments of the present invention are shown in the drawings. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.
As used herein, the term semiconductor is a term commonly used by those skilled in the art, for example, for P-type and N-type impurities, to distinguish the doping concentration, P + type represents P-type with heavy doping concentration, P-type represents P-type with medium doping concentration, P-type represents P-type with light doping concentration, N + type represents N-type with heavy doping concentration, N-type represents N-type with medium doping concentration, and N-type represents N-type with light doping concentration.
The power transistor can be a power device such as a vertical double-diffused metal oxide semiconductor field effect transistor (VDMOSFET) and an Insulated Gate Bipolar Transistor (IGBT). Since the gate-source of a power transistor such as a VDMOS is most susceptible to ESD damage, the present invention relates primarily to ESD protection structures between the gate-source.
Fig. 1 is a schematic plan view of a power transistor with an esd protection diode structure in an embodiment, which includes a termination region 1, an active region 2 surrounded by the termination region 1, and a polysilicon gate region 3 located between the termination region 1 and the active region 2, where the polysilicon gate region 3 is separated from a polysilicon gate (not shown in fig. 1) in the active region 2. The polysilicon gate region 3 includes a gate 31 and an esd protection diode structure 32 on both sides of the gate 31, and the gate 31 and the esd protection diode structure 32 are made of polysilicon. Fig. 2 is a schematic plan view of the gate 31 in one embodiment. The esd protection diode structure 32 on both sides of the gate 31 includes a plurality of P-type doped regions and N-type doped regions, which are arranged at intervals in the Y-axis direction of fig. 2, and the Y-axis direction is a direction in which the gate 31 extends toward both sides. Each pair of the P-type doped region and the N-type doped region forms a PN diode. The polysilicon gate region 3 has a first contact hole 321 in the outermost P-type doped region or the outermost N-type doped region on both sides thereof, and a second contact hole 311 in the gate 31. The second contact hole 311 is for connection with the gate metal, and the first contact hole 321 is for connection with the source metal.
According to the power transistor with the electrostatic discharge protection diode structure, the polysilicon gate region 3 is separated from the polysilicon grid bars in the active region 2 to form an independent island structure, the electrostatic discharge protection diode structures 32 are arranged on two sides of the polysilicon gate region 3, the grid 31 is arranged in the middle of the polysilicon gate region, the grid 31 is conveniently led out through the second contact hole 311 to be connected with the grid metal, and batch packaging is facilitated. The PN diode composed of the P-type doped region and the N-type doped region can clamp the forward voltage and the reverse voltage of the gate source at the same time, and the damage of high electrostatic voltage in different directions to the power device is prevented.
Since the operating range of the gate-source bias is 0-20V, the turn-on voltage cannot be less than 20V when designing the inter-gate-source ESD protection structure, so as to prevent the ESD protection diode from being turned on when the power transistor (e.g., VDMOS) normally operates. But the turn-on voltage of the ESD protection device cannot be too large because the ESD protection is not performed if the turn-on voltage is higher than the gate oxide breakdown voltage. The turn-on voltage (total breakdown voltage) Vtrig of the ESD protection diode should therefore be set to satisfy the following principle: vgs < Vtrip < BVox, i.e., greater than the gate-source bias, less than the gate oxide breakdown voltage. In particular, a plurality of polysilicon diodes can be connected in series to increase the turn-on voltage of the ESD protection diode. In one embodiment, the number of the polysilicon diodes is 3 to 6 of the esd protection diode structures 32 on both sides of the gate 31, and the number of the polysilicon diodes can be flexibly set according to the thickness of the gate oxide.
In the embodiment shown in fig. 1, the polysilicon gate region 3 is surrounded by the active region 2 and the terminal region 1, wherein three sides of the polysilicon gate region 3 are surrounded by the active region 2, and the remaining one side is surrounded by the terminal region 1.
In the embodiment shown in fig. 2, the doping type of the gate 31 is N-type, so the outermost doping regions in the esd protection diode structures 32 on both sides of the gate 31 are N-type doping regions. And the N-type doped region has a larger size in the Y-axis direction than the other N-type doped regions due to the first contact hole 321.
In the embodiment shown in fig. 2, the widths of the P-type doped region and the N-type doped region are equal, where the width refers to the direction of the X-axis in fig. 2. The size of each P-type doped region in the Y-axis direction is larger than that of each N-type doped region in the Y-axis direction because the doping concentration of the N-type doped region is larger than that of the P-type doped region.
Fig. 3 is a schematic plan view of a gate 31 in another embodiment. In the embodiment shown in fig. 3, one side a of the gate 31 adjacent to the termination region 1 protrudes outward such that the width of the gate 31 is greater than the width of the P-type doped region and the N-type doped region. In the embodiment, the side b opposite to the side a is flush with the corresponding sides of the P-type doped region and the N-type doped region.
The total length of the P-type doped region and the N-type doped region of the esd protection diode structure 32 affects the magnitude of the HBM (human body model) voltage. The ESD resistance index of a common power device is required to reach more than HBM 2000V. The ESD resistance of the power device is related to the total length of the P-type doped region and the N-type doped region, and the larger the total length is, the greater the ESD resistance is, but the larger the total length is, the larger the gate-source leakage Igss is. For the embodiment in which there are 5 polysilicon diodes in the esd protection diode structures 32 on both sides of the gate 31, when the widths (X-axis direction in fig. 3) of the P-type doped region and the N-type doped region are both 180 micrometers, the HBM can reach 14KV, which is more than enough for HBM voltage requirements, and the width of 180 micrometers is difficult for packaging large dies, which is not suitable for batch packaging. With the structure shown in fig. 3, the protrusion of the gate 31 does not increase the area of the chip, because the transition region between the active region 2 and the termination region 1 is usually 30 to 50 μm outside the gate bar (i.e. outside the edge a) at the edge of the active region 2 of the chip, the gate metal for passing gate voltage is above the transition region, and the termination injection transition region is below the transition region, which has no cell, so that these regions are skillfully utilized to increase the area of the gate bonding region.
The design of the protruding grid 31 can reduce the packaging difficulty, is beneficial to large-scale packaging, and simultaneously can not increase the grid source electric leakage Igss, because the Igss electric leakage of the ESD protection structure is mainly determined by the logarithm of the polysilicon diode and the length of the polysilicon diode, and the treatment of the shape of the polysilicon has no influence on the Igss electric leakage.
Further, in the embodiment shown in fig. 3, the second contact hole 311 is disposed in a region where the side a protrudes outward. The gate region of a power transistor (e.g., a VDMOS) with an ESD diode is typically small. If the second contact hole 311 is disposed at the center of the gate electrode 31 as in fig. 2, the bonding pad of the gate region is generally located at the center of the chip, and the presence of the second contact hole 311 may cause unevenness of the metal surface of the gate region, which may cause difficulty in bonding. In the embodiment shown in fig. 3, the second contact hole 311 is disposed in the region where the edge a protrudes outward, so that a region can be left on the right side of the gate 31 in fig. 3, which is more favorable for performing pressure welding and packaging in the center of the gate metal, and is favorable for performing batch packaging. Further, in the embodiment shown in fig. 3, the cross section of the first contact hole 321 is a long bar shape extending along the X-axis direction, and the cross section of the second contact hole 311 is a long bar shape extending along the Y-axis direction.
Fig. 4 is a schematic plan view of the device after adding polysilicon gate bars 21 in the active region 2, and the dielectric layer, the metal layer and the passivation layer are not shown in fig. 4. The polysilicon gate bar 21 is provided with a third contact hole 22, and the third contact hole 22 is used for connecting with the gate metal. Between dotted lines a and B, and between C and D beside the third contact hole 22 are etched regions of the active region metal. The gate metal and the source metal are separated by the etching region, the gate metal is arranged in the peripheral region of the active region of the dotted lines A and D, and the source metal is arranged in the inner region of the active region of the dotted lines B and C. The polysilicon gate region 3 is separated from the active region 2 as a small island structure, so that the short circuit of the gate source can be avoided. Because if the esd protection diode structure 32 is connected to the polysilicon gate bar 21, since the first contact hole 321 is connected to the source region metal, the esd protection diode structure 32 and the polysilicon gate bar 21 are both connected to the source, and the polysilicon gate bar 21 is connected to the gate through the third contact hole 22, which causes the gate-source short circuit and the turn-on voltage V TH Zero, gate-source breakdown voltage VgsAt zero, the gate-source leakage Igss fails (Over). This structure of independent islands of polysilicon gate regions 3 is true for stripe cells, which should be noted for stripe cells.
The invention also provides a manufacturing method of the power transistor with the electrostatic discharge protection diode structure. Fig. 5 is a flow chart of a method for manufacturing a power transistor with an esd protection diode structure in an embodiment, including the following steps:
and S110, forming a field oxide layer and a gate oxide layer on the substrate.
The gate oxide of the active region may be prepared after forming the P-type field limiting ring of the termination region (formed by P + implantation, which is referred to as first P + implantation in this specification) and performing the field oxide etching of the active region. In one embodiment, the gate oxide is grown by thermal oxidation. The gate oxide can be grown by a dry oxygen process or a dry-wet-dry (dry oxygen-wet oxygen-dry oxygen) process.
And S120, depositing polysilicon on the gate oxide layer and/or the field oxide layer to form a polysilicon gate.
In this embodiment, polysilicon is deposited, N-type ion diffusion (in other embodiments, N-type ion implantation may be performed on the polysilicon) is performed on the polysilicon, the N-type ion may be a phosphorus ion, and then photolithography and etching are performed on the polysilicon to form a polysilicon gate. Referring to fig. 4, the polysilicon gate here includes a polysilicon gate region 3 and polysilicon gate bars 21. The polysilicon gate region 3 is specifically arranged on the field oxide layer or the gate oxide layer, and can be flexibly selected according to different process flows of various companies.
S130, injecting P-type ions, forming a P well in the substrate, and forming a P-region in the polycrystalline silicon gate region due to the injection of the P-type ions.
P-type impurity ions are implanted and diffused to form a P-well, and a P-region is formed in the esd protection diode structure 32 region on both sides of the gate 31 by the implantation.
S140, injecting N-type ions, forming an N + source region in the P well, and forming an ESD protection diode structure in the polysilicon gate region.
In this step, when injecting N-type ions (N + injection), the photoresist covers the positions of the P-type doped regions in the esd protection diode structure 32, so that no N-type impurity is injected into these regions, and therefore, after the N-type ions are injected, the P-type doped regions and the N-type doped regions on both sides of the gate 31 are arranged at intervals in the first direction to form the esd protection diode structure 32. Since the photoresist covered by the P-type doped region in the ESD protection diode structure 32 and the N + photoresist of the N + source region injection blocking layer are formed in the same layer of lithography, the process is compatible with the conventional power device (without the ESD protection diode structure) manufacturing process, and no lithography layer is added. Compared with the traditional manufacturing method of the power device with the ESD protection structure, the method reduces one photoetching level, thereby reducing the manufacturing cost.
S150, depositing a dielectric layer on the substrate and the polysilicon gate.
In this embodiment, a double-layer structure of Undoped Silicate Glass (USG) and phosphosilicate glass (PSG) is used as the dielectric layer. In other embodiments, other conventional dielectric layer materials and other structures (e.g., a single layer dielectric layer structure) may be used.
And S160, carrying out contact hole photoetching and etching to form a contact hole.
The contact hole includes: a second contact hole 311 for connecting to a gate metal; a first contact hole 321 for connecting with a source metal; and a third contact hole 22 for connection with the gate metal.
And S170, performing P + implantation on the P trap through the contact hole.
After the contact holes are formed, the regions of the P-wells under the corresponding contact holes are exposed, so that P + implantation can be performed on the P-wells through the contact holes. In order to reduce the problem of large gate source Igss leakage in the conventional ESD protection structure, in this embodiment, the second P + implantation, which is generally performed between steps S140 and S150 in the conventional power device manufacturing process, is adjusted to be performed after the contact hole is etched, so that the dielectric layer deposited in step S150 can block the influence of the second P + implantation on the P-type doped region in the ESD protection diode structure 32, and does not become a P + region, thereby greatly reducing Igss leakage, and thus manufacturing a low-cost and high-reliability power device.
And S180, forming a metal interconnection layer.
After filling the contact hole with a metal (e.g., tungsten), a front metal layer is formed on the dielectric layer. After the step is finished, the steps of forming a passivation layer on the front metal layer, performing a back process of the power transistor and the like can be performed.
The above-mentioned embodiments only express several embodiments of the present invention, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the inventive concept, which falls within the scope of the present invention. Therefore, the protection scope of the present patent shall be subject to the appended claims.
Claims (7)
1. A power transistor with an electrostatic discharge protection diode structure comprises a terminal region and an active region surrounded by the terminal region, and is characterized by further comprising a polycrystalline silicon gate region located between the terminal region and the active region, wherein the polycrystalline silicon gate region is separated from a polycrystalline silicon gate in the active region, the polycrystalline silicon gate region comprises a gate and the electrostatic discharge protection diode structures on two sides of the gate, the gate and the electrostatic discharge protection diode structures are made of polycrystalline silicon, the electrostatic discharge protection diode structures on two sides of the gate comprise a plurality of P-type doped regions and a plurality of N-type doped regions, the P-type doped regions and the N-type doped regions are arranged at intervals in a first direction, and the first direction is a direction in which the gate extends towards two sides; the P-type doped region or the N-type doped region positioned at the outermost part of two sides of the polycrystalline silicon gate region is provided with a first contact hole, and the gate is provided with a second contact hole; the polysilicon gate region is surrounded by the active region and the terminal region, three sides of the polysilicon gate region are surrounded by the active region, the remaining side is surrounded by the terminal region, the widths of the P-type doped regions and the N-type doped regions are equal, the width direction is a second direction perpendicular to the first direction, and the first edge of the gate adjacent to the terminal region protrudes outwards to enable the width of the gate to be larger than the widths of the P-type doped regions and the N-type doped regions.
2. The power transistor with esd protection diode structure according to claim 1, wherein the doping type of the gate is N-type.
3. The power transistor with esd protection diode structure according to claim 1, wherein the second contact hole is disposed in a region where the first edge protrudes outward.
4. The power transistor with esd protection diode structure as claimed in claim 3, wherein the cross section of the first contact hole is elongated along the second direction, and the cross section of the second contact hole is elongated along the first direction.
5. The power transistor with esd protection diode structure of claim 1, wherein a doping concentration of each P-type doped region is less than a doping concentration of each N-type doped region, and a dimension of each P-type doped region in the first direction is greater than a dimension of each N-type doped region in the first direction.
6. A method of manufacturing a power transistor with an esd protection diode structure, comprising:
forming a field oxide layer and a gate oxide layer on a substrate;
depositing polysilicon on the gate oxide layer and/or the field oxide layer to form a polysilicon gate; the polycrystalline silicon grid comprises a polycrystalline silicon grid bar of an active region and a polycrystalline silicon grid region positioned between the active region and a terminal region, and the polycrystalline silicon grid region is separated from the polycrystalline silicon grid bar in the active region;
injecting P-type ions, forming a P well in the substrate, and forming a P-region in the polysilicon gate region due to the injection of the P-type ions;
injecting N-type ions, forming an N + source region in the P well, forming a plurality of P-type doped regions and N-type doped regions on two sides of a grid of a polycrystalline silicon grid region due to N-type ion injection in the P-region, arranging the P-type doped regions and the N-type doped regions at intervals in a first direction to form an electrostatic discharge protection diode structure, wherein the first direction is a direction in which the grid extends towards two sides;
depositing a dielectric layer on the substrate and the polysilicon gate;
carrying out contact hole photoetching and etching to form a contact hole;
performing P + injection on the P well through the contact hole;
forming a metal interconnection layer;
the polycrystalline silicon gate region is surrounded by the active region and the terminal region, three faces of the polycrystalline silicon gate region are surrounded by the active region, the remaining face is surrounded by the terminal region, the widths of the P-type doped region and the N-type doped region are equal, the width direction is a second direction perpendicular to the first direction, and the first edge of the gate adjacent to the terminal region protrudes outwards to enable the width of the gate to be larger than the widths of the P-type doped region and the N-type doped region.
7. The method as claimed in claim 6, further comprising a step of N-type ion diffusion for the polysilicon gate, wherein the doping type of the gate of the polysilicon gate region is N-type, before the step of implanting P-type ions.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610528260.5A CN106024634B (en) | 2016-07-06 | 2016-07-06 | Power transistor with electrostatic discharge protection diode structure and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610528260.5A CN106024634B (en) | 2016-07-06 | 2016-07-06 | Power transistor with electrostatic discharge protection diode structure and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN106024634A CN106024634A (en) | 2016-10-12 |
| CN106024634B true CN106024634B (en) | 2022-11-18 |
Family
ID=57107015
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201610528260.5A Active CN106024634B (en) | 2016-07-06 | 2016-07-06 | Power transistor with electrostatic discharge protection diode structure and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN106024634B (en) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109755313B (en) * | 2017-11-06 | 2024-02-20 | 华润微集成电路(无锡)有限公司 | LDMOS device and circuit for improving electrostatic discharge capacity of high-voltage starting circuit |
| CN109360807A (en) * | 2018-09-14 | 2019-02-19 | 福建省福芯电子科技有限公司 | The integrated preparation method for exhausting reinforced pipe |
| CN110739303B (en) * | 2019-10-30 | 2020-11-06 | 珠海迈巨微电子有限责任公司 | Trench VDMOS device integrated with ESD protection and manufacturing method |
| CN111508950B (en) * | 2020-04-09 | 2022-07-29 | 中国电子科技集团公司第五十五研究所 | Silicon carbide MOSFET device with integrated electrostatic protection capability and manufacturing method thereof |
| CN113690297B (en) * | 2021-08-25 | 2023-07-28 | 厦门市三安集成电路有限公司 | Nitride device and method for manufacturing the same |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002118258A (en) * | 2000-10-10 | 2002-04-19 | Sanyo Electric Co Ltd | Mosfet and protective circuit device using that |
| CN102891143A (en) * | 2012-10-12 | 2013-01-23 | 成都芯源系统有限公司 | Semiconductor device having electrostatic discharge protection module and method of manufacturing the same |
| CN105470309A (en) * | 2016-01-06 | 2016-04-06 | 无锡新洁能股份有限公司 | Low-voltage MOSFET device with antistatic protection structure and manufacturing method therefor |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002208702A (en) * | 2001-01-10 | 2002-07-26 | Mitsubishi Electric Corp | Power semiconductor device |
| US7902604B2 (en) * | 2009-02-09 | 2011-03-08 | Alpha & Omega Semiconductor, Inc. | Configuration of gate to drain (GD) clamp and ESD protection circuit for power device breakdown protection |
| US9728529B2 (en) * | 2014-04-14 | 2017-08-08 | Infineon Technologies Dresden Gmbh | Semiconductor device with electrostatic discharge protection structure |
-
2016
- 2016-07-06 CN CN201610528260.5A patent/CN106024634B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002118258A (en) * | 2000-10-10 | 2002-04-19 | Sanyo Electric Co Ltd | Mosfet and protective circuit device using that |
| CN102891143A (en) * | 2012-10-12 | 2013-01-23 | 成都芯源系统有限公司 | Semiconductor device having electrostatic discharge protection module and method of manufacturing the same |
| CN105470309A (en) * | 2016-01-06 | 2016-04-06 | 无锡新洁能股份有限公司 | Low-voltage MOSFET device with antistatic protection structure and manufacturing method therefor |
Also Published As
| Publication number | Publication date |
|---|---|
| CN106024634A (en) | 2016-10-12 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP2988871B2 (en) | Trench gate power MOSFET | |
| CN106024634B (en) | Power transistor with electrostatic discharge protection diode structure and manufacturing method thereof | |
| US8878283B2 (en) | Quasi-vertical gated NPN-PNP ESD protection device | |
| KR100638456B1 (en) | Esd protection circuit and method for manufacturing the same | |
| CN103219364B (en) | Semiconductor device and manufacture method thereof | |
| WO2014156849A1 (en) | Semiconductor device | |
| CN109659351B (en) | Insulated gate bipolar transistor | |
| CN110867487B (en) | Silicon controlled rectifier and manufacturing method thereof | |
| CN107301994B (en) | Transient Voltage Suppressor and preparation method thereof | |
| CN106601731B (en) | Semiconductor structure with ESD protection structure and manufacturing method thereof | |
| CN112820776A (en) | MOSFET device with improved anti-static capability and manufacturing method thereof | |
| CN104409454B (en) | A kind of NLDMOS antistatic protections pipe | |
| CN101901830B (en) | Forward and reverse conduction lateral insulated gate bipolar transistor of silicon on insulator | |
| CN105870078A (en) | Chip structure for effectively increasing PN junction area and manufacturing method thereof | |
| KR101570483B1 (en) | Power semiconductor device having diode element device for transient voltage protection and method of manufacture thereof | |
| CN112201688A (en) | Reverse conducting IGBT chip | |
| KR100928653B1 (en) | Semiconductor device and method for manufacturing thereof | |
| CN109065541B (en) | Bidirectional transient voltage suppressor and preparation method thereof | |
| US4520382A (en) | Semiconductor integrated circuit with inversion preventing electrode | |
| US20220216331A1 (en) | Semiconductor device and method for designing thereof | |
| CN215815877U (en) | High-maintenance high-failure bidirectional thyristor electrostatic protection device | |
| US7023028B2 (en) | Protection structure for protection from electrostatic discharge and integrated circuit | |
| US8704270B2 (en) | Shockley diode having a low turn-on voltage | |
| JP2018133493A (en) | Semiconductor device | |
| CN205984999U (en) | Take power transistor of electrostatic discharge protective diode structure |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |