CN110739303B - Trench VDMOS device integrated with ESD protection and manufacturing method - Google Patents
Trench VDMOS device integrated with ESD protection and manufacturing method Download PDFInfo
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- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
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Abstract
The invention provides a Trench VDMOS device integrated with ESD protection and a manufacturing method thereof, wherein the device comprises a Trench VDMOS structure and an ESD protection structure; the Trench VDMOS structure comprises a cell region and a terminal protection region, wherein the terminal protection region adopts a groove structure and comprises a stop ring and at least one voltage division ring, the ESD protection structure comprises a plurality of Zener diode units, the ESD protection structure is connected to two ends of grid metal and source metal, the Trench VDMOS reduces the specific on-resistance of the Trench VDMOS by reducing the cell pitch and increasing the contact area of the source metal and a first conductive type source electrode, and the ESD protection structure is positioned on a hard mask SiO2The active region photoetching mask is isolated from the Trench VDMOS unit and is compatible with a Trench VDMOS manufacturing process, and on the premise of not influencing the performance of a device, the active region photoetching mask is reduced, and the manufacturing cost is reduced.
Description
Technical Field
The invention belongs to the technical field of semiconductor power devices, and relates to a Trench VDMOS device integrated with ESD protection and a manufacturing method thereof.
Background
The trench power MOS device has the characteristics of high integration level, low on-resistance, high switching speed and small switching loss, is widely applied to various power supply management and switching conversion, and has wide development and application prospects. For the groove power MOS, the specific on-resistance can be obviously reduced by reducing the cell pitch, but the size of the groove power MOS cannot be further reduced by limiting the size and the alignment deviation of a contact hole, and meanwhile, as the cell pitch is reduced, the contact resistance of a device source electrode is increased, so that the total on-resistance of the power MOS is influenced.
The thickness of the gate oxide layer of the trench power MOS is relatively thin, and the structural characteristic determines that the trench power MOS device is an electrostatic sensitive device. With the continuous improvement of the process level and the great improvement of the trench power MOS device process, the device size is continuously reduced, and the gate oxide thickness is also thinner and thinner, which is more unfavorable for the electrostatic discharge (ESD) endurance of the device. Therefore, the capability of improving the electrostatic discharge protection of the trench power MOS device has a considerable effect on improving the reliability of the product. Failures caused by ESD problems include both destructive and potential failures. The destructive failure can cause the oxide layer, PN junction, even insulation layer breakdown and the like of the device, so that the device completely loses functions and cannot work normally; the latent failure does not directly destroy the functionality of the device, but causes damage inside the device, thereby weakening the electric overstress resistance of the device, shortening the service life of the device and the like, and affecting the reliability of an application circuit of the device.
Currently, common ESD protection structures include Silicon Controlled Rectifiers (SCRs), grounded-gate nmos (ggnmos), grounded-gate pmos (ggpmos), polysilicon/bulk silicon diodes, resistors, and the like. Such ESD protection structures are often used in I/O protection structures for integrated circuits and are rarely used in discrete components. Although the process implementation of the diode formed by polysilicon/bulk silicon and the ESD protection structures such as bulk silicon diodes is simple, the defects of large drain-source current, obvious parasitic effect, large substrate coupling noise and the like exist, the device can be damaged, and the normal operation of the device is not facilitated.
Disclosure of Invention
The invention aims to provide an integrated ESD protection Trench VDMOS device and a manufacturing method thereof, which overcome the defects of the existing ESD protection structure.
In order to solve the technical problems, the technical scheme adopted by the invention is as follows:
a Trench VDMOS device integrating ESD protection comprises a Trench VDMOS structure and an ESD protection structure;
the Trench VDMOS structure comprises a cell area and a terminal protection area, wherein the cell area comprises a plurality of cells which are identical in structure and are sequentially connected, the cell area comprises a first conduction type substrate 11, a first conduction type drift area 12 positioned on the first conduction type substrate 11, a second conduction type well area 21 positioned above the first conduction type drift area 12, a first conduction type source contact area 13 positioned above the second conduction type well area 21 and a second conduction type source contact area 22, a source metal 51 is positioned above a metal front medium 32 and is contacted with the second conduction type source contact area 22 and the first conduction type source contact area 13, and the cell area also comprises a first deep groove 1 extending into the first conduction type drift area 12, the gate dielectric layer 31 and the polysilicon filler 41 are positioned in the first deep groove 1, and the metal front dielectric 32 is positioned above the polysilicon filler 41;
the terminal protection region is of a trench structure and comprises a stop ring and at least one voltage division ring, the terminal protection region comprises a gate dielectric layer 31 and a polysilicon filler 41 in a second deep groove 2 and a third deep groove 3, a metal front dielectric 32 above the polysilicon filler 41 and above a second conductive type well region 21, and a stop ring metal 54 which is positioned above the metal front dielectric 32 and is in contact with the polysilicon filler 41 in the third deep groove 3 and a first conductive type contact region 15 in the second conductive type well region 21; the upper surface of the polysilicon filling 41 of the cell region and the terminal protection region is higher than the upper surface of the second conductivity type well region 21, and the lower surface of the polysilicon filling 41 is lower than the upper surface of the first conductivity type drift region 12;
the ESD protection structure comprises a number of zener diode cells, which are connected across the gate metal 52 and the source metal 51.
Preferably, the second conductive-type source contact regions 22 are arranged at intervals from the first conductive-type source contact regions 13 in the y direction, which is parallel to the length direction of the first deep trenches.
Preferably, the polysilicon filling 41 located inside the second deep trench 2 is in a floating state.
Preferably, the lower surface of the source metal 51 is lower than the upper surface of the first conductive type source contact region 13.
Preferably, the doping concentration of the first conductive type source contact region 13 is higher than the doping concentration of the second conductive type source contact region 22.
Preferably, the third deep groove 3 has a width larger than the widths of the first deep groove 1 and the second deep groove 2.
Preferably, the extending end of the first deep trench 1 is a circular lead terminal with a diameter larger than the width of the first deep trench 1, or a polygonal lead terminal with a side length larger than the width of the first deep trench 1, and the gate electrode lead hole is opened at the lead terminal position, so that the metal is connected with the polysilicon inside the first deep trench 1.
Preferably, the ESD protection structure is located above the hard mask dielectric layer 33, and includes a first conductivity type polysilicon region 14, a second conductivity type polysilicon region 23, and a metal front dielectric 32 located on a surface of the polysilicon, where the first conductivity type polysilicon region 14 and the second conductivity type polysilicon region 23 are arranged at an interval.
Preferably, the source metal 51 and the gate metal 52 are located above the metal front dielectric and in contact with the second conductivity type polysilicon region 23.
Preferably, the first conductive-type source contact region 13 is disposed above the second conductive-type source contact region 22.
Preferably, a metal silicide 00 is disposed above the first conductive type source contact region 13.
Preferably, the method is characterized in that: the first conductive type is N type, and the second conductive type is P type; or the first conductive type is P type, and the second conductive type is N type.
The invention also provides a manufacturing method of the integrated ESD protection Trench VDMOS device, which comprises the following steps:
step 4, forming a deep groove by adopting photoetching and etching processes;
step 5, thermally growing to form a gate dielectric layer 31;
step 6, depositing polycrystalline silicon, and etching the polycrystalline silicon to form a gate electrode;
step 9, forming a first conductive type source contact region 13 and a first conductive type polysilicon region 14 by first conductive type ion implantation;
step 10, depositing a dielectric layer, and forming a metal contact groove by adopting a photoetching process;
and step 13, thinning the substrate, and metalizing the back to form drain metal 53.
The invention also provides a second manufacturing method of the integrated ESD protection Trench VDMOS device, which comprises the following steps:
step 4, thermally growing to form a gate dielectric layer 31;
step 5, depositing polycrystalline silicon, and etching the polycrystalline silicon to form a gate electrode;
step 6, forming a second conductive type well region 21 by injecting second conductive type ions;
step 9, forming a first conductive type source contact region 13 and a first conductive type polysilicon region 14 by first conductive type ion implantation;
step 10, depositing a dielectric layer, and forming a metal contact groove by adopting a photoetching process;
and step 13, thinning the substrate, and metalizing the back to form drain metal 53. The invention has the beneficial effects that: the Trench VDMOS reduces the specific on-resistance of the Trench VDMOS by reducing the cell pitch and increasing the contact area of the source metal and the first conductive type source, and the ESD protection structure is positioned on the SiO of the hard mask2The Trench VDMOS unit is isolated from the Trench VDMOS unit and is compatible with a Trench VDMOS manufacturing process, and on the premise of not influencing the performance of a device, the active area photolithography mask is reduced, and the manufacturing cost is reduced.
Drawings
Fig. 1 is a schematic top plan view of a Trench VDMOS integrated with ESD protection according to embodiment 1 of the present invention.
Fig. 2 is a three-dimensional schematic diagram of a Trench VDMOS cell.
Fig. 3 is a cross-sectional view of a-a ', b-b' of fig. 2.
Fig. 4 is a sectional view a-a' of fig. 1.
Fig. 5 is a sectional view B-B' of fig. 1.
Fig. 6 is a cross-sectional view of C-C' of fig. 1.
Fig. 7 is a cross-sectional view of a Trench VDMOS provided in embodiment 2 of the present invention.
Fig. 8 is a cross-sectional view of a Trench VDMOS provided in embodiment 3 of the present invention.
FIGS. 9(a) -9(i) are process flow diagrams of the manufacturing method of example 1 of the present invention.
00 is a metal silicide, 1 is a first deep trench, 2 is a second deep trench, 3 is a third deep trench, 11 is a first conductive type substrate, 12 is a first conductive type drift region, 13 is a first conductive type source contact region, 14 is a first conductive type polysilicon region, 15 is a first conductive type contact region, 21 is a second conductive type well region, 22 is a second conductive type source contact region, 23 is a second conductive type polysilicon region, 31 is a gate dielectric layer, 32 is a metal front dielectric, 33 is a hard mask dielectric layer, 41 is a polysilicon filler, 51 is a source metal, 52 is a gate metal, 53 is a drain metal, and 54 is a stop ring metal.
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
Example 1
A Trench VDMOS device integrating ESD protection comprises a Trench VDMOS structure and an ESD protection structure;
the Trench VDMOS structure comprises a cell area and a terminal protection area, wherein the cell area comprises a plurality of cells which are identical in structure and are sequentially connected, the cell area comprises a first conduction type substrate 11, a first conduction type drift area 12 positioned on the first conduction type substrate 11, a second conduction type well area 21 positioned above the first conduction type drift area 12, a first conduction type source contact area 13 positioned above the second conduction type well area 21 and a second conduction type source contact area 22, a source metal 51 is positioned above a metal front medium 32 and is contacted with the second conduction type source contact area 22 and the first conduction type source contact area 13, and the cell area also comprises a first deep groove 1 extending into the first conduction type drift area 12, the gate dielectric layer 31 and the polysilicon filler 41 are positioned in the first deep groove 1, and the metal front dielectric 32 is positioned above the polysilicon filler 41;
the terminal protection region is of a trench structure and comprises a stop ring and at least one voltage division ring, the terminal protection region comprises a gate dielectric layer 31 and a polysilicon filler 41 in a second deep groove 2 and a third deep groove 3, a metal front dielectric 32 above the polysilicon filler 41 and above a second conductive type well region 21, and a stop ring metal 54 which is positioned above the metal front dielectric 32 and is in contact with the polysilicon filler 41 in the third deep groove 3 and a first conductive type contact region 15 in the second conductive type well region 21; the upper surface of the polysilicon filling 41 of the cell region and the terminal protection region is higher than the upper surface of the second conductivity type well region 21, and the lower surface of the polysilicon filling 41 is lower than the upper surface of the first conductivity type drift region 12;
the ESD protection structure comprises a number of zener diode cells, which are connected across the gate metal 52 and the source metal 51.
Fig. 1 is a top plan view of a Trench VDMOS device with integrated ESD protection. As can be seen from the figure, the central area of the MOS device is provided with a strip-shaped cellular array, the periphery of the cellular is provided with a terminal protection ring, and the ESD protection structure is positioned below the gate Pad. The terminal protection ring is composed of a voltage division ring positioned at the inner ring and a stop ring positioned at the outer ring. The voltage division ring is two in the embodiment, but one or more than two protection ring structures can also be adopted, which needs to be determined according to the breakdown voltage required by the Trench VDMOS.
Fig. 2 is a three-dimensional schematic diagram of a Trench VDMOS cell, fig. 3 is a cross-sectional view a-a 'and b-b' of fig. 2, and as can be seen from fig. 2-3, a first deep Trench 1 is located in a second conductive well 21 and has a depth deeper than a first conductive drift region 12 under the second conductive well 21, a gate dielectric layer 31 is grown on a sidewall surface of the first deep Trench 1 by thermal oxidation, a polysilicon filling 41 is deposited in the Trench, and a top of the Trench is covered by a metal front dielectric 32. The second conductive-type source contact regions 22 are arranged at intervals from the first conductive-type source contact regions 13 in the y direction, which is parallel to the length direction of the first deep trenches. The lower surface of the source metal 51 is lower than the upper surface of the first conductive type source contact region 13.
Fig. 4 is a cross-sectional view a-a' of fig. 1, which is a cross-sectional view of a Trench VDMOS device according to an embodiment of the invention. As can be seen from the figure, the voltage division ring adopts a trench structure, the second deep trench 2 is located in the second conductive type well region 21, the depth of the second deep trench is deep into the first conductive type drift region 12 below the second conductive type well region 21, the gate dielectric layer 31 is grown on the surface of the side wall of the second deep trench 2 through thermal oxidation, the polysilicon filler 41 is deposited in the trench, the top of the trench is covered by the metal front dielectric 32, and the polysilicon filler 41 in the second deep trench 2 is in a floating state, so as to form the terminal voltage division ring. The groove width of the third deep groove 3 is larger than the width of the first deep groove 1 and the second deep groove 2. The third deep trench 3 is located in the second conductive type well region 21, the depth of the third deep trench extends into the first conductive type drift region 12 below the second conductive type well region 21, a gate dielectric layer 31 is grown on the surface of the side wall of the third deep trench 3 through thermal oxidation, a polysilicon filler 41 is deposited in the trench, a stop ring metal 54 is arranged at the top of the deep trench, and the stop ring metal 54 connects the polysilicon filler 41 in the third deep trench 3 and the second conductive type well region 21 at the outer ring of the third deep trench 3 to be equipotential to form a stop ring.
Fig. 5 is a cross-sectional view of B-B' of fig. 1, in which the extended end of the first deep trench 1 is a circular lead terminal having a diameter larger than the width of the first deep trench 1 or a polygonal lead terminal having a side length larger than the width of the first deep trench 1, and a gate electrode lead hole is opened at the lead terminal position so that metal is connected to the polysilicon inside the first deep trench 1.
Fig. 6 is a cross-sectional view of C-C' of fig. 1, which is a schematic view of an ESD protection structure according to an embodiment of the present invention, the ESD protection structure is located above a hard mask dielectric layer 33, and includes a first conductivity type polysilicon region 14, a second conductivity type polysilicon region 23, and a metal front dielectric 32 located on a polysilicon surface, wherein the first conductivity type polysilicon region 14 and the second conductivity type polysilicon region 23 are arranged at an interval. The source metal 51 and gate metal 52 are located over the pre-metal dielectric in contact with the second conductivity type polysilicon region 23.
Preferably, the first conductivity type is N-type and the second conductivity type is P-type, or the first conductivity type is P-type and the second conductivity type is N-type.
The basic working principle of example 1 is as follows:
when the gate voltage is greater than the threshold voltage and less than the ESD protection structure trigger voltage, an inversion layer appears in a region of the second conductivity type well region 21 close to the gate dielectric layer 31, and under the action of the drain voltage, an electron path is formed along the source metal 51-the first conductivity type source contact region 13-the inversion layer of the second conductivity type well region 21-the first conductivity type drift region 12-the first conductivity type substrate 11-the drain metal 53. In order to further reduce the specific on-resistance of the device, the specific on-resistance of the Trench VDMOS can be further reduced by reducing the cell pitch, which is limited by the overlay deviation and the size of the contact hole cannot be further reduced, and the invention further reduces the specific on-resistance of the Trench VDMOS by disposing the second conductivity type source contact region 22 at the cross section perpendicular to the second conductivity type well region 21 to reduce the cell pitch, disposing the lower surface of the source metal to be lower than the upper surface of the first conductivity type source contact region 13 to increase the source contact area. Meanwhile, the doping concentration of the first conductive type source electrode contact region 13 is higher than that of the second conductive type source electrode contact region 22, so that the Trench VDMOS device with lower specific on-resistance is realized under the condition that a mask is not increased.
When the grid voltage is greater than the trigger voltage of the ESD protection structure, the current passes through the grid metal 52, the ESD protection structure and the source metal 51, the grid oxide layer is prevented from being broken down by high voltage, and the reliability of the Trench VDMOS is improved.
As shown in fig. 9(a) -9(i), this embodiment further provides a method for manufacturing the above-mentioned Trench VDMOS device with integrated ESD protection, including the following steps:
step 4, forming a deep groove by adopting photoetching and etching processes;
step 5, thermally growing to form a gate dielectric layer 31;
step 6, depositing polycrystalline silicon, and etching the polycrystalline silicon to form a gate electrode;
step 9, forming a first conductive type source contact region 13 and a first conductive type polysilicon region 14 by first conductive type ion implantation;
step 10, depositing a dielectric layer, and forming a metal contact groove by adopting a photoetching process;
and step 13, thinning the substrate, and metalizing the back to form drain metal 53.
Example 2
Example 3
Fig. 8 is a cross-sectional view of a Trench VDMOS provided in embodiment 3, which is different from embodiment 2 in that a metal silicide 00 is disposed above the first conductive type source contact region 13.
Example 4
The embodiment provides a manufacturing method of a Trench VDMOS device integrated with ESD protection, which includes the following steps:
step 4, thermally growing to form a gate dielectric layer 31;
step 5, depositing polycrystalline silicon, and etching the polycrystalline silicon to form a gate electrode;
step 6, forming a second conductive type well region 21 by injecting second conductive type ions;
step 9, forming a first conductive type source contact region 13 and a first conductive type polysilicon region 14 by first conductive type ion implantation;
step 10, depositing a dielectric layer, and forming a metal contact groove by adopting a photoetching process;
and step 13, thinning the substrate, and metalizing the back to form drain metal 53.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (13)
1. The utility model provides a integrated ESD protected Trench VDMOS device which characterized in that: the ESD protection structure comprises a Trench VDMOS structure and an ESD protection structure;
the Trench VDMOS structure comprises a cell area and a terminal protection area, wherein the cell area comprises a plurality of cells which are identical in structure and are connected in sequence, the cell area comprises a first conduction type substrate (11), a first conduction type drift area (12) positioned on the first conduction type substrate (11), a second conduction type well area (21) positioned above the first conduction type drift area (12), a first conduction type source contact area (13) and a second conduction type source contact area (22) positioned on the second conduction type well area (21), the first conduction type source contact area (13) is arranged above the second conduction type source contact area (22), a source metal (51) is positioned above a metal front medium (32) and is contacted with the second conduction type source contact area (22) and the first conduction type source contact area (13), and the cell area further comprises a first deep groove (1) extending into the first conduction type drift area (12), the gate dielectric layer (31) and the polysilicon filling material (41) are positioned in the first deep groove (1), and the metal front dielectric (32) is positioned above the polysilicon filling material (41);
the terminal protection region is of a trench structure and comprises a stop ring and at least one voltage division ring, the terminal protection region comprises a gate dielectric layer (31) and a polysilicon filler (41) in a second deep groove (2) and a third deep groove (3), a metal front dielectric (32) above the polysilicon filler (41) and above a second conductive type well region (21), and a stop ring metal (54) which is positioned above the metal front dielectric (32) and is in contact with the polysilicon filler (41) in the third deep groove (3) and a first conductive type contact region (15) in the second conductive type well region (21); the upper surface of a polysilicon filling (41) of the cellular region and the terminal protection region is higher than the upper surface of the second conductive type well region (21), and the lower surface of the polysilicon filling (41) is lower than the upper surface of the first conductive type drift region (12);
the ESD protection structure comprises a plurality of Zener diode units, and is connected to two ends of the grid metal (52) and the source metal (51).
2. The integrated ESD protected Trench VDMOS device of claim 1, wherein: the second conductive type source contact regions (22) are arranged at intervals from the first conductive type source contact regions (13) in the y direction, which is parallel to the length direction of the first deep trenches.
3. The integrated ESD protected Trench VDMOS device of claim 1, wherein: the polysilicon filling (41) in the second deep groove (2) is in a floating state.
4. The integrated ESD protected Trench VDMOS device of claim 1, wherein: the lower surface of the source metal (51) is lower than the upper surface of the first conductive type source contact region (13).
5. The integrated ESD protected Trench VDMOS device of claim 1, wherein: the doping concentration of the first conductivity type source contact region (13) is higher than the doping concentration of the second conductivity type source contact region (22).
6. The integrated ESD protected Trench VDMOS device of claim 1, wherein: the width of the third deep groove (3) is larger than the width of the first deep groove (1) and the second deep groove (2).
7. The integrated ESD protected Trench VDMOS device of claim 1, wherein: the extension end of the first deep groove (1) is a circular lead terminal with the diameter larger than the width of the first deep groove (1) or a polygonal lead terminal with the side length larger than the width of the first deep groove (1), and a gate electrode lead hole is formed in the position of the lead terminal, so that metal is connected with polycrystalline silicon in the first deep groove (1).
8. The integrated ESD protected Trench VDMOS device of claim 1, wherein: the ESD protection structure is located above the hard mask dielectric layer (33) and comprises a first conduction type polycrystalline silicon region (14), a second conduction type polycrystalline silicon region (23) and a metal front dielectric (32) located on the surface of polycrystalline silicon, wherein the first conduction type polycrystalline silicon region (14) and the second conduction type polycrystalline silicon region (23) are arranged at intervals.
9. The integrated ESD protected Trench VDMOS device of claim 8, wherein: a source metal (51) and a gate metal (52) are located over the metal front dielectric and in contact with the second conductivity type polysilicon region (23).
10. The integrated ESD protected Trench VDMOS device of claim 1, wherein: a metal silicide (00) is disposed over the first conductivity type source contact region (13).
11. The integrated ESD protected Trench VDMOS device of any one of claims 1 to 10, wherein: the first conductive type is N type, and the second conductive type is P type; or the first conductive type is P type, and the second conductive type is N type.
12. A method of manufacturing a Trench VDMOS device with integrated ESD protection as claimed in any of claims 1 to 9, comprising the steps of:
step 1, a first conductive type substrate (11) is adopted, and a first conductive type drift region (12) is formed in an epitaxial mode;
step 2, forming a second conductive type well region (21) by injecting second conductive type ions;
step 3, thermal growing or depositing SiO2Forming a hard mask dielectric layer (33);
step 4, forming a deep groove by adopting photoetching and etching processes;
step 5, thermally growing to form a gate dielectric layer (31);
step 6, depositing polycrystalline silicon, and etching the polycrystalline silicon to form a gate electrode;
step 7, depositing ESD polycrystalline silicon, injecting second conductive type ions to form a second conductive type polycrystalline silicon area (23), and etching the polycrystalline silicon to form ESD protection polycrystalline silicon;
step 8, etching the hard mask by a dry method to form an active area;
step 9, forming a first conductive type source contact region (13), a first conductive type polycrystalline silicon region (14) by first conductive type ion implantation;
step 10, depositing a dielectric layer, and forming a metal contact groove by adopting a photoetching process;
step 11, forming a second conductive type source contact region (22) by second conductive type ion implantation;
step 12, depositing metal, and forming source metal (51), gate metal (52) and stop ring metal (54) through a photoetching process;
and step 13, thinning the substrate, and metalizing the back to form drain metal (53).
13. A method of manufacturing a Trench VDMOS device with integrated ESD protection as claimed in any of claims 1 to 9, comprising the steps of:
step 1, a first conductive type substrate (11) is adopted, and a first conductive type drift region (12) is formed in an epitaxial mode;
step 2, thermal growth or deposition of SiO2Forming a hard mask dielectric layer (33);
step 3, forming a deep groove by adopting photoetching and etching processes;
step 4, thermally growing to form a gate dielectric layer (31);
step 5, depositing polycrystalline silicon, and etching the polycrystalline silicon to form a gate electrode;
step 6, forming a second conductive type well region (21) by injecting second conductive type ions;
step 7, depositing ESD polycrystalline silicon, injecting second conductive type ions to form a second conductive type polycrystalline silicon area (23), and etching the polycrystalline silicon to form ESD protection polycrystalline silicon;
step 8, etching the hard mask by a dry method to form an active area;
step 9, forming a first conductive type source contact region (13), a first conductive type polycrystalline silicon region (14) by first conductive type ion implantation;
step 10, depositing a dielectric layer, and forming a metal contact groove by adopting a photoetching process;
step 11, forming a second conductive type source contact region (22) by second conductive type ion implantation;
step 12, depositing metal, and forming source metal (51), gate metal (52) and stop ring metal (54) through a photoetching process;
and step 13, thinning the substrate, and metalizing the back to form drain metal (53).
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| CN111490094B (en) * | 2020-04-20 | 2022-08-02 | 中国电子科技集团公司第五十八研究所 | Manufacturing method of trench split gate DMOS device with ESD protection structure |
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