CN110739303A - Trench VDMOS device integrated with ESD protection and manufacturing method - Google Patents
Trench VDMOS device integrated with ESD protection and manufacturing method Download PDFInfo
- Publication number
- CN110739303A CN110739303A CN201911043136.XA CN201911043136A CN110739303A CN 110739303 A CN110739303 A CN 110739303A CN 201911043136 A CN201911043136 A CN 201911043136A CN 110739303 A CN110739303 A CN 110739303A
- Authority
- CN
- China
- Prior art keywords
- region
- conductive type
- metal
- trench
- polysilicon
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 16
- 239000002184 metal Substances 0.000 claims abstract description 97
- 238000001259 photo etching Methods 0.000 claims abstract description 19
- 229910052681 coesite Inorganic materials 0.000 claims abstract description 7
- 229910052906 cristobalite Inorganic materials 0.000 claims abstract description 7
- 239000000377 silicon dioxide Substances 0.000 claims abstract description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 7
- 229910052682 stishovite Inorganic materials 0.000 claims abstract description 7
- 229910052905 tridymite Inorganic materials 0.000 claims abstract description 7
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 93
- 229920005591 polysilicon Polymers 0.000 claims description 73
- 238000000034 method Methods 0.000 claims description 31
- 238000000151 deposition Methods 0.000 claims description 30
- 238000005530 etching Methods 0.000 claims description 24
- 239000000945 filler Substances 0.000 claims description 23
- 230000008569 process Effects 0.000 claims description 22
- 239000000758 substrate Substances 0.000 claims description 21
- 238000005468 ion implantation Methods 0.000 claims description 12
- 150000002500 ions Chemical class 0.000 claims description 12
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 5
- 229910021332 silicide Inorganic materials 0.000 claims description 4
- 230000008021 deposition Effects 0.000 claims description 3
- 230000001413 cellular effect Effects 0.000 claims 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 238000000407 epitaxy Methods 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 230000007547 defect Effects 0.000 description 2
- 230000001066 destructive effect Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000006872 improvement Effects 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 230000009471 action Effects 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 230000003313 weakening effect Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/0203—Particular design considerations for integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7803—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device
Abstract
The invention provides Trench VDMOS devices integrating ESD protection and a manufacturing method thereof, wherein the device comprises a Trench VDMOS structure and an ESD protection structure, the Trench VDMOS structure comprises a cell area and a terminal protection area, the terminal protection area adopts a groove structure and comprises cut-off rings and at least voltage division rings, the ESD protection structure comprises a plurality of Zener diode units, the ESD protection structure is connected with two ends of a grid metal and a source metal, the Trench VDMOS reduces the cell pitch, increases the contact area of the source metal and a conductive type source electrode, and reduces the specific on-resistance of the Trench VDMOS, and the ESD protection structure is positioned on a hard mask SiO2Isolated from the Trench VDMOS unit and made of Trench VDMOSThe manufacturing process is compatible, and on the premise of not influencing the performance of the device, the number of active region photoetching plates is reduced, and the manufacturing cost is reduced.
Description
Technical Field
The invention belongs to the technical field of semiconductor power devices, and relates to Trench VDMOS devices integrating ESD protection and a manufacturing method thereof.
Background
The trench power MOS device has the characteristics of high integration level, low on-resistance, high switching speed and small switching loss, is widely applied to various power supply management and switching conversion, and has a development and application prospect of . for the trench power MOS, the reduction of the cell pitch can obviously reduce the specific on-resistance, but the size of a contact hole is limited and the alignment deviation is limited, the size of the trench power MOS cannot be reduced by steps, and meanwhile, along with the reduction of the cell pitch, the contact resistance of a device source electrode is increased, and the total on-resistance of the power MOS is influenced.
The thickness of the gate oxide layer of the trench power MOS is relatively thin, and the structural characteristic determines that the trench power MOS device is an electrostatic sensitive device. With the continuous improvement of the process level and the great improvement of the trench power MOS device process, the device size is continuously reduced, and the gate oxide thickness is also thinner and thinner, which is more unfavorable for the electrostatic discharge (ESD) endurance of the device. Therefore, the capability of improving the electrostatic discharge protection of the trench power MOS device has a considerable effect on improving the reliability of the product. Failures caused by ESD problems include both destructive and potential failures. The destructive failure can cause the oxide layer, PN junction, even insulation layer breakdown and the like of the device, so that the device completely loses functions and cannot work normally; the latent failure does not directly destroy the functionality of the device, but causes damage inside the device, thereby weakening the electric overstress resistance of the device, shortening the service life of the device and the like, and affecting the reliability of an application circuit of the device.
Currently, common ESD protection structures include Silicon Controlled Rectifiers (SCRs), grounded-gate nmos (ggnmos), grounded-gate pmos (ggpmos), polysilicon/bulk silicon diodes, resistors, and the like. Such ESD protection structures are often used in I/O protection structures for integrated circuits and are rarely used in discrete components. Although the process implementation of the diode formed by polysilicon/bulk silicon and the ESD protection structures such as bulk silicon diodes is simple, the defects of large drain-source current, obvious parasitic effect, large substrate coupling noise and the like exist, the device can be damaged, and the normal operation of the device is not facilitated.
Disclosure of Invention
The invention aims to provide Trench VDMOS devices with integrated ESD protection and a manufacturing method thereof, which overcome the defects of the existing ESD protection structure.
In order to solve the technical problems, the technical scheme adopted by the invention is as follows:
Trench VDMOS devices integrating ESD protection comprise a Trench VDMOS structure and an ESD protection structure;
the Trench VDMOS structure comprises a cell region and a terminal protection region, wherein the cell region comprises a plurality of cells which are identical in structure and are sequentially connected, the cell region comprises an th conduction type substrate 11, a th conduction type drift region 12 positioned on a th conduction type substrate 11, a second conduction type well region 21 positioned above the th conduction type drift region 12, a th conduction type source contact region 13 and a second conduction type source contact region 22 positioned above the second conduction type well region 21, a source metal 51 positioned above a metal front dielectric 32 and contacted with the second conduction type source contact region 22 and a th conduction type source contact region 13, the Trench VDMOS structure also comprises a deep groove 1 extending into the th conduction type drift region 12, a gate 31 and a polysilicon filler 41 positioned inside the th deep groove 1, and a metal front dielectric 32 positioned above the polysilicon filler 41;
the terminal protection region is of a trench structure and comprises stop rings and at least shunt rings, the terminal protection region comprises a gate dielectric layer 31 and a polysilicon filler 41 in a second deep groove 2 and a third deep groove 3, a metal front dielectric 32 positioned above the polysilicon filler 41 and above a second conductive type well region 21, and a stop ring metal 54 positioned above the metal front dielectric 32 and contacted with the polysilicon filler 41 in the third deep groove 3 and a conductive type contact region 15 in the second conductive type well region 21, wherein the upper surfaces of the polysilicon fillers 41 in the cell region and the terminal protection region are higher than the upper surface of the second conductive type well region 21, and the lower surface of the polysilicon filler 41 is lower than the upper surface of a conductive type drift region 12;
the ESD protection structure comprises a number of zener diode cells, which are connected across the gate metal 52 and the source metal 51.
Preferably, the second conductive type source contact regions 22 are arranged at intervals from the th conductive type source contact regions 13 in the y direction, which is parallel to the length direction of the th deep trench.
Preferably, the polysilicon filling 41 located inside the second deep trench 2 is in a floating state.
Preferably, the lower surface of the source metal 51 is lower than the upper surface of the th conductive type source contact region 13.
Preferably, the doping concentration of the th conductivity type source contact region 13 is higher than the doping concentration of the second conductivity type source contact region 22.
Preferably, the third deep groove 3 has a width larger than the th deep groove 1 and the second deep groove 2.
Preferably, the extension end of the th deep trench 1 is circular lead terminals with diameter larger than th deep trench 1 width or polygonal lead terminals with side length larger than th deep trench 1 width, and gate electrode lead holes are opened at the lead terminal positions to connect the metal with the polysilicon inside th deep trench 1.
Preferably, the ESD protection structure is located above the hard mask dielectric layer 33, and includes an th conductive type polysilicon region 14, a second conductive type polysilicon region 23, and a metal front dielectric 32 located on a polysilicon surface, where the conductive type polysilicon region 14 and the second conductive type polysilicon region 23 are arranged at an interval.
Preferably, the source metal 51 and the gate metal 52 are located above the metal front dielectric and in contact with the second conductivity type polysilicon region 23.
Preferably, th conductive type source contact region 13 is disposed above the second conductive type source contact region 22.
Preferably, a metal silicide 00 is disposed over the th conductive type source contact region 13.
It is preferably characterized in that the th conductivity type is N-type and the second conductivity type is P-type, or the th conductivity type is P-type and the second conductivity type is N-type.
The invention also provides manufacturing methods of the integrated ESD protection Trench VDMOS device, which comprises the following steps:
step 4, forming a deep groove by adopting photoetching and etching processes;
step 5, thermally growing to form a gate dielectric layer 31;
step 6, depositing polycrystalline silicon, and etching the polycrystalline silicon to form a gate electrode;
step 8, etching the hard mask by a dry method to form an active area;
step 9, forming a conductive type source contact region 13 and a conductive type polysilicon region 14 by conductive type ion implantation;
step 10, depositing a dielectric layer, and forming a metal contact groove by adopting a photoetching process;
and step 13, thinning the substrate, and metalizing the back to form drain metal 53.
The invention also provides a second manufacturing method of the integrated ESD protection Trench VDMOS device, which comprises the following steps:
step 4, thermally growing to form a gate dielectric layer 31;
step 5, depositing polycrystalline silicon, and etching the polycrystalline silicon to form a gate electrode;
step 6, forming a second conductive type well region 21 by injecting second conductive type ions;
step 8, etching the hard mask by a dry method to form an active area;
step 9, forming a conductive type source contact region 13 and a conductive type polysilicon region 14 by conductive type ion implantation;
step 10, depositing a dielectric layer, and forming a metal contact groove by adopting a photoetching process;
Drawings
Fig. 1 is a schematic top plan view of kinds of integrated ESD protection Trench VDMOS provided in embodiment 1 of the present invention.
Fig. 2 is a three-dimensional schematic diagram of a Trench VDMOS cell.
Fig. 3 is a cross-sectional view of a-a ', b-b' of fig. 2.
Fig. 4 is a sectional view a-a' of fig. 1.
Fig. 5 is a sectional view B-B' of fig. 1.
Fig. 6 is a cross-sectional view of C-C' of fig. 1.
Fig. 7 is a cross-sectional view of a Trench VDMOS provided in embodiment 2 of the present invention.
Fig. 8 is a cross-sectional view of a Trench VDMOS provided in embodiment 3 of the present invention.
FIGS. 9(a) -9(i) are process flow diagrams of the manufacturing method of example 1 of the present invention.
00 is a metal silicide, 1 is an th deep trench, 2 is a second deep trench, 3 is a third deep trench, 11 is a th conductive type substrate, 12 is a th conductive type drift region, 13 is a th conductive type source contact region, 14 is a th conductive type polysilicon region, 15 is a th conductive type contact region, 21 is a second conductive type well region, 22 is a second conductive type source contact region, 23 is a second conductive type polysilicon region, 31 is a gate dielectric layer, 32 is a metal front dielectric layer, 33 is a hard mask dielectric layer, 41 is a polysilicon filler, 51 is a source metal, 52 is a gate metal, 53 is a drain metal, and 54 is a stop ring metal.
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
Example 1
Trench VDMOS devices integrating ESD protection comprise a Trench VDMOS structure and an ESD protection structure;
the Trench VDMOS structure comprises a cell region and a terminal protection region, wherein the cell region comprises a plurality of cells which are identical in structure and are sequentially connected, the cell region comprises an th conduction type substrate 11, a th conduction type drift region 12 positioned on a th conduction type substrate 11, a second conduction type well region 21 positioned above the th conduction type drift region 12, a th conduction type source contact region 13 and a second conduction type source contact region 22 positioned above the second conduction type well region 21, a source metal 51 positioned above a metal front dielectric 32 and contacted with the second conduction type source contact region 22 and a th conduction type source contact region 13, the Trench VDMOS structure also comprises a deep groove 1 extending into the th conduction type drift region 12, a gate 31 and a polysilicon filler 41 positioned inside the th deep groove 1, and a metal front dielectric 32 positioned above the polysilicon filler 41;
the terminal protection region is of a trench structure and comprises stop rings and at least shunt rings, the terminal protection region comprises a gate dielectric layer 31 and a polysilicon filler 41 in a second deep groove 2 and a third deep groove 3, a metal front dielectric 32 positioned above the polysilicon filler 41 and above a second conductive type well region 21, and a stop ring metal 54 positioned above the metal front dielectric 32 and contacted with the polysilicon filler 41 in the third deep groove 3 and a conductive type contact region 15 in the second conductive type well region 21, wherein the upper surfaces of the polysilicon fillers 41 in the cell region and the terminal protection region are higher than the upper surface of the second conductive type well region 21, and the lower surface of the polysilicon filler 41 is lower than the upper surface of a conductive type drift region 12;
the ESD protection structure comprises a number of zener diode cells, which are connected across the gate metal 52 and the source metal 51.
Fig. 1 is a schematic top plan view of a Trench VDMOS device with integrated ESD protection, which shows that a strip-shaped cell array is disposed in a central region of the MOS device, a terminal protection ring is disposed on a periphery of a cell, and an ESD protection structure is disposed below a gate Pad.
Fig. 2 is a three-dimensional schematic diagram of a Trench VDMOS cell, fig. 3 is a cross-sectional view of a-a 'and b-b' of fig. 2, and as can be seen from fig. 2-3, an th deep Trench 1 is located in the second conductive well 21 and has a depth deeper than the th conductive drift region 12 under the second conductive well 21, a gate dielectric layer 31 is grown on the sidewall surface of the th deep Trench 1 by thermal oxidation, a polysilicon filling 41 is deposited in the Trench, the top of the Trench is covered by a metal front dielectric 32, a second conductive source contact region 22 is spaced from the th conductive source contact region 13 in the y direction, the y direction is parallel to the length direction of the th deep Trench, and the lower surface of the source metal 51 is lower than the upper surface of the th conductive source contact region 13.
Fig. 4 is a sectional view taken along line a-a' of fig. 1, which is a cross-sectional view of a Trench VDMOS device according to an embodiment of the invention, where the strap is formed by a Trench structure, the second deep Trench 2 is located in the second conductivity type well region 21 and has a depth deeper than the th conductivity type drift region 12 below the second conductivity type well region 21, the side wall surface of the second deep Trench 2 is thermally oxidized to grow a gate dielectric layer 31, a polysilicon filling 41 is deposited in the Trench, the top of the Trench is covered by a metal front dielectric 32, the polysilicon filling 41 in the second deep Trench 2 is in a floating state to form a terminal strap, the width of the Trench of the third deep Trench 3 is greater than the widths of the th deep Trench 1 and the second deep Trench 2, the third deep Trench 3 is located in the second conductivity type well region 21 and has a depth deeper than the th conductivity type drift region 12 below the second conductivity type well region 21, the side wall surface of the third deep Trench 3 is thermally oxidized to grow a gate dielectric layer 31, the polysilicon filling 41 in the Trench, the top of the deep Trench is provided with a stop ring metal 54, and the third Trench 3 is connected to form a polysilicon stop ring 21.
Fig. 5 is a cross-sectional view of B-B' of fig. 1, wherein the th deep trench 1 has an extension end of circular lead terminals with a diameter larger than the width of the th deep trench 1 or polygonal lead terminals with a side length larger than the width of the th deep trench 1, and a gate electrode lead hole is opened at the lead terminal position so that metal is connected to the polysilicon inside the th deep trench 1.
Fig. 6 is a cross-sectional view of C-C' of fig. 1, which is a schematic view of an ESD protection structure according to an embodiment of the present invention, the ESD protection structure is located above the hard mask dielectric layer 33, and includes th-conductivity-type polysilicon region 14, a second-conductivity-type polysilicon region 23, and a metal front dielectric 32 located on the polysilicon surface, the th-conductivity-type polysilicon region 14 is spaced apart from the second-conductivity-type polysilicon region 23, and the source metal 51 and the gate metal 52 are located above the metal front dielectric and contact the second-conductivity-type polysilicon region 23.
Preferably, the th conductive type is N-type and the second conductive type is P-type, or the th conductive type is P-type and the second conductive type is N-type.
The basic working principle of example 1 is as follows:
when the grid voltage is higher than the threshold voltage and is lower than the trigger voltage of the ESD protection structure, an inversion layer appears in the region of the second conductive type well region 21 close to the grid dielectric layer 31, and an electron path along the source metal 51, the conductive type source contact region 13, the inversion layer of the second conductive type well region 21, the conductive type drift region 12, the conductive type substrate 11 and the drain metal 53 is formed under the action of the drain voltage.
When the grid voltage is greater than the trigger voltage of the ESD protection structure, the current passes through the grid metal 52, the ESD protection structure and the source metal 51, the grid oxide layer is prevented from being broken down by high voltage, and the reliability of the Trench VDMOS is improved.
As shown in fig. 9(a) -9(i), this embodiment further provides methods for manufacturing the above-mentioned Trench VDMOS device with integrated ESD protection, including the following steps:
step 4, forming a deep groove by adopting photoetching and etching processes;
step 5, thermally growing to form a gate dielectric layer 31;
step 6, depositing polycrystalline silicon, and etching the polycrystalline silicon to form a gate electrode;
step 8, etching the hard mask by a dry method to form an active area;
step 9, forming a conductive type source contact region 13 and a conductive type polysilicon region 14 by conductive type ion implantation;
step 10, depositing a dielectric layer, and forming a metal contact groove by adopting a photoetching process;
and step 13, thinning the substrate, and metalizing the back to form drain metal 53.
Example 2
Example 3
Example 4
The embodiment provides methods for manufacturing a Trench VDMOS device with integrated ESD protection, including the following steps:
step 4, thermally growing to form a gate dielectric layer 31;
step 5, depositing polycrystalline silicon, and etching the polycrystalline silicon to form a gate electrode;
step 6, forming a second conductive type well region 21 by injecting second conductive type ions;
step 8, etching the hard mask by a dry method to form an active area;
step 9, forming a conductive type source contact region 13 and a conductive type polysilicon region 14 by conductive type ion implantation;
step 10, depositing a dielectric layer, and forming a metal contact groove by adopting a photoetching process;
and step 13, thinning the substrate, and metalizing the back to form drain metal 53.
It will be appreciated that those skilled in the art, upon attaining an understanding of the foregoing may readily produce alterations to, variations of, and equivalents to , without departing from the spirit and scope of the present disclosure, which are to be accorded the scope of the appended claims.
Claims (14)
- The integrated ESD protection Trench VDMOS device is characterized by comprising a Trench VDMOS structure and an ESD protection structure;the Trench VDMOS structure comprises a cell region and a terminal protection region, the cell region comprises a plurality of cells which are identical in structure and are connected in sequence, the cell region comprises an th conduction type substrate (11), a th conduction type drift region (12) positioned on the th conduction type substrate (11), a second conduction type well region (21) positioned above the th conduction type drift region (12), a th conduction type source contact region (13) and a second conduction type source contact region (22) positioned above the second conduction type well region (21), source metal (51) positioned above a metal front dielectric (32) and contacted with the second conduction type source contact region (22) and a th conduction type source contact region (13), the Trench VDMOS structure further comprises a deep groove (1) extending into the th conduction type drift region (12), a gate dielectric layer (31) and a polysilicon filler (41) positioned inside the th deep groove (1), and the polysilicon filler (32) positioned above the polysilicon filler (41);the terminal protection region is of a trench structure and comprises cut-off rings and at least voltage-dividing rings, the terminal protection region comprises a gate dielectric layer (31) and a polysilicon filler (41) in a second deep groove (2) and a third deep groove (3), a metal front dielectric (32) positioned above the polysilicon filler (41) and above a second conductive type well region (21), and a cut-off ring metal (54) positioned above the metal front dielectric (32) and contacted with the polysilicon filler (41) in the third deep groove (3) and a conductive type contact region (15) in the second conductive type well region (21), wherein the upper surfaces of the polysilicon fillers (41) of the cellular region and the terminal protection region are higher than the upper surface of the second conductive type well region (21), and the lower surface of the polysilicon filler (41) is lower than the upper surface of a conductive type drift region (12);the ESD protection structure comprises a plurality of Zener diode units, and is connected to two ends of the grid metal (52) and the source metal (51).
- 2. The Trench VDMOS device with integrated ESD protection of claim 1, wherein the second conductivity type source contact region (22) is spaced apart from the conductivity type source contact region (13) in the y-direction, which is parallel to the length direction of the deep Trench.
- 3. The kind of integrated ESD protected Trench VDMOS device of claim 1, wherein the polysilicon filling (41) inside the second deep Trench (2) is in floating state.
- 4. The integrated ESD protected Trench VDMOS device of claim 1, wherein the lower surface of the source metal (51) is lower than the upper surface of the th conductive type source contact region (13).
- 5. The integrated ESD protected Trench VDMOS device according to claim 1, wherein the doping concentration of the th conductivity type source contact region (13) is higher than the doping concentration of the second conductivity type source contact region (22).
- 6. The integrated ESD protected Trench VDMOS device according to claim 1, wherein the third deep Trench (3) has a width larger than deep trenches (1) and (2).
- 7. The integrated ESD protected Trench VDMOS device according to claim 1, wherein the extension end of the deep Trench (1) is circular lead terminals with diameter larger than the width of the deep Trench (1) or polygonal lead terminals with side length larger than the width of the deep Trench (1), and gate electrode lead holes are opened at the lead terminal positions to connect the metal with the polysilicon inside the deep Trench (1).
- 8. The Trench VDMOS device with integrated ESD protection of claim 1, wherein the ESD protection structure is located above the hard mask dielectric layer (33) and comprises a conductivity type polysilicon region (14), a second conductivity type polysilicon region (23), and a metal front dielectric (32) located on the surface of the polysilicon, the conductivity type polysilicon region (14) and the second conductivity type polysilicon region (23) are arranged at intervals.
- 9. The integrated ESD protected Trench VDMOS device of claim 8, wherein the source metal (51) and the gate metal (52) are over the pre-metal dielectric and in contact with the second conductivity type polysilicon region (23).
- 10. The integrated ESD protected Trench VDMOS device of claim 1, wherein a th conductivity type source contact region (13) is disposed over the second conductivity type source contact region (22).
- 11. The integrated ESD protected Trench VDMOS device of claim 10, wherein a metal silicide (00) is disposed over the conductivity type source contact region (13).
- 12. The integrated ESD protected Trench VDMOS device of any of claims 1-11 and , wherein the th conductivity type is N-type and the second conductivity type is P-type, or the th conductivity type is P-type and the second conductivity type is N-type.
- 13. The method of manufacturing integrated ESD protected Trench VDMOS devices of any of claims 1-9 and , comprising the steps of:step 1, an th conductive type substrate (11) is adopted to epitaxially form a th conductive type drift region (12);step 2, forming a second conductive type well region (21) by injecting second conductive type ions;step 3, thermal growing or depositing SiO2Forming a hard mask dielectric layer (33);step 4, forming a deep groove by adopting photoetching and etching processes;step 5, thermally growing to form a gate dielectric layer (31);step 6, depositing polycrystalline silicon, and etching the polycrystalline silicon to form a gate electrode;step 7, depositing ESD polycrystalline silicon, injecting second conductive type ions to form a second conductive type polycrystalline silicon area (23), and etching the polycrystalline silicon to form ESD protection polycrystalline silicon;step 8, etching the hard mask by a dry method to form an active area;step 9, forming a conductive type source contact region (13), a conductive type polysilicon region (14) by conductive type ion implantation;step 10, depositing a dielectric layer, and forming a metal contact groove by adopting a photoetching process;step 11, forming a second conductive type source contact region (22) by second conductive type ion implantation;step 12, depositing metal, and forming source metal (51), gate metal (52) and stop ring metal (54) through a photoetching process;and step 13, thinning the substrate, and metalizing the back to form drain metal (53).
- 14. The method of manufacturing integrated ESD protected Trench VDMOS devices of any of claims 1-9 and , comprising the steps of:step 1, using an th conductive type substrate (11) to epitaxially form a th conductive type drift region (12);step 2, thermal growth or deposition of SiO2Forming a hard mask dielectric layer (33);step 3, forming a deep groove by adopting photoetching and etching processes;step 4, thermally growing to form a gate dielectric layer (31);step 5, depositing polycrystalline silicon, and etching the polycrystalline silicon to form a gate electrode;step 6, forming a second conductive type well region (21) by injecting second conductive type ions;step 7, depositing ESD polycrystalline silicon, injecting second conductive type ions to form a second conductive type polycrystalline silicon area (23), and etching the polycrystalline silicon to form ESD protection polycrystalline silicon;step 8, etching the hard mask by a dry method to form an active area;step 9, forming a conductive type source contact region (13), a conductive type polysilicon region (14) by conductive type ion implantation;step 10, depositing a dielectric layer, and forming a metal contact groove by adopting a photoetching process;step 11, forming a second conductive type source contact region (22) by second conductive type ion implantation;step 12, depositing metal, and forming source metal (51), gate metal (52) and stop ring metal (54) through a photoetching process;and step 13, thinning the substrate, and metalizing the back to form drain metal (53).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911043136.XA CN110739303B (en) | 2019-10-30 | 2019-10-30 | Trench VDMOS device integrated with ESD protection and manufacturing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911043136.XA CN110739303B (en) | 2019-10-30 | 2019-10-30 | Trench VDMOS device integrated with ESD protection and manufacturing method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN110739303A true CN110739303A (en) | 2020-01-31 |
| CN110739303B CN110739303B (en) | 2020-11-06 |
Family
ID=69270381
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201911043136.XA Active CN110739303B (en) | 2019-10-30 | 2019-10-30 | Trench VDMOS device integrated with ESD protection and manufacturing method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN110739303B (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111490094A (en) * | 2020-04-20 | 2020-08-04 | 中国电子科技集团公司第五十八研究所 | Manufacturing method of trench split gate DMOS device with ESD protection structure |
| CN111508950A (en) * | 2020-04-09 | 2020-08-07 | 中国电子科技集团公司第五十五研究所 | Silicon carbide MOSFET device with integrated electrostatic protection capability and manufacturing method thereof |
| CN112234056A (en) * | 2020-09-03 | 2021-01-15 | 深圳市汇德科技有限公司 | Semiconductor device with a plurality of transistors |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1655331A (en) * | 1999-04-22 | 2005-08-17 | 先进模拟科技公司 | A super-self-aligned trench-gate DMOS |
| CN101147265A (en) * | 2005-06-08 | 2008-03-19 | 夏普株式会社 | Trench MOSFET and method for manufacturing same |
| CN102214689A (en) * | 2010-04-06 | 2011-10-12 | 上海华虹Nec电子有限公司 | Terminal protection structure of super junction device and manufacturing method of terminal protection structure |
| CN104681480A (en) * | 2007-12-31 | 2015-06-03 | 万国半导体股份有限公司 | Reduced mask configuration for semiconductor power device with electrostatic discharge (ESD) circuit protection |
| CN106024634A (en) * | 2016-07-06 | 2016-10-12 | 深圳深爱半导体股份有限公司 | Power transistor with electrostatic discharge protection diode structures, and manufacturing method thereof |
-
2019
- 2019-10-30 CN CN201911043136.XA patent/CN110739303B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1655331A (en) * | 1999-04-22 | 2005-08-17 | 先进模拟科技公司 | A super-self-aligned trench-gate DMOS |
| CN101147265A (en) * | 2005-06-08 | 2008-03-19 | 夏普株式会社 | Trench MOSFET and method for manufacturing same |
| CN104681480A (en) * | 2007-12-31 | 2015-06-03 | 万国半导体股份有限公司 | Reduced mask configuration for semiconductor power device with electrostatic discharge (ESD) circuit protection |
| CN102214689A (en) * | 2010-04-06 | 2011-10-12 | 上海华虹Nec电子有限公司 | Terminal protection structure of super junction device and manufacturing method of terminal protection structure |
| CN106024634A (en) * | 2016-07-06 | 2016-10-12 | 深圳深爱半导体股份有限公司 | Power transistor with electrostatic discharge protection diode structures, and manufacturing method thereof |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111508950A (en) * | 2020-04-09 | 2020-08-07 | 中国电子科技集团公司第五十五研究所 | Silicon carbide MOSFET device with integrated electrostatic protection capability and manufacturing method thereof |
| CN111490094A (en) * | 2020-04-20 | 2020-08-04 | 中国电子科技集团公司第五十八研究所 | Manufacturing method of trench split gate DMOS device with ESD protection structure |
| CN111490094B (en) * | 2020-04-20 | 2022-08-02 | 中国电子科技集团公司第五十八研究所 | Manufacturing method of trench split gate DMOS device with ESD protection structure |
| CN112234056A (en) * | 2020-09-03 | 2021-01-15 | 深圳市汇德科技有限公司 | Semiconductor device with a plurality of transistors |
| CN112234056B (en) * | 2020-09-03 | 2024-04-09 | 深圳市汇德科技有限公司 | Semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| CN110739303B (en) | 2020-11-06 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US10038062B2 (en) | Circuit configuration and manufacturing processes for vertical transient voltage suppressor (TVS) and EMI filter | |
| US8896093B2 (en) | Circuit configuration and manufacturing processes for vertical transient voltage suppressor (TVS) and EMI filter | |
| US6624030B2 (en) | Method of fabricating power rectifier device having a laterally graded P-N junction for a channel region | |
| US11049931B2 (en) | Semiconductor device | |
| US20080121988A1 (en) | Circuit configuration and manufacturing processes for vertical transient voltage suppressor (TVS) and EMI filter | |
| CN110739303B (en) | Trench VDMOS device integrated with ESD protection and manufacturing method | |
| CN103456788A (en) | Vertical power mosfet and methods for forming the same | |
| CN107799514B (en) | Electrostatic discharge protection structure and forming method thereof | |
| CN103050541A (en) | Radio frequency LDMOS (laterally diffused metal oxide semiconductor) device and manufacture method thereof | |
| US20100140713A1 (en) | Transistor-type protection device and semiconductor integrated circuit | |
| US10050154B2 (en) | Trench vertical JFET with ladder termination | |
| CN109037204B (en) | Power device and manufacturing method thereof | |
| CN114497201A (en) | Field effect transistor of integrated body relay diode, preparation method thereof and power device | |
| CN116314302A (en) | Manufacturing method of groove type silicon carbide MOSFET device | |
| CN111192871B (en) | Transistor structure for electrostatic protection and manufacturing method thereof | |
| CN111199970B (en) | Transistor structure for electrostatic protection and manufacturing method thereof | |
| CN110911495B (en) | Groove VDMOS device integrated with ESD protection and manufacturing method | |
| CN109346508B (en) | Semiconductor structure with current path direction control function | |
| CN113937098A (en) | Electrostatic protection chip for rapid charging management system and preparation method thereof | |
| CN219419037U (en) | Groove type silicon carbide MOSFET device | |
| CN112018162B (en) | 4H-SiC side gate integrated SBD MOSFET device and preparation method thereof | |
| CN114023737B (en) | Electrostatic protection chip based on power management and preparation method thereof | |
| CN219591392U (en) | Semiconductor structure and semiconductor power device | |
| CN211017088U (en) | ESD integrated VDMOS device | |
| CN105489602A (en) | Electrostatic discharge protection device with low trigger voltage |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |