CN111508950B - Silicon carbide MOSFET device with integrated electrostatic protection capability and manufacturing method thereof - Google Patents
Silicon carbide MOSFET device with integrated electrostatic protection capability and manufacturing method thereof Download PDFInfo
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- CN111508950B CN111508950B CN202010275034.7A CN202010275034A CN111508950B CN 111508950 B CN111508950 B CN 111508950B CN 202010275034 A CN202010275034 A CN 202010275034A CN 111508950 B CN111508950 B CN 111508950B
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- 229910010271 silicon carbide Inorganic materials 0.000 title claims abstract description 39
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 title claims abstract description 38
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 9
- 239000002184 metal Substances 0.000 claims abstract description 15
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 14
- 229920005591 polysilicon Polymers 0.000 claims abstract description 14
- 238000000034 method Methods 0.000 claims abstract description 8
- 239000010410 layer Substances 0.000 claims description 77
- 239000004065 semiconductor Substances 0.000 claims description 17
- 239000000758 substrate Substances 0.000 claims description 17
- 210000000746 body region Anatomy 0.000 claims description 16
- 239000011229 interlayer Substances 0.000 claims description 16
- 238000004518 low pressure chemical vapour deposition Methods 0.000 claims description 6
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims description 4
- 238000000231 atomic layer deposition Methods 0.000 claims description 3
- 238000011065 in-situ storage Methods 0.000 claims description 3
- 230000003647 oxidation Effects 0.000 claims description 3
- 238000007254 oxidation reaction Methods 0.000 claims description 3
- 238000005468 ion implantation Methods 0.000 description 5
- 238000010586 diagram Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000002427 irreversible effect Effects 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 229920006395 saturated elastomer Polymers 0.000 description 1
- 230000035939 shock Effects 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0255—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using diodes as protective elements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
- H01L29/0688—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions characterised by the particular shape of a junction between semiconductor regions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
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- Microelectronics & Electronic Packaging (AREA)
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Abstract
The invention provides a silicon carbide MOSFET device integrated with an electrostatic protection diode and a manufacturing method thereof. The device comprises a source metal on the front side, a gate metal and a drain metal on the back side, wherein ohmic contact is arranged below the source metal and is electrically connected with the deepest second conductive type region below the gate electrode block. There is floating first conductive type area with medium depth under the grid electrode block, there is the shallowest second conductive type area in the floating first conductive type area, the grid electrode has ohmic contact with the shallowest second conductive type area, and connects with the polysilicon grid at the same time, so there is a PNP (or NPN) junction between the grid source, namely the silicon carbide Zener diode whose tail end (or head end) is butt jointed. The invention has simple structure, occupies no extra space, has simple realization method and can improve the anti-static impact capability of the silicon carbide MOSFET device grid.
Description
Technical Field
The invention relates to the field of design and manufacture of silicon carbide power semiconductor devices, in particular to a structure and a manufacture method of a silicon carbide MOSFET device integrated with an electrostatic protection diode.
Background
Silicon carbide is one of the third-generation semiconductor materials, and has many advantages compared with silicon, such as wide forbidden band, high breakdown field strength, high thermal conductivity, high saturated electron mobility, stable chemical properties and the like, so that the silicon carbide power device has great application advantages in the field of high-temperature, high-frequency and high-power electronics. Compared with silicon, the full silicon carbide power module has the advantages of smaller electric energy loss, smaller volume and more suitability for application at high temperature, so that the full silicon carbide power module has great advantages in the aspects of high-end switching power supplies, new energy automobiles, rail transit and the like.
Silicon carbide MOSFETs are an important component of all-silicon carbide power modules, and their performance and reliability are of critical importance. Electrostatic failure is one of the common failure modes of semiconductor devices, and generally, when the devices are subjected to electrostatic shock, the weakest gate oxide layer can be broken down to cause irreversible damage.
The existing MOSFET device with the electrostatic protection diode is mainly realized by adding a polysilicon Zener diode between a grid source, thick field oxygen needs to grow below the polysilicon Zener diode, the difficulty and the complexity of the process are increased, and in addition, the scheme also needs additional space for placing the Zener diode.
Disclosure of Invention
The invention provides a structure and a manufacturing method of a silicon carbide MOSFET device integrated with an electrostatic protection diode, which are used for reducing the damage of overshoot voltage and electrostatic discharge to a gate dielectric layer of the device, and through connecting a silicon carbide Zener diode in parallel between a gate source and a gate source, the silicon carbide MOSFET device does not occupy redundant space and does not increase the complexity of the process.
The technical scheme is as follows:
to achieve the above and other related objects, the present invention provides a silicon carbide MOSFET device with an integrated esd protection diode, comprising:
the epitaxial layer is positioned on the semiconductor substrate;
the semiconductor device comprises well regions of a second conductivity type and body regions of the second conductivity type, wherein the well regions are adjacently arranged, and the body regions are respectively positioned on the well regions;
a JFET area of the first conductivity type is arranged between the adjacent well areas of the second conductivity type;
the source region of the first conduction type is positioned at the upper part of the well region in the active region, on two sides of the body region, the boundary of the source region is positioned in the well region, and a certain length is arranged between the source region and the boundary of the well region;
the gate electrode is positioned on the epitaxial layer, and a gate dielectric layer is filled between the gate electrode and the epitaxial layer;
The electrostatic protection diode is positioned at the upper part of the epitaxial layer and comprises a deepest second conductive type area, a slightly shallow floating first conductive type area and a shallowest second conductive type area, and the deepest second conductive type area is electrically connected with the well area in the active area;
the interlayer dielectric layer is positioned on the gate electrode and the exposed epitaxial layer;
the grid electrode is electrically connected with the grid electrode and one end of the electrostatic protection diode through a contact hole of the interlayer dielectric layer;
the source terminal is electrically connected with the source region of the first conduction type, the body region of the second conduction type and the other end of the electrostatic protection diode through the contact hole of the interlayer dielectric layer;
and the drain terminal metal is positioned below the semiconductor substrate.
Further, the semiconductor substrate is a silicon carbide substrate.
Further, the epitaxial layer is a silicon carbide epitaxial layer.
Further, the material of the gate electrode is heavily doped polysilicon of the second conductivity type.
Further, the electrostatic protection diode is a silicon carbide zener diode.
Further, the esd diode is a PNP diode or an NPN diode, that is, two PN junctions with butt-jointed tails (or heads and tails), wherein one of the second conductive type regions is electrically connected to the source metal, the other second conductive type region is electrically connected to the gate metal, and the first conductive type region is electrically floating.
Furthermore, in the structure of the PNP diode or the NPN diode, the two second conductivity type regions are deeper and shallower, and the first conductivity type region is located in the middle.
Further, the invention provides a preparation method of the silicon carbide MOSFET device integrated with the electrostatic protection diode, which comprises the following steps:
s1, forming an epitaxial layer of a first conduction type on a semiconductor substrate of the first conduction type;
s2, forming a well region of a second conductivity type, a body region of the second conductivity type, a source region of a first conductivity type and a JFET region on the upper portion of the epitaxial layer;
s3, forming a deepest second conductive type region, a floating first conductive type region and a shallowest second conductive type region of the electrostatic protection diode on the upper portion of the epitaxial layer;
s4, forming a terminal field limiting ring doped region on the upper part of the epitaxial layer;
s5, forming a gate dielectric layer and a gate electrode on the epitaxial layer;
s6, forming an interlayer dielectric layer on the gate electrode and the exposed epitaxial layer;
s7, forming a contact hole in the interlayer medium;
and S8, forming metal layers of a grid electrode terminal, a source electrode terminal and a drain electrode terminal.
Further, in step S3, the deepest second conductive region of the esd protection diode may be formed in synchronization with the well region, and the floating first conductive region and the shallowest second conductive region may be formed separately.
Further, in step S5, the gate dielectric layer is formed by one or more of thermal oxidation, LPCVD, PECVD, or ALD, and the polysilicon electrode is formed by in-situ doping, or undoped polysilicon is formed by doping.
Has the advantages that:
the silicon carbide MOSFET device integrated with the electrostatic protection diode and the manufacturing method thereof have the advantages of simple structure, no occupation of redundant chip space and simple realization method, and improve the antistatic impact capacity between the grid sources by introducing the Zener diode between the grid sources.
Drawings
Fig. 1 is a schematic diagram of a silicon carbide MOSFET device integrated with an esd protection diode according to an embodiment of the present invention, in which an epitaxial layer is formed on a substrate and a well region, a body region, a source region, a JFET region, and other structures are obtained by ion implantation;
FIG. 2 is a schematic diagram of an ESD protection diode formed by ion implantation under a gate electrode block according to an embodiment of the present invention;
fig. 3 is a schematic diagram of forming a gate dielectric layer, a polysilicon electrode, an interlayer dielectric layer, and a metal layer over an epitaxial layer in an embodiment of the invention.
Fig. 4 is a plan view of the device around the gate electrode block, with the active region unit cell cross-sectional view taken at position BB 'and the gate electrode block cross-sectional view taken at position AA'.
In fig. 1-3, 100 is a semiconductor substrate, 200 is an epitaxial layer, 210 is a well region, 220 is a body region, 230 is a source region, 240 is a deepest second conductivity type region, 250 is a floating first conductivity type region, 260 is a shallowest second conductivity type region, 300 is a gate dielectric layer, 400 is a gate electrode, 500 is an interlayer dielectric layer, 600 is a gate terminal, 700 is a source terminal, and 800 is a drain terminal metal.
The specific implementation mode is as follows:
the silicon carbide MOSFET device integrated with the esd protection diode according to the present invention will be further described with reference to the accompanying drawings.
In an embodiment of the present invention, there is provided a silicon carbide MOSFET device integrated with an esd diode, the active region unit cell structure of which is shown in fig. 1, including an epitaxial layer 200 of a first conductivity type disposed on a semiconductor substrate 100 of the first conductivity type, a well region 210 of a second conductivity type disposed adjacent to the epitaxial layer 200, and a body region 230 of the second conductivity type disposed above the well region 210; on the upper portion of the well region 210 and on both sides of the body region 230, a source region 220 of the first conductivity type is disposed, and a boundary of the source region 220 is inside a boundary of the well region 210 and has a certain length from the boundary of the well region 210. A JFET region (211) of the first conductivity type is provided on the upper portion of the epitaxial layer 200 between adjacent well regions 210.
As shown in fig. 2 and fig. 3, a gate dielectric layer 300 and a gate electrode 400 are further formed on the epitaxial layer 200, and the gate dielectric layer 300 is filled between the gate electrode 400 and the epitaxial layer 200; a deepest second conductive type region 240, a slightly shallow floating first conductive type region 250 and a shallowest second conductive type region 260 of the electrostatic protection diode are arranged below the gate electrode block; an interlevel dielectric layer 500 is provided over the gate electrode 400 and the exposed epitaxial layer 200. A contact hole is formed in the interlayer dielectric layer 500, a gate terminal 600 and a source terminal 700 are disposed on the upper portion of the interlayer dielectric layer 500, the gate terminal 600 is electrically connected to the gate electrode 400 and one end of the esd protection diode through the contact hole, and the source terminal 700 is electrically connected to the first conductive type source region 230, the second conductive type body region 220 and the other end of the esd protection diode through the contact hole.
As shown in fig. 4, the cross-sectional view at the BB 'position is a unit cell view of the active area (fig. 1), the cross-sectional view at the AA' position is a cross-sectional view of the gate electrode block (fig. 2), and the deepest second conductivity type region 240 under the gate electrode block and the well region 210 of the active area are both the second conductivity type regions and are in electrical communication.
In another embodiment of the present invention, the semiconductor substrate 100 is a silicon carbide substrate, the epitaxial layer 200 is a silicon carbide epitaxial layer, the gate electrode 400 is made of heavily doped polysilicon of the second conductivity type, and the esd protection diode is a silicon carbide zener diode.
Further, in an embodiment of the present invention, the esd diode is a PNP diode or NPN diode, and the diodes are two PN junctions butted end to end (or head to head), wherein one second conductive region is electrically connected to the source metal, the other second conductive region is electrically connected to the gate metal, the first conductive region is electrically floating, the two second conductive regions have a deeper depth, and the first conductive region has a middle depth.
In one embodiment of the present invention, a method for manufacturing the above silicon carbide MOSFET integrated with an esd protection diode is provided, which comprises the following steps:
s1, forming an epitaxial layer 200 of a first conductivity type on a semiconductor substrate 100 of the first conductivity type by vapor deposition, as shown in fig. 1;
s2, forming a well region 210 of a second conductivity type and a body region 220 of the second conductivity type, as well as a source region 230 and a JFET region of a first conductivity type on the upper portion of the epitaxial layer 200 by ion implantation, as shown in FIG. 1;
s3, forming the deepest second conductive type region 240, the slightly shallow floating first conductive type region 250 and the shallowest second conductive type region 260 of the electrostatic protection diode on the upper part of the epitaxial layer through ion implantation, as shown in FIG. 2;
S4, forming a terminal doped region of a field limiting ring structure on the upper part of the epitaxial layer through ion implantation;
s5, forming a gate dielectric layer 300 on the epitaxial layer, and forming a gate electrode 400 through LPCVD (low pressure chemical vapor deposition), as shown in FIG. 3;
s6, forming an interlayer dielectric layer 500 on the gate electrode 400 and the exposed epitaxial layer 200 through LPCVD or PECVD, as shown in FIG. 3;
s7, forming a contact hole in the interlayer medium through photoetching and etching;
s8. forming a gate terminal 600, a source terminal 700, a drain terminal metal 800 by PVD, as shown in fig. 3.
Further, in step S3, the deepest second conductive type region 240 of the esd protection diode may be formed in synchronization with the well region 210, and the floating first conductive type region 250 and the shallowest second conductive type region 260 may be separately formed.
Further, in step S5, the gate dielectric layer 300 may be formed by one (or two) of thermal oxidation, LPCVD, PECVD, ALD, etc., and the polysilicon electrode is formed by in-situ doping, or undoped polysilicon is formed by doping.
Claims (9)
1. A silicon carbide MOSFET device incorporating an esd protection diode, comprising:
-a semiconductor substrate (100) of a first conductivity type and an epitaxial layer (200) of the first conductivity type, the epitaxial layer (200) being located on the semiconductor substrate (100);
The epitaxial layer structure comprises well regions (210) of the second conductivity type and body regions (220) of the second conductivity type, wherein the well regions (210) are adjacently arranged, and the body regions (220) are respectively positioned on the well regions (210), and the well regions (210) are positioned on the upper portion of the epitaxial layer (200) in the active region;
a JFET area (211) of the first conduction type is arranged between the adjacent well areas (210) of the second conduction type;
the source region (230) of the first conduction type is positioned at the upper part of the well region (210) in the active region, and on two sides of the body region (220), the boundary of the source region is positioned in the well region (210), and a certain length is arranged away from the boundary of the well region (210);
the gate electrode (400) is positioned on the epitaxial layer (200), and a gate dielectric layer (300) is filled between the gate electrode (400) and the epitaxial layer (200);
the electrostatic protection diode is positioned on the upper part of the epitaxial layer (200) and comprises a deepest second conduction type area (240), a slightly shallow floating first conduction type area (250) and a shallowest second conduction type area (260), wherein the deepest second conduction type area (240) is electrically connected with the well area (210) in the active area;
an interlayer dielectric layer (500) positioned on the gate electrode (400) and the exposed epitaxial layer (200);
A gate terminal (600) electrically connected to the gate electrode (400) and one end of the ESD diode through a contact hole of an interlayer dielectric layer (500);
a source terminal (700) electrically connected to the first conductive type source region (230), the second conductive type body region (220), and the other end of the ESD diode through a contact hole of the interlayer dielectric layer (500);
a drain terminal metal (800) located below the semiconductor substrate (100).
2. The diode-integrated silicon carbide MOSFET device of claim 1, wherein the semiconductor substrate (100) is a silicon carbide substrate.
3. The diode integrated silicon carbide MOSFET device of claim 1, wherein the epitaxial layer (200) is a silicon carbide epitaxial layer.
4. The silicon carbide MOSFET device of claim 1, wherein the gate electrode (400) is a heavily doped polysilicon of the second conductivity type.
5. The silicon carbide MOSFET device integrated with an esd protection diode as recited in claim 1, wherein the esd protection diode is a silicon carbide zener diode.
6. The integrated esd protection diode silicon carbide MOSFET device of claim 1, wherein the esd protection diode is a PNP diode or an NPN diode.
7. The method of fabricating a silicon carbide MOSFET device incorporating an esd protection diode as recited in claim 1, comprising the steps of:
s1, forming an epitaxial layer of a first conduction type on a semiconductor substrate of the first conduction type;
s2, forming a well region and a body region of a second conductivity type, a source region and a JFET region of a first conductivity type on the upper portion of the epitaxial layer;
s3, forming a deepest second conductive type region, a floating first conductive type region and a shallowest second conductive type region of the electrostatic protection diode on the upper portion of the epitaxial layer;
s4, forming a terminal doping area of a field limiting ring structure on the upper part of the epitaxial layer;
s5, forming a gate dielectric layer and a gate electrode on the epitaxial layer;
s6, forming an interlayer dielectric layer on the gate electrode and the exposed epitaxial layer;
s7, forming a contact hole in the interlayer medium;
and S8, forming metal layers of a grid electrode terminal, a source electrode terminal and a drain electrode terminal.
8. The method of claim 7, wherein in step S3, the deepest second conductivity type region and the well region of the esd diode are formed simultaneously, and the shallower floating first conductivity type region and the shallowest second conductivity type region are formed separately.
9. The method of claim 7, wherein in step S5, the gate dielectric layer is formed by one or more of thermal oxidation, LPCVD, PECVD and ALD, and the gate electrode is a polysilicon electrode formed by in-situ doping or a polysilicon electrode formed by doping undoped polysilicon.
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