JP2002026314A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device of improved breakdown strength. SOLUTION: Inside a device, a drain region 15 and source region 16 are enclosed with a p-well layer 14. A high-concentration n-type deep diffusion layer 19 is formed from the surface of a substrate 11 at a drain as deep as an embedded layer 12. The distance X between a drain contact region 20 and a source region 16 is larger than the film thickness Y of an epitaxial layer 13 on the embedded layer 12, with the length not preventing micronizing of an element.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high breakdown voltage semiconductor device, and more particularly to a power MOSFET having a horizontal structure.

[0002]

2. Description of the Related Art A power MOSFET for high withstand voltage employs a horizontal structure having a short current path in order to reduce the on-resistance, and further optimizes the device length by shortening the device length.

FIG. 6 shows a conventional horizontal power MO for high withstand voltage.
FIG. 2 shows a cross-sectional view of an SFET.

[0006] As shown in FIG. 6, a p-type semiconductor substrate 11 is formed.
1, an n-type buried layer 112 is formed, and an n-type epitaxial layer 113 is formed on the buried layer 112 by epitaxial growth. A p-type well layer 114 is selectively formed on the surface of the epitaxial layer 113, and a low-concentration n ⁻ -type drain region 115 is selectively formed on the surface of the well layer 114. A high concentration n ⁺ -type source region 116 is selectively formed on the surface of well layer 114 so as to be separated from drain region 115. On the semiconductor substrate 111 between the drain region 115 and the source region 116, that is, on the channel 117, a gate electrode 118 is formed insulated from the semiconductor substrate 111.

In the drain region 115, an n ⁺ -type drain contact region 120 having a higher concentration than the drain region 115 is formed. The semiconductor substrate 11 between the drain contact region 120 and the channel 117
1, a field insulating film 121 is formed. Further, on the surface of the well layer 114, the source region 116 is formed.
Is formed adjacent to the source contact region 122.

Further, an n-type isolation / diffusion layer 123 is formed surrounding the well layer 114 so as to be separated from the well layer 114.
This separation / diffusion layer 123 is provided so as to reach the end of the buried layer 112. On the surface of the isolation diffusion layer 123, an n ⁺ -type drain contact region 124 having a higher concentration than the isolation diffusion layer 123 is formed.

The interlayer insulating film 12 is formed on the semiconductor substrate 111 on which the field insulating film 121 and each semiconductor region are formed.
5 are formed. The interlayer insulating film 125 has a contact hole 126 exposing the surfaces of the drain contact regions 120 and 124, and a contact hole 127 exposing the surfaces of the source region 116 and the source contact region 122.

The contact hole 1 is formed on the interlayer insulating film 125.
First and second drain electrodes 128 and 129 are formed in contact with the drain contact regions 120 and 124 through the gate electrode 26, and a source electrode 130 is formed in the source region 116 and the source contact region 122 through the contact hole 127. . The first drain electrode 128 is electrically connected to the drain region 115 via the drain contact region 120, and the source electrode 130 is also electrically connected to the well layer 114 via the source contact region 122. Further, one second drain electrode 129 is connected to the other second drain electrode 12 via the drain contact region 124, the isolation diffusion layer 123, and the buried layer 112.
9 is electrically connected.

Further, a p-type well layer 131 is formed apart from the isolation diffusion layer 123, and a p-type buried layer 132 connecting the well layer 131 and the semiconductor substrate 111 is formed. A p ⁺ -type ground contact region 133 having a higher concentration than the well layer 131 is formed on the well layer 131, and a ground electrode 135 in contact with the ground contact region 133 via the contact hole 134 in the interlayer insulating film 125 is formed. Is formed.

[0010]

However, the conventional high breakdown voltage semiconductor device, particularly a power MOSFET having a horizontal structure as a high-side switch, has an n ⁺ diffusion layer of a drain portion as compared with a high breakdown voltage device having a vertical structure. Since the (drain contact region 120) is shallow, the PN junction is shallow and the capacitance between the source and the drain is small.
Therefore, when a surge is applied via the drain electrode 128, the surge charge cannot be sufficiently charged, so that the surge current cannot be reduced. Further, since the current path is formed at the interface of the substrate 111, the electric field tends to concentrate on the curved surface 120 'of the drain contact region 120. Therefore, the breakdown strength due to static electricity (ESD breakdown strength) is lower than that of a high-voltage device having a vertical structure.

Therefore, conventionally, by providing a protection circuit such as an active clamp protection circuit in a high breakdown voltage device,
The aim was to improve the ESD resistance. However, it is very difficult to improve the ESD withstand capability due to the fact that there is a circuit configuration in which a protection circuit cannot be mounted, and even in the case where a protection circuit is provided, the chip area increases due to the large element area. there were.

The present invention has been made to solve the above problems, and an object of the present invention is to provide a semiconductor device capable of improving the breakdown strength.

[0013]

The present invention uses the following means to achieve the above object.

According to a first semiconductor device of the present invention, there is provided a semiconductor substrate of a first conductivity type, a buried layer of a second conductivity type formed on the semiconductor substrate, and a second buried layer formed on the buried layer.
A conductive type epitaxial layer; a first conductive type well layer formed on the surface of the epitaxial layer; a second conductive type source region selectively formed on the surface of the well layer; A second conductive type drain region selectively formed on the surface separately from the source region; and a second conductive type higher concentration than the drain region selectively formed on the surface of the drain region. A drain contact region, a gate electrode formed insulated from the semiconductor substrate on the semiconductor substrate between the drain region and the source region, and a gate electrode formed on the drain contact region; A first drain electrode electrically connected to the drain region through the source electrode, and a source electrode formed on the source region and electrically connected to the source region. A second conductivity type separation / diffusion layer formed around the well layer so as to be separated from the well layer and in contact with the buried layer; and formed on the separation / diffusion layer and electrically connected to the first drain electrode. A second drain electrode to be connected, wherein a distance X between the drain contact region and the source region is longer than a film thickness Y of the epitaxial layer on the buried layer.

According to the first semiconductor device, when a surge is applied through the drain electrode, the surge current is mainly shifted in the direction of the film thickness Y (vertical direction) rather than in the direction of the distance X (horizontal direction). You can escape. As a result, the electric field is more concentrated in the vertical direction than in the horizontal direction, and breakdown occurs in the buried layer. That is, the electric field concentration on the curved surface of the drain contact region is reduced, and the breakdown in the lateral direction can be suppressed. As a result, the electric field concentration is reduced, and the breakdown strength of the element can be improved. Furthermore, since the drain region and the source region are formed in the well layer inside the device, it is possible to prevent the current path from spreading to the source region, so that the resistance of the element can be reduced.

According to a second semiconductor device of the present invention, there is provided a semiconductor substrate of a first conductivity type, a buried layer of a second conductivity type formed on the semiconductor substrate, and a second buried layer formed on the buried layer.
A conductive type epitaxial layer, a first conductive type well layer selectively formed on the surface of the epitaxial layer, a second conductive type source region selectively formed on the surface of the well layer, A drain region of the second conductivity type selectively formed on the surface of the epitaxial layer or the well layer separately from the source region, and higher than the drain region selectively formed on the surface of the drain region; Concentration of a second conductivity type drain contact region, a second conductivity type deep diffusion layer formed in the drain region deeper than a lower surface of the drain region and in contact with the buried layer, the drain region and the source A gate electrode formed insulated from the semiconductor substrate on the semiconductor substrate between the drain contact region and the drain contact region; A first drain electrode electrically connected to the drain region via a contact region, a source electrode formed on the source region and electrically connected to the source region, A second conductivity type separation / diffusion layer formed surrounding the drain region and the source region and in contact with the buried layer; and a second conductivity type separation / diffusion layer formed on the separation / diffusion layer and electrically connected to the first drain electrode. And a distance X ′ between the deep diffusion layer and the source region is longer than a film thickness Y of the epitaxial layer on the buried layer.

According to the second semiconductor device, when a surge is applied through the drain electrode, the surge current is reduced more in the direction of the film thickness Y (vertical direction) than in the direction of the distance X '(horizontal direction).
You can escape to the Lord. As a result, the electric field is more concentrated in the vertical direction than in the horizontal direction, and breakdown occurs in the buried layer. That is, the electric field concentration on the curved surface of the drain contact region is reduced, and the breakdown in the lateral direction can be suppressed. As a result, the electric field concentration is reduced,
The breakdown strength of the element can be improved. Further, since the deep diffusion layer is formed from the substrate surface of the drain portion to the depth reaching the buried layer, the capacitance between the source and the drain can be increased. Therefore, when a surge is applied via the drain electrode, the surge charge can be sufficiently charged with this capacitance, and the surge voltage can be suppressed. As a result, the electric field concentration on the curved surface of the drain contact region is reduced, and the ESD breakdown strength can be improved.

According to a third semiconductor device of the present invention, there is provided a semiconductor substrate of a first conductivity type, a buried layer of a second conductivity type formed on the semiconductor substrate, and a second buried layer formed on the buried layer.
A conductive type epitaxial layer, a first conductive type well layer selectively formed on the surface of the epitaxial layer, a second conductive type source region selectively formed on the surface of the well layer, A second conductivity type drain region selectively formed on the surface of the epitaxial layer or the well layer and separated from the source region; and a drain region which is deeper than the lower surface of the drain region and is in contact with the buried layer. A second conductive type deep diffusion layer having a higher concentration than the drain region, and a gate formed on the semiconductor substrate between the drain region and the source region insulated from the semiconductor substrate. An electrode, a first drain electrode formed on the deep diffusion layer and electrically connected to the drain region via the deep diffusion layer, and a first drain electrode formed on the source region A source electrode electrically connected to the source region, a second conductivity type separation / diffusion layer formed surrounding the drain region and the source region apart from the well layer and in contact with the buried layer; A second drain electrode formed on the isolation diffusion layer and electrically connected to the first drain electrode, wherein a distance X ′ between the deep diffusion layer and the source region is above the buried layer. Is longer than the film thickness Y of the epitaxial layer.

According to the third semiconductor device, the second semiconductor device
The same effects as those of the semiconductor device described above can be obtained.

In the first to third semiconductor devices, it is preferable that the distance X or the distance X ′ is longer than the film thickness Y by 10% to 50% of the film thickness Y.

In the second and third semiconductor devices, it is preferable that the drain region and the source region are formed in the well layer. The concentration of the deep diffusion layer is 3.0 × 10 ¹² cm ^{−3 to} 5.0 × 1.
It is desirably 0 ¹⁵ cm ^-3 .

[0022]

Embodiments of the present invention will be described below with reference to the drawings.

[First Embodiment] In the first embodiment, the distance X between the drain contact region and the source region is longer than the film thickness Y of the epitaxial layer on the buried layer, and prevents miniaturization of the device. It is characterized in that it is not long enough. This suppresses lateral electric field concentration,
The breakdown resistance has been improved.

FIG. 1 is a cross-sectional view of a high breakdown voltage lateral MOSFET according to a first embodiment of the present invention.

As shown in FIG. 1, a p-type semiconductor substrate 11 is formed.
An n-type buried layer 12 is formed on the buried layer 1.
An n-type epitaxial layer 13 is formed on the substrate 2 by epitaxial growth. A p-type well layer 14 is selectively formed on the surface of the epitaxial layer 13, and a low-concentration n ⁻ -type drain region 15 is formed on the surface of the well layer 14.
Are selectively formed. A high-concentration n ⁺ -type source region 16 is selectively formed on the surface of the well layer 14 separately from the drain region 15. Drain region 15
On the semiconductor substrate 11 between the semiconductor substrate 11 and the source region 16, that is, on the channel 17, a gate electrode 18 is formed insulated from the semiconductor substrate 11.

An n ⁺ -type drain contact region 20 having a higher concentration than the drain region 15 is formed on the surface of the drain region 15. Drain contact region 20
A field insulating film 21 is formed on the semiconductor substrate 11 between the gate and the channel 17. A source contact region 22 is formed on the surface of the well layer 14 adjacent to the source region 16.

An n-type separation / diffusion layer 23 is formed so as to surround the well layer 14 so as to be separated from the well layer 14, and the separation / diffusion layer 23 is provided so as to reach an end of the buried layer 12. . On the surface of the isolation diffusion layer 23, an n ⁺ -type drain contact region 24 having a higher concentration than the isolation diffusion layer 23 is formed.

On the semiconductor substrate 11 on which the field insulating film 21 and the respective semiconductor regions are formed, an interlayer insulating film 25 is formed. The interlayer insulating film 25 has a contact hole 26 exposing the surfaces of the drain contact regions 20 and 24.
And a contact hole 27 exposing the surfaces of the source region 16 and the source contact region 22.

The contact hole 26 is formed on the interlayer insulating film 25.
And first and second drain electrodes 28 and 29 in contact with drain contact regions 20 and 24 through contact hole 2
7, source region 16 and source contact region 2
2 is formed in contact with the source electrode 30. The first drain electrode 28 is electrically connected to the drain region 15 through the drain contact region 20, and the source electrode 3
0 is also electrically connected to the well layer 14 via the source contact region 22. Further, one second drain electrode 29 is electrically connected to the other second drain electrode 29 via the drain contact region 24, the separation diffusion layer 23, and the buried layer 12.

Further, a p-type well layer 31 is formed apart from the separation diffusion layer 23, and a p-type buried layer 32 connecting the well layer 31 and the semiconductor substrate 11 is formed. A p ⁺ -type ground contact region 33 having a higher concentration than the well layer 31 is formed on the well layer 31, and a ground electrode 35 in contact with the ground contact region 33 via a contact hole 34 in the interlayer insulating film 25 is formed. Is formed.

In the first embodiment, the distance between the source and the drain, that is, the distance between the n ⁺ -type drain contact region 20 and the n ⁺ -type source region 16 is defined as X, and the distance between the drain and the buried layer is defined as X. That is, the buried layer 1
2, the distance X between the drain contact region 20 and the source region 16 is assumed to be Y.
Is longer than the film thickness Y of the epitaxial layer 13 (X>
Y), and the length is such that the miniaturization of the element is not hindered. For example, the distance X is 1 to the film thickness Y with respect to the film thickness Y.
It is desirable to make it 0% to 50% longer.

According to the first embodiment, the buried layer 12, the isolation diffusion layer 23 and the drain contact region 24
Power MOSFET surrounded by an n-type diffusion layer made of
In T, the distance X between the drain contact region 20 and the source region 16 is longer than the film thickness Y of the epitaxial layer 13 on the buried layer 12 and is set to a length that does not hinder miniaturization of the device.

Therefore, when a surge is applied via the drain electrode 28, the surge current can be mainly released in the direction of the film thickness Y (vertical direction) rather than in the direction of the distance X (horizontal direction). As a result, the electric field is more concentrated in the vertical direction than in the horizontal direction, and breakdown occurs in the n-type buried layer 12. That is, the electric field concentration on the curved surface of the drain contact region 20 is reduced, and the breakdown in the lateral direction can be suppressed. As a result, the electric field concentration is reduced, and the breakdown strength of the element can be improved.

Further, inside the device, the drain region 15 and the source region 16 are formed in the p-well layer 14. Therefore, since the current path can be prevented from spreading to the source region 16, the resistance of the element can be reduced. Thereby, even if the distance X between the drain contact region 20 and the source region 16 is longer than the film thickness Y of the epitaxial layer 13 on the buried layer 12, deterioration of the device performance due to the long distance X is prevented. Is possible.

[Second Embodiment] In the second embodiment, an n-type deep diffusion layer having a high concentration is formed from the substrate surface of the drain portion to a depth reaching the buried layer.
The feature is that the distance X 'between the deep diffusion layer and the source region is longer than the thickness Y of the epitaxial layer on the buried layer and is set to a length that does not hinder miniaturization of the device. Thus, the electric field is concentrated in the vertical direction rather than the horizontal direction, and the capacitance between the source and the drain is increased, thereby improving the breakdown strength. Hereinafter, only the structure different from the first embodiment will be described.

FIG. 2 is a sectional view of a lateral MOSFET for high withstand voltage according to a second embodiment of the present invention.

As shown in FIG. 2, the second embodiment is the first embodiment.
The difference from the first embodiment is that the inside of the drain region 15 is deeper than the lower surface of the drain region 15 and the substrate 1
High concentration of n from one surface to a depth contacting the buried layer 12
That is, the mold deep diffusion layer 19 is formed.
As a result, the second drain electrode 29 includes the drain contact regions 24 and 20, the isolation / diffusion layer 23, and the buried layer 1
2 and the first drain electrode 28 via the deep diffusion layer 19.

In the first embodiment, the p-well layer 1
4, a drain region 15, a source region 16, and a source contact region 22 were formed. In contrast, the second
In the embodiment, the source region 1 is provided in the p-well layer 14 '.
6 and the source contact region 22 only, and the drain region 15 is formed apart from the p-well layer 14 '. The isolation diffusion layer 23 is formed so as to be separated from the p-well layer 14 'and surround the element region in which the drain region 15 and the source region 16 are formed.

The concentration of the above-described deep diffusion layer 19 is set to a value higher than the concentration at which the entire surface of the deep diffusion layer 19 is not depleted when a surge is applied, and lower than the concentration at which generation of a leak current can be suppressed. Therefore, the concentration of the deep diffusion layer 19 is desirably, for example, 3.0 × 10 ¹² cm ^{−3 to} 5.0 × 10 ¹⁵ cm ⁻³ .

In the second embodiment, the distance between the source and the drain, that is, the deep diffusion layer 19 and n ⁺
When the distance from the source region 16 of the mold is X ′ and the distance between the drain and the buried layer, that is, the thickness of the epitaxial layer 13 on the buried layer 12 is Y, the deep diffusion layer 19 is formed.
The distance X ′ between the semiconductor layer and the source region 16 is equal to the epitaxial layer 1
The thickness is longer than the film thickness Y (X> Y) and does not hinder miniaturization of the element. For example, distance X '
Is preferably 10% to 50% longer than the film thickness Y.

According to the second embodiment, similarly to the first embodiment, the distance X ′ between the deep diffusion layer 19 and the source region 16 is different from that of the epitaxial layer 1 on the buried layer 12.
The thickness is longer than the film thickness Y of No. 3 and does not hinder miniaturization of the element. Therefore, when a surge is applied through the drain electrode 28, the surge current can be mainly released in the direction of the film thickness Y (vertical direction) rather than in the direction of the distance X '(horizontal direction). As a result, the electric field is more concentrated in the vertical direction than in the horizontal direction, and breakdown occurs in the n-type buried layer 12. That is, the electric field concentration on the curved surface of the drain contact region 20 is reduced, and the breakdown in the lateral direction can be suppressed. As a result, the electric field concentration is reduced, and the breakdown strength of the element can be improved.

Further, an n-type deep diffusion layer 19 having a high concentration is formed from the surface of the substrate 11 in the drain portion to the depth reaching the buried layer 12. Therefore, the capacitance between the source and the drain can be increased. Therefore, when a surge is applied via the drain electrode 28, the surge charge can be sufficiently charged with this capacitance, and the surge voltage can be suppressed. As a result, the electric field concentration on the curved surface of the drain contact region 20 is further alleviated, and the ESD breakdown strength can be further improved.

Further, the concentration of the deep diffusion layer 19 is set so that the entire surface of the deep diffusion layer 19 is not depleted when a surge is applied. As a result, the electric field concentration due to the surge can be further alleviated, and the ESD resistance can be further improved.

Incidentally, the second embodiment is not limited to the above structure, but may have a structure as described below.

FIG. 3 shows another structure according to the second embodiment. As shown in FIG. 3, as in the first embodiment, the drain region 15 and the source region 16 may be formed in the p-well layer 14 inside the device. In this case, not only the same effects as those in the second embodiment can be obtained, but also
Since the current path can be prevented from spreading to the source region 16, the resistance of the element can be reduced. Further, since there is no need to form a plurality of p-well layers 14 'as in the above-described structure, the manufacturing process is facilitated.

[Third Embodiment] In the third embodiment, as in the second embodiment, a deep diffusion layer is formed from the substrate surface of the drain portion to a depth reaching the buried layer. The feature is that the diffusion layer also functions as a drain contact region. The second
Only the structure different from the above embodiment will be described.

FIG. 4 is a sectional view of a lateral MOSFET for high breakdown voltage according to a third embodiment of the present invention.

As shown in FIG. 4, the third embodiment is the second embodiment.
The difference from this embodiment is that the drain contact region 20 is not provided, and a deep diffusion layer 19 ′ that is in direct contact with the drain electrode 28 is formed in the drain region 15. That is, since the deep diffusion layer 19 ′ also functions as the drain contact region 20, the deep diffusion layer 19 ′ is an n ⁺ -type high concentration diffusion layer like the drain contact region 20.

According to the third embodiment, the same effects as in the second embodiment can be obtained. Further, there is an advantage that the impurity profile becomes uniform and electric field concentration can be further prevented.

Note that the third embodiment is not limited to the above-described structure, and may have a structure as described below.

FIG. 5 shows another structure according to the third embodiment. As shown in FIG. 5, as in the first embodiment, the drain region 15 and the source region 16 may be formed in the p-well layer 14 inside the device. In this case, not only the same effects as those in the third embodiment can be obtained, but also
Since the current path can be prevented from spreading to the source region 16, the resistance of the element can be reduced. Further, since there is no need to form a plurality of p-well layers 14 'as in the above-described structure, the manufacturing process is facilitated.

The present invention can be variously modified and implemented without departing from the gist thereof.

[0053]

As described above, according to the present invention, it is possible to provide a semiconductor device capable of improving the breakdown strength.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a sectional view showing a semiconductor device according to a second embodiment of the present invention.

FIG. 3 is a sectional view showing a semiconductor device having another structure according to the second embodiment of the present invention;

FIG. 4 is a sectional view showing a semiconductor device according to a third embodiment of the present invention.

FIG. 5 is a sectional view showing a semiconductor device having another structure according to the third embodiment of the present invention.

FIG. 6 is a sectional view showing a semiconductor device according to a conventional technique.

[Explanation of symbols]

11 ... p-type semiconductor substrate, 12 ... n-type buried layer, 13 ... n-type epitaxial layer, 14, 14 ', 31 ... p-type well layer, 15 ... n ^- -type drain region, 16 ... n ⁺ -type source region, 17 ... channel, 18 ... gate electrode, 19,19 '... n-type deep diffusion layer, 20, 24 ... n ⁺ type drain contact region, 21 ... field insulating film, 22 ... p ⁺ type source contact region, 23 ... n-type separation Diffusion layer, 25: interlayer insulating film, 26, 27, 34: contact hole, 28, 29: drain electrode, 30: source electrode, 32: p-type buried layer, 33: ground contact region, 35: ground electrode.

Claims (6)

[Claims] A first conductive type semiconductor substrate; a second conductive type buried layer formed on the semiconductor substrate; a second conductive type epitaxial layer formed on the buried layer; A first conductivity type well layer formed on the surface of the second conductive type source region selectively formed on the surface of the well layer; A second conductivity type drain region selectively formed; a second conductivity type drain contact region having a higher concentration than the drain region selectively formed on the surface of the drain region; A gate electrode formed on the semiconductor substrate between the source region and the semiconductor substrate insulated from the semiconductor substrate; and a gate electrode formed on the drain contact region, via the drain contact region. A first drain electrode electrically connected to the drain region, a source electrode formed on the source region and electrically connected to the source region, and a first electrode separated from the well layer and surrounding the well layer. A second conductivity type separation / diffusion layer formed and in contact with the buried layer; and a second drain electrode formed on the separation / diffusion layer and electrically connected to the first drain electrode. A semiconductor device, wherein a distance X between a drain contact region and the source region is longer than a film thickness Y of the epitaxial layer on the buried layer. 2. A semiconductor substrate of a first conductivity type, a buried layer of a second conductivity type formed on the semiconductor substrate, an epitaxial layer of a second conductivity type formed on the buried layer, and the epitaxial layer The first selectively formed on the surface of
A conductivity type well layer; a second conductivity type source region selectively formed on the surface of the well layer; and selectively formed on the surface of the epitaxial layer or the well layer separately from the source region. A second conductivity type drain region, a second conductivity type drain contact region having a higher concentration than the drain region selectively formed on the surface of the drain region, and a lower surface of the drain region in the drain region. And a second conductive type deep diffusion layer formed deeper and in contact with the buried layer, and formed on the semiconductor substrate between the drain region and the source region, insulated from the semiconductor substrate. A gate electrode; a first drain electrode formed on the drain contact region and electrically connected to the drain region via the drain contact region; A source electrode formed on the source region and electrically connected to the source region; and a second electrode formed to surround the drain region and the source region apart from the well layer and to be in contact with the buried layer.
A conductive type separation / diffusion layer; and a second drain electrode formed on the separation / diffusion layer and electrically connected to the first drain electrode, wherein a distance between the deep diffusion layer and the source region is provided. X 'is
A semiconductor device, wherein the thickness is greater than the thickness Y of the epitaxial layer on the buried layer. 3. A semiconductor substrate of a first conductivity type, a buried layer of a second conductivity type formed on the semiconductor substrate, an epitaxial layer of a second conductivity type formed on the buried layer, and the epitaxial layer The first selectively formed on the surface of
A conductivity type well layer; a second conductivity type source region selectively formed on the surface of the well layer; and selectively formed on the surface of the epitaxial layer or the well layer separately from the source region. A drain region of the second conductivity type formed, and a deep diffusion layer of the second conductivity type formed in the drain region deeper than the lower surface of the drain region, in contact with the buried layer, and having a higher concentration than the drain region. A gate electrode formed on the semiconductor substrate between the drain region and the source region so as to be insulated from the semiconductor substrate; a gate electrode formed on the deep diffusion layer; A first drain electrode electrically connected to the region, a source electrode formed on the source region and electrically connected to the source region, A second region formed surrounding the drain region and the source region and in contact with the buried layer;
A conductive type separation / diffusion layer; and a second drain electrode formed on the separation / diffusion layer and electrically connected to the first drain electrode, wherein a distance between the deep diffusion layer and the source region is provided. X 'is
A semiconductor device, wherein the thickness is greater than the thickness Y of the epitaxial layer on the buried layer. 4. The semiconductor device according to claim 2, wherein said drain region and said source region are formed in said well layer. 5. The semiconductor device according to claim 1, wherein the distance X or the distance X ′ is longer than the film thickness Y by 10% to 50% of the film thickness Y. 6. The concentration of the deep diffusion layer is 3.0 ×
The semiconductor device according to claim 2, wherein the semiconductor device has a thickness of 10 ¹² cm ^{−3 to} 5.0 × 10 ¹⁵ cm ⁻³ .