CN116072732A - Silicon carbide MOSFET device integrating Schottky diode - Google Patents

Silicon carbide MOSFET device integrating Schottky diode Download PDF

Info

Publication number
CN116072732A
CN116072732A CN202310092700.7A CN202310092700A CN116072732A CN 116072732 A CN116072732 A CN 116072732A CN 202310092700 A CN202310092700 A CN 202310092700A CN 116072732 A CN116072732 A CN 116072732A
Authority
CN
China
Prior art keywords
region
epitaxial layer
junction field
schottky contact
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202310092700.7A
Other languages
Chinese (zh)
Inventor
李立均
林志东
彭志高
陶永洪
郭元旭
王敏
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hunan Sanan Semiconductor Co Ltd
Original Assignee
Hunan Sanan Semiconductor Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hunan Sanan Semiconductor Co Ltd filed Critical Hunan Sanan Semiconductor Co Ltd
Priority to CN202310092700.7A priority Critical patent/CN116072732A/en
Publication of CN116072732A publication Critical patent/CN116072732A/en
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7803—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device
    • H01L29/7806—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device the other device being a Schottky barrier diode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H01L29/0692—Surface layout
    • H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
    • H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H01L29/872—Schottky diodes
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Manufacturing & Machinery (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

A silicon carbide MOSFET device integrating a Schottky diode relates to the technical field of semiconductors. The device comprises a plurality of cell units, wherein each cell unit consists of two asymmetric first cells and second cells which are connected with each other, a first junction field region and a second Schottky contact region which are connected with each other are arranged between the first cells and the second cells, a first P well region and a first P+ region of the first cells are positioned on one side of the first junction field region far away from the second Schottky contact region, a second P well region and a second P+ region of the second cells are positioned on one side of the second Schottky contact region far away from the first junction field region, and the arrangement directions of the P well region and the P+ region of the first cells and the second cells are consistent. The silicon carbide MOSFET device integrated with the Schottky diode can reduce the grid capacitance, improve the breakdown voltage and further improve the device performance.

Description

Silicon carbide MOSFET device integrating Schottky diode
The present case is a divisional application of the Chinese application filed with application number 202110215037.6 and application date of 2021, 2 and 25.
Technical Field
The present disclosure relates to the field of semiconductor technology, and in particular, to a silicon carbide MOSFET device incorporating a schottky diode.
Background
Silicon carbide metal oxide semiconductor field effect transistors (SiC MOSFETs) are unipolar conductive devices that can operate at higher frequencies as control switches for use in high voltage, high current, high power scenarios. However, because the forbidden bandwidth of the SiC material is high, the parasitic PiN diode has a high turn-on voltage drop and a corresponding loss. Therefore, the current SiC MOSFET device is often connected in anti-parallel with a SiC Schottky diode (SBD) in application, the turn-on voltage of the SiC SBD is low, and the reverse recovery time is shorter, so that the SiC MOSFET device is more suitable for the anti-parallel connection of the SiC MOSFET. Currently, there are two main structures for SiC MOSFET devices that integrate schottky diodes. The first is that the schottky contact electrode is located in the middle of the JFET region, referring to fig. 1, the structure can reduce the gate capacitance, but at the same time, can cause the SiC MOSFET to have larger leakage current and lower breakdown voltage when in the reverse cut-off state; the second is that the schottky contact electrode is located between the ohmic contact metals, referring to fig. 2, the gate capacitance of this structure is larger, and the cell size of the device is increased, which reduces the current density of the device.
Disclosure of Invention
The present disclosure is directed to a silicon carbide MOSFET device integrating a schottky diode that can reduce gate capacitance, increase breakdown voltage, and thus improve device performance.
Embodiments of the present disclosure are implemented as follows:
in one aspect of the present disclosure, a schottky diode integrated silicon carbide MOSFET device is provided, the MOSFET device comprising a plurality of cell units, the cell units being comprised of a first cell and a second cell; the first unit cell comprises a first drain electrode, a first substrate positioned on the first drain electrode, a first N-epitaxial layer arranged on the first substrate, a first Schottky contact region and a first junction field region which are positioned in the first N-epitaxial layer and are arranged at intervals, and the first Schottky contact region and the first junction field region extend from the first N-epitaxial layer to the first substrate; the first N-epitaxial layer is also provided with a first P well region which is connected with the first junction field region and extends from the first N-epitaxial layer to the first substrate; the first N-epitaxial layer is also provided with a first P+ region, the first P+ region is positioned at one side of the first P well region far away from the first junction field region and is connected with the first Schottky contact region, and the first P+ region extends from the first N-epitaxial layer to the first substrate; the first N-epitaxial layer is also provided with a first N+ region which is arranged in the first P well region and connected with the first P+ region, and the first N+ region extends from the first N-epitaxial layer to the first substrate; the first cell further comprises a first Schottky contact metal arranged on the first Schottky contact region, a first ohmic contact metal arranged on the first P+ region and arranged on part of the first N+ region, and a first gate structure; the first gate structure comprises a first gate oxide layer, a first polysilicon gate electrode arranged on the first gate oxide layer and a first interlayer dielectric coating the first gate oxide layer and the first polysilicon gate electrode, the first gate structure is arranged on the first junction field region and extends to be arranged on part of the first N+ region, and the first gate oxide layer extends from part of the first junction field region to the first N+ region to part of the first N+ region; the first cell further comprises a first source electrode arranged on the first Schottky contact metal, the first ohmic contact metal and the first interlayer medium; the second cell comprises a second drain electrode, a second substrate positioned on the second drain electrode, a second N-epitaxial layer arranged on the second substrate, and second Schottky contact areas and second junction field areas which are positioned in the second N-epitaxial layer and are arranged at intervals, wherein the second Schottky contact areas and the second junction field areas extend from the second N-epitaxial layer to the second substrate; the second N-epitaxial layer is also provided with a second P well region which is connected with the second junction field region and extends from the second N-epitaxial layer to the second substrate; the second N-epitaxial layer is also provided with a second P+ region, the second P+ region is positioned at one side of the second P well region far away from the second junction field region and is connected with the second Schottky contact region, and the second P+ region extends from the second N-epitaxial layer to the second substrate; the second N-epitaxial layer is also provided with a second N+ region which is arranged in the second P well region and connected with the second P+ region, and the second N+ region extends from the second N-epitaxial layer to the second substrate; the second cell further comprises a second Schottky contact metal arranged on the second Schottky contact region, a second ohmic contact metal arranged on the second P+ region and arranged on part of the second N+ region, and a second gate structure; the second gate structure comprises a second gate oxide layer, a second polysilicon gate electrode arranged on the second gate oxide layer and a second interlayer dielectric coating the second gate oxide layer and the second polysilicon gate electrode, and is arranged on the second junction field region and extends to be arranged on part of the second N+ region, and the second gate oxide layer extends from part of the second junction field region to the second N+ region to part of the second N+ region; the second cell further includes a second source electrode disposed on the second schottky contact metal, the second ohmic contact metal, and the second interlayer dielectric; the first junction field region in the first cell is connected to the second schottky contact region in the second cell.
Another aspect of the present disclosure provides a silicon carbide MOSFET device incorporating a schottky diode, comprising: a drain electrode; a substrate on the drain; an N-epitaxial layer disposed on the substrate; the N-epitaxial layer comprises a plurality of doped regions which are arranged in an interval manner in the N-epitaxial layer, wherein the doped regions comprise: the P well region and the P+ region extend from the N-epitaxial layer to the substrate; forming a junction field region and a Schottky contact region between adjacent doped regions, wherein the junction field region is connected with the Schottky contact region, the junction field region is connected with the P well region, and the Schottky contact region is connected with the P+ region; the N+ regions are respectively arranged in one corresponding doping region, are connected with the corresponding P+ regions and extend from the N-epitaxial layer to the substrate; the Schottky contact metals are respectively arranged on a corresponding Schottky contact area; the ohmic contact metals are respectively arranged on one corresponding P+ region and extend to the corresponding part of the N+ region; a plurality of gate structures respectively disposed on a corresponding one of the junction field regions and extending over a corresponding portion of the n+ region, the gate structures comprising: the gate oxide layer extends from the corresponding part of the junction field region to the corresponding N+ region and extends to the corresponding part of the N+ region; and the source electrode is arranged on the Schottky contact metal, the ohmic contact metal and the interlayer medium.
The embodiment provides a silicon carbide MOSFET device integrated with a Schottky diode, which comprises a plurality of cell structures, wherein the cell structures are as follows: an N-epitaxial layer having a surface and a back surface; a substrate arranged on the back surface of the N-epitaxial layer; the drain electrode is arranged on one surface of the substrate, which is away from the N-epitaxial layer; the Schottky contact area and the junction field area are arranged at intervals and extend from the surface of the N-epitaxial layer into the N-epitaxial layer; one side of the P well region is connected with the junction field region, and the P well region extends into the N-epitaxial layer from the surface of the N-epitaxial layer; the P+ region is positioned on one side of the P well region far away from the junction field region, is connected with the Schottky contact region and extends into the N-epitaxial layer from the surface of the N-epitaxial layer; the N+ region is connected with the P+ region, is arranged in the P well region and extends from the surface of the N-epitaxial layer into the P well region; a schottky contact metal disposed on the schottky contact region; ohmic contact metal disposed on the p+ region and on a portion of the n+ region; the gate structure comprises a gate oxide layer, a polysilicon gate electrode arranged on the gate oxide layer and an interlayer medium wrapping the gate oxide layer and the polysilicon gate electrode, the gate structure is arranged on the junction field region and extends to be arranged on a part of the N+ region, and the gate oxide layer extends from the part of the junction field region to the N+ region and extends to a part of the N+ region; and the source electrode is arranged on the Schottky contact metal, the ohmic contact metal and the interlayer medium.
The beneficial effects of the present disclosure include:
(1) According to the semiconductor device, the device is arranged to be of an asymmetric structure, the region of the N-epitaxial layer between the P well regions of the two connected cell structures can form the connecting region which is formed by connecting the junction field region and the Schottky contact region, so that the region which is used for forward current conduction and the region which is used for reverse diode freewheeling current can be used for region sharing, and the size of the cell can be reduced.
(2) Meanwhile, the polysilicon gate electrode and the gate oxide layer above the junction field region are partially removed to form Schottky contact metal, so that the area of the polysilicon gate electrode covered above the connection region can be reduced, the gate capacitance, namely the Miller capacitance of the MOSFET, is greatly reduced, and the switching frequency characteristic of the device is further improved.
(3) In addition, by reducing the width of the junction field region and simultaneously enabling the region where the Schottky contact metal is located to be close to the P+ region, the electric field at the Schottky contact position when the device is turned off reversely can be greatly reduced, the electric leakage of the body diode is reduced, and the breakdown voltage is improved; the forward voltage drop of the body diode is small, the conduction loss of the body diode is reduced, and the reverse recovery characteristic of the body diode is improved; and the cell structure of the device is optimized, so that the current density of the device is improved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings that are needed in the embodiments will be briefly described below, it being understood that the following drawings only illustrate some embodiments of the present disclosure and therefore should not be considered as limiting the scope, and other related drawings may be obtained according to these drawings without inventive effort for a person of ordinary skill in the art.
Fig. 1 is a schematic diagram of a prior art integrated schottky diode silicon carbide MOSFET device;
fig. 2 is a schematic diagram of a second prior art integrated schottky diode silicon carbide MOSFET device;
fig. 3 is a schematic structural diagram of a silicon carbide MOSFET device incorporating a schottky diode provided in some embodiments of the present disclosure;
fig. 4 is a schematic diagram of a P-type implanted region in a schottky diode integrated silicon carbide MOSFET device provided in accordance with some embodiments of the present disclosure;
fig. 5 is a schematic diagram of a second P-type implant region in a schottky diode integrated silicon carbide MOSFET device according to some embodiments of the present disclosure;
fig. 6 is a flow chart of a method for fabricating a schottky diode integrated silicon carbide MOSFET device according to some embodiments of the present disclosure;
Fig. 7 is a schematic diagram of one of the states of a silicon carbide MOSFET device incorporating a schottky diode provided in some embodiments of the present disclosure;
fig. 8 is a second schematic state diagram of a schottky diode integrated silicon carbide MOSFET device provided in some embodiments of the present disclosure;
fig. 9 is a third schematic state diagram of a schottky diode integrated silicon carbide MOSFET device provided in some embodiments of the present disclosure;
fig. 10 is a third schematic structural view of a silicon carbide MOSFET device incorporating a schottky diode provided in accordance with some embodiments of the present disclosure;
fig. 11 is a schematic diagram of a silicon carbide MOSFET device incorporating a schottky diode according to some embodiments of the present disclosure;
fig. 12 is a schematic diagram of a silicon carbide MOSFET device integrated with a schottky diode according to some embodiments of the present disclosure.
Icon: 10-a substrate; 11-a first substrate; 12-a second substrate; a 20-N-epitaxial layer; 210-a first N-epitaxial layer; 220-a second N-epitaxial layer; 21A-linking region; 101-a first cell; 102-a second cell; 80-source; 81-a first source; 82-a second source; 90-drain electrode; 91-a first drain; 92-a second drain; 201-a first schottky contact region; 203-a first junction field region; 202-a second schottky contact region; 204-second junction field regions; 301-a first P-well region; 302-a second P well region; 401-a first p+ region; 402-a second p+ region; 501-a first n+ region; 502-a second n+ region; 701-a first schottky contact metal; 702-a second schottky contact metal; 941-a first ohmic contact metal; 942-a second ohmic contact metal; 691-a first gate structure; 692-a second gate structure; 611-a first gate oxide; 612-a second gate oxide; 621-a first polysilicon gate electrode; 622-a second polysilicon gate electrode; 931-a first interlayer dielectric; 932-a second interlayer dielectric; 212-schottky contact region; 34-doped regions; a 30-P well region; a 40-P+ region; a 50-n+ region; 69-gate structure; 61-gate oxide; 62-a polysilicon gate electrode; a 70-schottky contact metal; 93-interlayer dielectric; 94-ohmic contact metal; a 95-P implant region; 100-cell structure; 21-junction field regions; the width of the b-P type injection region along the first direction; a-distance between two adjacent P-type implantation regions; the distance between the c-P type injection region and the adjacent P well region.
Detailed Description
For the purposes of making the objects, technical solutions and advantages of the embodiments of the present disclosure more apparent, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present disclosure, and it is apparent that the described embodiments are some embodiments of the present disclosure, but not all embodiments. The components of the embodiments of the present disclosure, which are generally described and illustrated in the figures herein, may be arranged and designed in a wide variety of different configurations.
Thus, the following detailed description of the embodiments of the present disclosure provided in the accompanying drawings is not intended to limit the scope of the disclosure, as claimed, but is merely representative of selected embodiments of the disclosure. All other embodiments, which can be made by one of ordinary skill in the art without inventive effort, based on the embodiments in this disclosure are intended to be within the scope of this disclosure.
It should be noted that: like reference numerals and letters denote like items in the following figures, and thus once an item is defined in one figure, no further definition or explanation thereof is necessary in the following figures.
In the description of the present disclosure, it should be noted that, directions or positional relationships indicated by terms such as "center", "upper", "lower", "left", "right", "inner", "outer", etc., are directions or positional relationships based on those shown in the drawings, or are directions or positional relationships that are conventionally put in use of the inventive product, are merely for convenience of description of the present disclosure and simplification of description, and are not indicative or implying that the apparatus or element in question must have a specific direction, be configured and operated in a specific direction, and thus should not be construed as limiting the present disclosure. Furthermore, the terms "first," "second," and the like, are used merely to distinguish between descriptions and should not be construed as indicating or implying relative importance.
The silicon carbide MOSFET devices of the present integrated schottky diode are all in a laterally symmetrical structure, and typical structures can be seen in fig. 1 and 2. In fig. 1, the schottky contact metal 70 is located in the middle of the junction field region (i.e., JFET region, hereinafter) to reduce the gate capacitance, but at the same time, the leakage current is larger and the breakdown voltage is lower when the device is in the reverse cut-off state; in fig. 2, the schottky contact metal 70 is located between the left and right ohmic contact metals 94, which results in a separation of the regions through which forward and reverse currents flow, thereby increasing the device cell size, and the polysilicon gate electrode 62 overlies the entire JFET region, resulting in a larger gate capacitance and reduced device current density. Therefore, the embodiment provides a novel silicon carbide MOSFET device integrated with a Schottky diode, so that the forward voltage drop of the body diode can be reduced, the grid capacitance can be reduced, the electric leakage of the diode can be reduced, the breakdown voltage can be improved, the cell structure of the device can be optimized, and the current density of the device can be improved.
Referring to fig. 3, the present embodiment provides a silicon carbide MOSFET device integrated with a schottky diode, the silicon carbide MOSFET device integrated with a schottky diode includes a plurality of cell structures, the cell structures including a drain electrode 90, a substrate 10 disposed on the drain electrode 90, an N-epi layer 20 formed on the substrate 10, and a P-well region 30, a p+ region 40 and an n+ region 50 disposed in the N-epi layer 20, wherein the P-well region 30 is adjacent to the p+ region 40, the n+ region 50 is disposed in the P-well region 30, and the p+ region 40 is adjacent to the n+ region 50; the cell structure further includes a gate oxide 61, an ohmic contact metal 94 and a schottky contact metal 70 on the N-epi layer 20 and in a side-by-side distribution; ohmic contact metal 94 is located between schottky contact metal 70 and gate oxide 61, polysilicon gate electrode 62 is formed on gate oxide 61, and interlayer dielectric 93 is coated on the periphery of polysilicon gate electrode 62; the cell structure further includes a source electrode 80 overlying the interlayer dielectric 93, the ohmic contact metal 94, and the schottky contact metal 70, the interlayer dielectric 93 being used to isolate the source electrode 80 from the gate oxide 61 and the polysilicon gate electrode 62, respectively, and to isolate the ohmic contact metal 94 from the gate oxide 61 and the polysilicon gate electrode 62, respectively (the interlayer dielectric 93 encapsulates the periphery of the gate oxide 61 and the polysilicon gate electrode 62); wherein, the gate oxide 61 covers the surface of the P-well region 30, both sides of which cover part of the surface of the n+ region 50 and part of the surface of the junction field region 21 in the N-epitaxial layer 20, the ohmic contact metal 94 covers the surface of the p+ region 40 and part of the surface of the n+ region 50, and the schottky contact metal 70 is formed on the N-epitaxial layer 20 and located at the side of the p+ region 40 away from the n+ region 50.
Note that, the gate oxide 61, the ohmic contact metal 94 and the schottky contact metal 70 are all formed above the N-epi layer 20, and the ohmic contact metal 94 is located between the schottky contact metal 70 and the gate oxide 61, as shown in fig. 3.
The gate oxide 61 and the ohmic contact metal 94 are isolated, i.e., insulated, by the interlayer dielectric 93, wherein the manner in which the gate oxide 61 and the ohmic contact metal 94 are insulated is not limited. For example, the gate oxide 61 and the ohmic contact metal 94 may be spaced apart to achieve insulation. Here, the interlayer dielectric 93 is not conductive. The specific manner of insulation employed will be within the skill of the art depending upon the situation.
Two cell structures of the silicon carbide MOSFET device integrated with the schottky diode are shown in fig. 3 in a parallel state, wherein the junction field region 21 of each cell structure is located on opposite sides of the cell structure, and the schottky contact region (i.e., the region where the schottky contact metal 70 is located) is located on the left side of the cell structure, so that the two cell structures are connected in parallel, as shown in fig. 3, so that the region where the forward conduction current and the reverse diode current flow can be shared, and thus the cell size can be reduced. Illustratively, the forward conduction current and the reverse diode current share a connection region, which is a region composed of the junction field region 21 and the schottky contact region, which are connected to each other between two adjacent cell structures, so that the cell size can be reduced.
The N-epi layer 20 has a P-well region 30 formed therein, an n+ region 50 located in the P-well region 30, and a p+ region 40 located at the left side of the P-well region 30, wherein the n+ region 50 and the p+ region 40 are located above the N-epi layer 20 (the upper surfaces of the n+ region 50 and the p+ region 40 are exposed out of the N-epi layer 20), the n+ region 50 and the P-well region 30 are adjacent to the p+ region 40, and the n+ region 50 and the P-well region 30 are located at the same side of the p+ region 40. It should be appreciated that since the cell structures of the present disclosure are non-bilateral symmetry structures, the location of the n+ region 50, the p+ region 40, and the P-well region 30 of each cell structure within the N-epitaxial layer 20 of that cell structure is the same. In this embodiment, n+ region 50 is located on the right side of P-well region 30 and p+ region 40 is located in the upper left corner of P-well region 30.
In this embodiment, the orthographic projection of the gate oxide 61 on the N-epi layer 20 covers the upper surface of the P-well region 30 (the upper surface of the P-well region 30 is the portion of the P-well region 30 exposed from the N-epi layer 20), the partial region of the n+ region 50, and the partial region of the junction field region 21.
The schottky contact metal 70 is located above the N-epi layer 20, so that, compared with the prior art (JFET region is separated from schottky contact region) provided in fig. 2, the forward conduction current and reverse diode current regions of this embodiment are shared, i.e. the junction region formed by junction field region 21 and schottky region together, and the area of polysilicon gate electrode 62 covering over junction field region 21 can be reduced by removing a portion of gate oxide layer 61 and polysilicon gate electrode 62 and forming schottky contact metal 70 (schottky contact region can be formed), thereby greatly reducing the gate capacitance and further improving the switching frequency characteristics of the device. Meanwhile, since the forward conduction current and the reverse diode current region of the present disclosure are shared, the width of the junction field region 21 can be further reduced, and the schottky contact region is close to the p+ region 40, so that the electric field at the schottky contact position when the device is turned off in the reverse direction can be greatly reduced, and further, compared with the prior art provided in fig. 1, the disadvantages of larger leakage current and reduced breakdown voltage when the device is turned off in the reverse direction are improved.
In this embodiment, the source electrode 80 is in contact with the schottky contact metal 70 and the ohmic contact metal 94, respectively, and the source electrode 80 may be formed above the interlayer dielectric 93 as shown in fig. 3, for example. Of course, in other embodiments, the source electrode 80 may be formed only on the schottky contact metal 70 and the ohmic contact metal 94, i.e., the portion on the interlayer dielectric 93 may be etched away. When the source electrode 80 is formed only on the schottky contact metal 70 and the ohmic contact metal 94, the interlayer dielectric 93 may not be provided, and the gate oxide 61 and the ohmic contact metal 94 may be spaced apart from each other, so that the gate oxide 61 and the polysilicon gate electrode 62 on the gate oxide 61 are not short-circuited to the ohmic contact metal 94.
In summary, the present embodiment provides a silicon carbide MOSFET device integrated with a schottky diode, which includes a plurality of cell structures including a drain electrode 90, a substrate 10 on the drain electrode 90, an N-epi layer 20 formed on the substrate 10, and a P-well region 30, a p+ region 40 and an n+ region 50 in the N-epi layer 20, wherein the P-well region 30 is adjacent to the p+ region 40, the n+ region 50 is in the P-well region 30, and the p+ region 40 is adjacent to the n+ region 50; the cell structure further includes a gate oxide 61, an ohmic contact metal 94 and a schottky contact metal 70 on the N-epi layer 20 and in a side-by-side distribution; ohmic contact metal 94 is located between schottky contact metal 70 and gate oxide 61, polysilicon gate electrode 62 is formed on gate oxide 61, and interlayer dielectric 93 is coated on the periphery of polysilicon gate electrode 62; the cell structure further includes a source electrode 80 overlying the interlayer dielectric 93, the ohmic contact metal 94, and the schottky contact metal 70, the interlayer dielectric 93 being used to isolate the source electrode 80 from the gate oxide 61 and the polysilicon gate electrode 62, respectively, and the ohmic contact metal 94 from the gate oxide 61 and the polysilicon gate electrode 62, respectively (the interlayer dielectric 93 should be coating the periphery of the gate oxide 61 and the periphery of the polysilicon gate electrode 62); wherein, the gate oxide 61 covers the surface of the P-well region 30, both sides of which cover part of the surface of the n+ region 50 and part of the surface of the junction field region 21 in the N-epitaxial layer 20, the ohmic contact metal 94 covers the surface of the p+ region 40 and part of the surface of the n+ region 50, and the schottky contact metal 70 is formed on the N-epitaxial layer 20 and located at the side of the p+ region 40 away from the n+ region 50. In this way, the device is configured to be in a non-bilateral symmetry structure, so that the region of the N-epitaxial layer 20 between the P-well regions 30 of two adjacent cell structures forms a connection region (in which the region where the schottky contact metal 70 is located is also located) obtained by connecting the junction field region 21 and the schottky contact region, and therefore, the region where forward conduction current flows and the region where reverse diode freewheels flow can be shared, and the size of the cell structure of the present disclosure can be reduced; meanwhile, the polysilicon gate electrode 62 and the gate oxide layer 61 above the junction field region 21 are partially removed to form the schottky contact metal 70, so that the area of the polysilicon gate electrode 62 covered above the junction field region 21 can be reduced, the gate capacitance is greatly reduced, and the switching frequency characteristic of the device is improved; in addition, the width of the junction field region 21 is reduced, and the region where the schottky contact metal 70 is located is close to the p+ region 40, so that the electric field at the schottky contact when the device is turned off in the reverse direction can be greatly reduced, and further the disadvantages of larger leakage current and reduced breakdown voltage in the reverse direction are improved.
Referring again to fig. 4 and 5, in order to further reduce the magnitude of leakage current caused by the schottky contact of the device in the reverse off state, the schottky diode-integrated silicon carbide MOSFET device optionally further includes at least one P-type implant region 95 formed in the N-epitaxial layer 20. In this way, due to the arrangement of the P-type implantation region 95, the depletion of the junction field region 21 in the second direction (in which the second direction is the same direction as the arrangement direction of the p+ region 40 and the n+ region 50) can be enhanced when the device is in the reverse off state, and the peak value of the electric field at the schottky contact is reduced, so that the magnitude of the leakage current when the device is in the reverse off state is reduced.
The P-type implant region 95 may be formed by P ion implantation or p+ ion implantation, for example. When the P-type implant region 95 is formed by p+ ion implantation, it may be formed by itself or may be formed together with the p+ region 40.
Alternatively, the P-type implanted region 95 may include a plurality of P-type implanted regions 95 arranged at intervals along a first direction, and the first direction is perpendicular to the arrangement direction of the p+ region 40 and the n+ region 50.
In addition, the distance a between two adjacent P-type implanted regions may be between 1.0 μm and 100.0 μm, for example, may be 1.0 μm, 5 μm, 10 μm, 30 μm, 50 μm, 80 μm, 100 μm, etc., which are not exemplified.
Also, the width of the P-type implant region along the first direction is between 0.2 μm and 20 μm, wherein the first direction is perpendicular to the arrangement direction of the p+ region 40 and the n+ region 50. Illustratively, the width b of each P-type implanted region along the first direction may be between 0.2 μm and 20.0 μm, such as 0.2 μm, 0.5 μm, 2 μm, 3 μm, 5 μm, 10 μm, 16 μm, 20 μm, etc., which are not further listed.
In one embodiment, referring to fig. 4, optionally, a P-type implant region 95 is connected to the p+ region 40 on one side and to the P-well region 30 of an adjacent cell structure on the other side.
In another embodiment, referring to fig. 5, one side of the P-type implantation region 95 is connected to the p+ region 40, and the other side is spaced apart from the P-well region 30 of the adjacent cell structure.
When one side of the P-type injection region 95 is spaced from the P-well region 30 of the adjacent cell structure, the distance c between the P-type injection region and the P-well region of the adjacent cell structure is smaller than the width of the junction field region 21 along the second direction, wherein the second direction is parallel to the arrangement direction of the p+ region 40 and the n+ region 50. That is, the width direction of the junction field regions 21 is the same as the arrangement direction of the p+ regions 40 and the n+ regions 50 (i.e., the left-right direction of the orientation shown in fig. 5).
In the present embodiment, the material of the schottky contact metal 70 includes at least one of Ti, mo, ni, pt and TiW.
Referring to fig. 6 to 9 in combination, the present embodiment further provides a method for manufacturing a silicon carbide MOSFET device integrated with a schottky diode, the method comprising the steps of:
s110, an N-epitaxial layer 20 is formed on the substrate 10.
S120, a P-well region 30 is formed above the N-epi layer 20 by ion implantation.
The P-well region 30 is located in the N-epi layer 20 and is located above the N-epi layer 20, i.e., the upper surface of the P-well region 30 is exposed from the N-epi layer 20.
S130, two p+ regions 40 and n+ regions 50 are formed adjacently disposed on one side above the P well region 30 by ion implantation.
I.e., p+ region 40 and n+ region 50 are located above P-well region 30 and are exposed from P-well region 30, respectively. Meanwhile, the p+ region 40 and the n+ region 50 are in contact connection and are located on the same side of the P well region 30, as shown in fig. 7, in this embodiment, the p+ region 40 and the n+ region 50 are located at the leftmost side of the P well region 30, the p+ region 40 is located at the left side of the n+ region 50, and the n+ region 50 is located at the right side of the p+ region 40.
S140, a gate oxide layer 61 is formed on the P-well region 30, and the gate oxide layer 61 covers the upper surface of the P-well region 30, a portion of the surface of the n+ region 50 located in the P-well region 30, and the surface of the junction field region 21.
That is, the front projection of the gate oxide 61 on the N-epi layer 20 covers the upper surface of the P-well region 30 (i.e., the surface exposed by the N-epi layer 20), a portion of the surface of the n+ region 50 within the P-well region 30, and the surface of the junction field region 21. Junction field region 21 is located on the side of P-well region 30 remote from p+ region 40 (i.e., to the right of the cell structure) and opposite the orthographic projection of gate oxide 61 onto N-epi layer 20.
S150, a polysilicon gate electrode 62 is formed on the gate oxide 61.
The polysilicon gate electrode 62 covers only the gate oxide 61. Specific implementation this embodiment is not limited, and may be implemented by first depositing a whole layer and then etching.
And S160, depositing an interlayer dielectric 93 on the polysilicon gate electrode 62, and forming ohmic contact holes exposing the P+ region 40 and the N+ region 50 by etching.
And S170, respectively depositing ohmic contact metal 94 in the ohmic contact holes and on the surface of the substrate 10 away from the N-epitaxial layer 20, and forming ohmic contact through a tempering process.
In this way, after depositing the ohmic contact metal 94 in the ohmic contact hole, the ohmic contact metal 94 may be made to cover the upper surface of the p+ region 40 and a portion of the surface of the n+ region 50. It should be noted that the ohmic contact metal (not shown) is deposited on the side of the substrate 10 away from the N-epi layer 20 in order to form an ohmic contact for the subsequent preparation of the drain electrode 90.
S180, etching the interlayer dielectric 93 to form a schottky contact hole exposed in the N-epi layer 20, the schottky contact hole being located on a side of the p+ region 40 away from the n+ region 50.
And S190, depositing a Schottky contact metal 70 in the Schottky contact hole, and forming the Schottky contact through a tempering process.
As shown in fig. 8, an interlayer dielectric 93 may be deposited to insulate the polysilicon gate electrode 62 from the ohmic contact metal 94.
At the same time, the interlayer dielectric 93 may also be used to insulate the source 80 from the polysilicon gate electrode 62 after the source 80 is subsequently formed.
S200, depositing a front side metal on the schottky contact metal 70 and the ohmic contact metal 94 to form the source electrode 80, and depositing a back side metal on the side of the substrate 10 remote from the N-epi layer 20 to form the drain electrode 90.
Referring again to fig. 9, source 80 is located above the device (i.e., also overlying interlayer dielectric 93) and drain 90 is located below the device. Of course, in other embodiments, the source 80 may be deposited only on the schottky contact metal 70 and the ohmic contact metal 94.
In addition, referring to fig. 4, the P-well regions 30 (or the first P-well region 301 and the second P-well region 302 hereinafter) provided in the disclosure are all stripe-shaped.
The P-well regions 30 are arranged in a stripe along a first direction perpendicular to the arrangement direction of the first cells 101 to the second cells 102 on the N-epi layer 20.
The p+ regions 40 (or the first p+ region 401 and the second p+ region 402 hereinafter) provided by the present disclosure are also stripe-shaped. Similarly, the p+ regions 40 are also arranged in a stripe along the first direction.
To more clearly describe the non-bilateral symmetry of the schottky diode integrated silicon carbide MOSFET provided by the present disclosure, the present disclosure describes the silicon carbide MOSFET provided by the present disclosure from the following three ways:
in a first embodiment, the disclosure is illustrated by taking a single cell unit consisting of a first cell 101 and a second cell 102, please refer to fig. 10.
Referring to fig. 10, an embodiment of the present disclosure provides a silicon carbide MOSFET device integrated with a schottky diode, the MOSFET device including a plurality of cell units; the cell unit is composed of a first cell 101 and a second cell 102.
The first cell 101 includes a first drain electrode 91, a first substrate 11 on the first drain electrode 91, a first N-epitaxial layer 210 provided on the first substrate 11, first schottky contact regions 201 and first junction field regions 203 provided in the first N-epitaxial layer 210 at intervals, the first schottky contact regions 201 and the first junction field regions 203 extending from the first N-epitaxial layer 210 toward the first substrate 11; the first N-epitaxial layer 210 is further provided with a first P-well region 301, the first P-well region 301 is connected to the first junction field region 203, and the first P-well region 301 extends from the first N-epitaxial layer 210 to the first substrate 11; the first N-epi layer 210 is further provided with a first p+ region 401, where the first p+ region 401 is located on a side of the first P-well region 301 away from the first junction field region 203 and is connected to the first schottky contact region 201, and the first p+ region 401 extends from the first N-epi layer 210 toward the first substrate 11; the first N-epi layer 210 is further provided with a first n+ region 501, where the first n+ region 501 is disposed in the first P-well region 301 and connected to the first p+ region 401, and the first n+ region 501 extends from the first N-epi layer 210 to the first substrate 11; the first cell 101 further includes a first schottky contact metal 701 disposed on the first schottky contact region 201, a first ohmic contact metal 941 disposed on the first p+ region 401 and disposed on a portion of the first n+ region 501, and a first gate structure 691; the first gate structure 691 includes a first gate oxide 611, a first polysilicon gate electrode 621 disposed on the first gate oxide 611, and a first interlayer dielectric 931 surrounding the first gate oxide 611 and the first polysilicon gate electrode 621, the first gate structure 691 being disposed on the first junction field region 203 and extending over a portion of the first n+ region 501, the first gate oxide 611 extending from the portion of the first junction field region 203 to the first n+ region 501 to a portion of the first n+ region 501; the first cell 101 further includes a first source electrode 81 disposed on the first schottky contact metal 701, the first ohmic contact metal 941, and the first interlayer dielectric 931.
The second cell 102 includes a second drain 92, a second substrate 12 on the second drain 92, a second N-epi layer 220 on the second substrate 12, a second schottky contact region 202 and a second junction field region 204 in the second N-epi layer 220 and spaced apart, the second schottky contact region 202 and the second junction field region 204 extending from the second N-epi layer 220 toward the second substrate 12; a second P-well region 302 is further disposed in the second N-epitaxial layer 220, the second P-well region 302 being connected to the second junction field region 204, the second P-well region 302 extending from the second N-epitaxial layer 220 to the second substrate 12; the second N-epi layer 220 is further provided with a second p+ region 402, which is located on a side of the second P-well region 302 away from the second junction field region 204 and is connected to the second schottky contact region 202, and the second p+ region 402 extends from the second N-epi layer 220 toward the second substrate 12; the second N-epi layer 220 is further provided with a second n+ region 502, where the second n+ region 502 is disposed in the second P-well region 302 and connected to the second p+ region 402, and the second n+ region 502 extends from the second N-epi layer 220 to the second substrate 12; the second cell 102 further includes a second schottky contact metal 702 disposed on the second schottky contact region 202, a second ohmic contact metal 942 disposed on the second p+ region 402 and on a portion of the second n+ region 502, and a second gate structure 692; the second gate structure 692 includes a second gate oxide layer 612, a second polysilicon gate electrode 622 disposed on the second gate oxide layer 612, and a second interlayer dielectric 932 surrounding the second gate oxide layer 612 and the second polysilicon gate electrode 622, the second gate structure 692 being disposed on the second junction field region 204 and extending over a portion of the second n+ region 502, the second gate oxide layer 612 extending from a portion of the second junction field region 204 to the second n+ region 502 to a portion of the second n+ region 502; the second cell 102 further includes a second source 82 disposed on the second schottky contact metal 702, the second ohmic contact metal 942, and the second interlayer dielectric 932.
The first junction field region 203 in the first cell 101 is connected to the second schottky contact region 202 in the second cell 102.
It should be noted that the first junction field region 203 in the first cell 101 and the second schottky contact region 202 in the second cell are connected to form a connection region 21A between the first cell 101 and the second cell 102.
It should be noted that, the arrangement direction of the first P-well region 301 and the first p+ region 401 of the first cell 101 is identical to the arrangement direction of the second P-well region 302 and the second p+ region 402 of the second cell 102.
Note that the first interlayer dielectric 931 is nonconductive and can be used to insulate between the first gate oxide 611 and the first ohmic contact metal 941, respectively; a second interlayer dielectric 932 can be used to insulate between the second gate oxide 612 and the second ohmic contact metal 942, respectively. Of course, the insulation between the first gate oxide 611 and the first ohmic contact metal 941, or between the second gate oxide 612 and the second ohmic contact metal 942 may be implemented in a spaced apart manner, which is not limited in any way.
It is appreciated that a first interlayer dielectric 931 can be used to isolate the first source electrode 81 from the first gate oxide 611 and the first polysilicon gate electrode 621, respectively, and to isolate the first ohmic contact metal 941 from the first gate oxide 611 and the first polysilicon gate electrode 621, respectively. A second interlayer dielectric 932 may be used to isolate the second source 82 from the second gate oxide 612 and the second polysilicon gate electrode 622, respectively, and to isolate the second ohmic contact metal 942 from the second gate oxide 612 and the second polysilicon gate electrode 622, respectively. Thus, the first gate oxide 611 and the first polysilicon gate electrode 621 on the first gate oxide 611 are not shorted to the first ohmic contact metal 941; likewise, the second gate oxide 612 and the second polysilicon gate electrode 622 on the second gate oxide 612 will not be shorted to the second ohmic contact metal 942.
Referring to fig. 10 again, as shown in fig. 10, the silicon carbide MOSFET device is integrated with a schottky diode, that is, any two cells in the silicon carbide MOSFET device integrated with a schottky diode are in a parallel state, wherein a junction field region of each cell and a schottky contact region of an adjacent cell are connected to form a connection region of the adjacent two cells, that is, each cell is provided with a connection region on opposite sides of an arrangement direction of the cells. In this way, two cells connected in parallel can be realized as shown in fig. 10, so that the forward conduction current and the reverse diode current share the connection region 21A, which can reduce the cell size, thereby reducing the size of the device.
It is understood that, based on the first P-well region 301 and the second P-well region 302 being stripe-shaped, the first p+ region 401 and the second p+ region 402 respectively connected to the first P-well region 301 and the second P-well region 302 are also arranged along the first P-well region 301 and the second P-well region 302 respectively. That is, here, the first p+ region 401 and the second p+ region 402 are also arranged in a stripe shape along the first direction.
Referring to fig. 10, in order to further reduce the leakage current caused by the schottky contact of the device in the reverse off state. In some embodiments, the first junction field region 203 and the second schottky contact region 202 are formed with a connection region 21A between the first cell 101 and the second cell 102; a plurality of P-type implanted regions 95 are disposed along the second P-well region 302 within the connection region 21A (the structure of the P-type implanted regions 95 may refer to fig. 4 and 5). Thus, due to the arrangement of the P-type injection region 95, the depletion of the first junction field region 203 in the second direction can be enhanced when the device is in the reverse off state, and the electric field peak value at the schottky contact of the second schottky contact metal 702 can be reduced, so that the leakage current when the device is in the reverse off state can be reduced. The second direction here is the arrangement direction between the first cell 101 and the second cell 102.
The P-type implant region 95 may be formed by P ion implantation, or by p+ ion implantation, for example. When the P-type implantation region 95 is formed by p+ ion implantation, the P-type implantation region can be manufactured independently or can be manufactured together with a p+ region, namely a P well region.
In some embodiments, the P-type implanted regions 95 may include a plurality of P-type implanted regions 95 arranged at intervals along a first direction, which may be understood as a stripe arrangement direction of the first P-well region 301 or the second P-well region 302, or the first direction is perpendicular to the arrangement direction of the first unit cells 101 to the second unit cells 102 on the N-epi layer 20.
In other embodiments, the distance a between any two adjacent P-type implanted regions 95 along the second P-well region 302 is equal. The distance a may be between 1.0 μm and 100.0 μm, for example, may be 1.0 μm, 5 μm, 10 μm, 30 μm, 50 μm, 80 μm, 100 μm, etc., which are not exemplified.
In some embodiments, the width of P-type implant region 95 in the first direction is less than the width of second P-well region 302 in the first direction. Illustratively, the width b of each P-type implant region 95 along the first direction may be between 0.2 μm and 20 μm. For example, 0.2 μm, 0.5 μm, 2 μm, 3 μm, 5 μm, 10 μm, 16 μm, 20 μm, etc., are not exemplified.
In some embodiments, a P-type implant region 95 extends from the N-epi layer 20 toward the substrate 10, one side of the P-type implant region 95 being connected to the second p+ region 402, and the other side of the P-type implant region 95 being connected to the first P-well region 301.
In other embodiments, the P-type implantation region 95 extends from the N-epi layer 20 toward the substrate 10, one side of the P-type implantation region 95 is connected to the second p+ region 402, and the other side of the P-type implantation region 95 has a predetermined distance from the first P-well region 301, see fig. 5.
In some embodiments, the predetermined distance is less than the width of the first junction field region 203 along the direction of the arrangement of the first cell 101 to the second cell 102. That is, the predetermined distance c is smaller than the width of the first junction field region 203 along the second direction, wherein the second direction is the arrangement direction of the first cell 101 and the second cell 102.
In some implementations, the materials of the first and second schottky contact metals 701, 702 described above include at least one of Ti, mo, ni, pt and TiW.
In a second description, referring to fig. 11, a silicon carbide MOSFET device integrated with a schottky diode provided in the present disclosure includes:
a drain electrode 90;
a substrate 10 on the drain electrode 90;
an N-epitaxial layer 20 disposed on the substrate 10;
A plurality of doped regions 34 are disposed in the N-epitaxial layer 20 at intervals, the doped regions 34 comprising: p-well region 30 and p+ region 40, and P-well region 30 and p+ region 40 both extend from N-epitaxial layer 20 toward substrate 10;
a junction field region 21 and a schottky contact region 212 are formed between adjacent doped regions 34, wherein the junction field region 21 is connected to the schottky contact region 212, the junction field region 21 is connected to the P-well region 30, and the schottky contact region 212 is connected to the p+ region 40;
a plurality of n+ regions 50 respectively disposed in a corresponding one of the doped regions 34, the n+ regions 50 being connected to a corresponding p+ region 40, the n+ regions 50 extending from the N-epitaxial layer 20 toward the substrate 10;
a plurality of schottky contact metals 70 respectively disposed on a corresponding one of the schottky contact regions 212;
a plurality of ohmic contact metals 94 respectively disposed on a corresponding one of the p+ regions 40 and extending over a corresponding portion of the n+ region 50;
a plurality of gate structures 69 respectively disposed on a corresponding one of the junction field regions 21 and extending over a corresponding portion of the n+ region 50, the gate structures 69 comprising: a gate oxide layer 61, a polysilicon gate electrode 62 disposed on the gate oxide layer 61, and an interlayer dielectric 93 surrounding the gate oxide layer 61 and the polysilicon gate electrode 62, the gate oxide layer 61 extending from the corresponding partial junction field regions 21 toward the corresponding n+ regions 50 and onto the corresponding partial n+ regions 50;
A source electrode 80 is disposed on the schottky contact metal 70, the ohmic contact metal 94, and the interlayer dielectric 93.
Note that, the gate oxide 61, the ohmic contact metal 94, and the schottky contact metal 70 are all formed above the N-epi layer 20, and the ohmic contact metal 94 is located between the schottky contact metal 70 and the gate oxide 61.
The interlayer dielectric 93 is nonconductive and can be used to insulate the gate oxide 61 from the ohmic contact metal 94, respectively; of course, the insulating manner between the gate oxide 61 and the ohmic contact metal 94 may also be realized in a spaced-apart manner, without any limitation.
It is understood that an interlayer dielectric 93 may be used to isolate the source 80 from the gate oxide 61 and the polysilicon gate electrode 62, respectively. Thus, the gate oxide 61 is not shorted to the ohmic contact metal 94.
Referring to fig. 11 again, as shown in fig. 11, the silicon carbide MOSFET device is integrated with a schottky diode, that is, any two doped regions 34 in the silicon carbide MOSFET device integrated with a schottky diode are connected through a connection region 21A, the junction field region 21 in the connection region 21A is connected to the P-well region 30, and the schottky contact region 212 in the connection region 21A is connected to the p+ region 40. In this way, the forward conduction current and the reverse diode current can share the connection region 21A, which can reduce the cell size, thereby reducing the size of the device.
Referring to fig. 4 and 5 in combination, in some embodiments, the P-well regions 30 are stripe-shaped.
It will be appreciated that the P-well regions 30 are arranged in a stripe along a first direction that is perpendicular to the direction of arrangement between two adjacent doped regions 34 on the N-epi layer 20.
Referring to fig. 4 and 5 in combination, in other embodiments, the p+ region 40 is stripe-shaped.
It is understood that, based on the fact that the P-well region 30 is stripe-shaped, the p+ region 40 connected to the P-well region 30 is also arranged along the P-well region 30. That is, the p+ regions 40 are also arranged in a stripe shape along the first direction.
Referring to fig. 11 again, the front projection of the gate oxide 61 on the N-epi layer 20 covers the upper surface of the corresponding P-well region 30, the partial region corresponding to the n+ region 50, and the partial region corresponding to the junction field region 21. A schottky contact metal 70 is located over the N-epi layer 20 and is connected to an adjacent gate structure 69. Thus, compared to the prior art provided in fig. 2, in which the JEFT region is separated from the schottky contact region 212, the forward current guiding and reverse diode current common connection region 21A of the embodiment of the present disclosure, compared to the prior art of fig. 2, is equivalent to removing a portion of the gate oxide layer 61 of the adjacent gate structure 69 on the connection region 21A and forming the schottky contact metal 70, that is, forming the schottky contact region 212 connected to the junction field region 21, the area of the gate covering over the connection region 21A can be reduced, thereby greatly reducing the gate capacitance and further improving the switching frequency characteristics of the device. Meanwhile, since the forward current and the reverse diode current share the connection region 21A in the embodiment of the present disclosure, the width of the connection region 21A may be further reduced, and the schottky contact region 212 connected to the junction field region 21 may be connected to the p+ region 40, so that the electric field at the schottky contact metal when the device is turned off in the reverse direction may be greatly reduced, and further, the disadvantages of the leakage current bias and the breakdown voltage reduction at the time of the reverse direction turn-off may be improved compared with the prior art provided in fig. 1.
To further reduce the magnitude of leakage current caused by schottky contacts in the reverse off state of the device. In some embodiments, the junction field region 21 and the schottky contact region 212 connected to each other form the connection region 21A, and the MOSFET device further includes:
a plurality of P-type doped implantation structures are respectively disposed in a corresponding one of the connection regions 21A, and the implantation structures include a plurality of P-type implantation regions 95 disposed along the P-well region 30 (the structure of the P-type implantation regions 95 may refer to fig. 4 and 5).
It should be noted that one connection region 21A corresponds to one implantation structure, and one implantation structure includes a plurality of P-type implantation regions 95 disposed along the P-well region 30 (along the strip extending direction of the P-well region 30).
In this way, due to the arrangement of the P-type implantation region 95, the depletion of the junction field region 21 in the second direction can be enhanced when the device is in the reverse off state, and the electric field peak at the schottky contact of the schottky contact metal 70 can be reduced, thereby reducing the magnitude of the leakage current when the device is in the reverse off state. The second direction here is the direction of arrangement between adjacent doped regions 34.
The P-type implant region 95 may be formed by P ion implantation, or by p+ ion implantation, for example. When the P-type implant region 95 is formed by p+ ion implantation, it may be formed by itself or may be formed together with the p+ region 40.
In some embodiments, the P-type implantation regions 95 may include a plurality of P-type implantation regions 95 spaced apart along a first direction, which may be understood as a stripe-shaped layout direction of the P-well region 30.
In some embodiments, the distance between two adjacent P-type implant regions 95 along P-well region 30 is equal. Referring to fig. 11 or 12, the distance a between two adjacent P-type implantation regions 95 is equal. The distance a may be between 1.0 μm and 100.0 μm, for example, may be 1.0 μm, 5 μm, 10 μm, 30 μm, 50 μm, 80 μm, 100 μm, etc., which are not exemplified.
In some embodiments, the width of P-type implant region 95 in the first direction is less than the width of P-well region 30 in the first direction. Illustratively, the width b of each P-type implant region 95 along the first direction may be between 0.2 μm and 20 μm. For example, 0.2 μm, 0.5 μm, 2 μm, 3 μm, 5 μm, 10 μm, 16 μm, 20 μm, etc., are not exemplified.
In some embodiments, P-type implant region 95 extends from N-epitaxial layer 20 toward substrate 10, and the width of P-type implant region 95 along the alignment between two adjacent doped regions 34 is equal to the width of connection region 21A along the alignment between two adjacent doped regions 34.
In other embodiments, the P-type implanted region 95 extends from the N-epitaxial layer 20 toward the substrate 10, and the width of the P-type implanted region 95 along the alignment direction between two adjacent doped regions 34 is smaller than the width of the connection region 21A along the alignment direction between two adjacent doped regions 34.
In some embodiments, one side of the P-type implant region 95 is connected to the corresponding p+ region 40, and the distance between the other side of the P-type implant region 95 and the corresponding P-well region 30 is less than the width of the junction field regions 21 along the alignment direction between adjacent doped regions 34.
Illustratively, the distance between the other side of the P-type implantation region 95 and the corresponding P-well region 30 is a preset distance c that is smaller than the width of the junction field regions 21 along the arrangement direction between the adjacent doped regions 34.
In some implementations, the material of the schottky contact metal 70 described above includes at least one of Ti, mo, ni, pt and TiW.
In a third embodiment, the disclosure describes a single cell structure in detail, please refer to fig. 12.
Referring again to fig. 12, an embodiment of the present disclosure provides a silicon carbide MOSFET device integrated with a schottky diode, the MOSFET device including a plurality of cell structures 100, the cell structures 100 comprising:
an N-epitaxial layer 20 having a front surface and a back surface;
a substrate 10 disposed on the back surface of the N-epitaxial layer 20;
a drain electrode 90 disposed on a side of the substrate 10 facing away from the N-epitaxial layer 20;
the schottky contact region 212 and the junction field region 21 are arranged at intervals, and the schottky contact region 212 and the junction field region 21 extend into the N-epitaxial layer 20 from the surface of the N-epitaxial layer 20;
A P-well region 30, one side of the P-well region 30 being connected to the junction field region 21, the P-well region 30 extending from the surface of the N-epitaxial layer 20 into the N-epitaxial layer 20;
a p+ region 40, the p+ region 40 being located on a side of the P well region 30 away from the junction field region 21 and connected to the schottky contact region 212, the p+ region 40 extending from the surface of the N-epitaxial layer 20 into the N-epitaxial layer 20;
an n+ region 50, the n+ region 50 being connected to the p+ region 40, the n+ region 50 being disposed within the P-well region 30 and extending from the surface of the N-epitaxial layer 20 from within the P-well region 30;
a schottky contact metal 70 disposed on the schottky contact region 212;
ohmic contact metal 94 disposed on p+ region 40 and on a portion of n+ region 50;
gate structure 69, gate structure 69 comprising gate oxide 61, polysilicon gate electrode 62 disposed on gate oxide 61, and interlayer dielectric 93 comprising gate oxide 61 and polysilicon gate electrode 62, gate structure 69 disposed on junction field region 21 and extending over a portion of n+ region 50, and gate oxide 61 extending from a portion of junction field region 21 to n+ region 50 and over a portion of n+ region 50.
In the above embodiment, the silicon carbide MOSFET device is integrated with a schottky diode, that is, any two doped regions 34 in the silicon carbide MOSFET device integrated with a schottky diode are connected through a connection region 21A, and the junction field region 21 in the connection region 21A is connected to the P well region 30, and the schottky contact region 212 in the connection region 21A is connected to the p+ region 40. In this way, the forward conduction current and the reverse diode current can share the connection region 21A, which can reduce the cell size, thereby reducing the size of the device.
In some embodiments, the P-well regions 30 are stripe-shaped. In other embodiments, the p+ regions 40 are also striped.
Referring to fig. 12 again, in a cellular structure 100, the front projection of the gate oxide 61 on the N-epi layer 20 covers the upper surface of the P-well region 30, a partial region of the n+ region 50, and a partial region of the junction field region 21. A schottky contact metal 70 is located over the N-epi layer 20 and is connected to an adjacent gate structure 69. Thus, compared to the prior art provided in fig. 2, in which the JEFT region is separated from the schottky contact region 212, the forward current guiding and reverse diode current common connection region 21A of the embodiment of the present disclosure, compared to the prior art of fig. 2, is equivalent to removing a portion of the gate oxide layer 61 of the adjacent gate structure 69 on the connection region 21A and forming the schottky contact metal 70, that is, forming the schottky contact region 212 connected to the junction field region 21, the area of the gate covering over the connection region 21A can be reduced, thereby greatly reducing the gate capacitance and further improving the switching frequency characteristics of the device. Meanwhile, since the forward current and the reverse diode current share the connection region 21A in the embodiment of the present disclosure, the width of the connection region 21A may be further reduced, and the schottky contact region 212 connected to the junction field region 21 may be connected to the p+ region 40, so that the electric field at the schottky contact metal when the device is turned off in the reverse direction may be greatly reduced, and further, the disadvantages of the leakage current bias and the breakdown voltage reduction at the time of the reverse direction turn-off may be improved compared with the prior art provided in fig. 1.
It should be noted that, as will be understood by those skilled in the art, the technical effects of the embodiments and embodiments of the integrated schottky diode silicon carbide MOSFET device including the plurality of cell structures 100 have been described in detail in the above-mentioned integrated schottky diode silicon carbide MOSFET device or the above-mentioned integrated schottky diode silicon carbide MOSFET device including the plurality of cell units, which will not be described in detail herein.
The foregoing is merely an alternative embodiment of the present disclosure, and is not intended to limit the present disclosure, so that various modifications and variations may be made to the present disclosure by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present disclosure should be included in the protection scope of the present disclosure.
In addition, the specific features described in the foregoing embodiments may be combined in any suitable manner, and in order to avoid unnecessary repetition, the present disclosure does not further describe various possible combinations.

Claims (16)

1. A schottky diode integrated silicon carbide MOSFET device, wherein the MOSFET device comprises a plurality of cell units, the cell units comprising a first cell and a second cell;
the first unit cell comprises a first drain electrode, a first substrate positioned on the first drain electrode, a first N-epitaxial layer arranged on the first substrate, and first Schottky contact areas and first junction field areas which are positioned in the first N-epitaxial layer and are arranged at intervals, wherein the first Schottky contact areas and the first junction field areas extend from the first N-epitaxial layer to the first substrate; a first P well region is further arranged in the first N-epitaxial layer, the first P well region is connected with the first junction field region, and the first P well region extends from the first N-epitaxial layer to the first substrate; a first P+ region is further arranged in the first N-epitaxial layer, the first P+ region is located at one side of the first P well region, which is far away from the first junction field region, and is connected with the first Schottky contact region, and the first P+ region extends from the first N-epitaxial layer to the first substrate; the first N-epitaxial layer is also provided with a first N+ region, the first N+ region is arranged in the first P well region and is connected with the first P+ region, and the first N+ region extends from the first N-epitaxial layer to the first substrate; the first cell further includes a first schottky contact metal disposed on the first schottky contact region, a first ohmic contact metal disposed on the first p+ region and disposed on a portion of the first n+ region, and a first gate structure; the first gate structure comprises a first gate oxide layer, a first polysilicon gate electrode arranged on the first gate oxide layer and a first interlayer dielectric coating the first gate oxide layer and the first polysilicon gate electrode, the first gate structure is arranged on a first junction field region and extends to be arranged on a part of the first N+ region, and the first gate oxide layer extends from the part of the first junction field region to the first N+ region to the part of the first N+ region; the first cell further includes a first source electrode disposed on the first schottky contact metal, the first ohmic contact metal, and the first interlayer dielectric;
The second binary cell comprises a second drain electrode, a second substrate positioned on the second drain electrode, a second N-epitaxial layer arranged on the second substrate, and second Schottky contact areas and second junction field areas which are positioned in the second N-epitaxial layer and are arranged at intervals, wherein the second Schottky contact areas and the second junction field areas extend from the second N-epitaxial layer to the second substrate; a second P well region is further arranged in the second N-epitaxial layer, the second P well region is connected with the second junction field region, and the second P well region extends from the second N-epitaxial layer to the second substrate; a second P+ region is further arranged in the second N-epitaxial layer, is positioned on one side of the second P well region away from the second junction field region, is connected with the second Schottky contact region, and extends from the second N-epitaxial layer to the second substrate; the second N-epitaxial layer is also provided with a second N+ region, the second N+ region is arranged in the second P well region and is connected with the second P+ region, and the second N+ region extends from the second N-epitaxial layer to the second substrate; the second cell further comprises a second Schottky contact metal arranged on the second Schottky contact region, a second ohmic contact metal arranged on the second P+ region and arranged on part of the second N+ region, and a second gate structure; the second gate structure comprises a second gate oxide layer, a second polysilicon gate electrode arranged on the second gate oxide layer and a second interlayer dielectric coating the second gate oxide layer and the second polysilicon gate electrode, the second gate structure is arranged on a second junction field region and extends to be arranged on a part of the second N+ region, and the second gate oxide layer extends from the part of the second junction field region to the second N+ region to the part of the second N+ region; the second cell further includes a second source electrode disposed on the second schottky contact metal, the second ohmic contact metal, and the second interlayer dielectric;
The first junction field region in the first subcell is connected to the second schottky contact region in the second subcell.
2. The schottky diode-integrated silicon carbide MOSFET device of claim 1 wherein said first and second P-well regions are stripe-shaped.
3. The schottky diode-integrated silicon carbide MOSFET device of claim 2 wherein said first p+ region and said second p+ region are stripe-shaped.
4. The schottky diode-integrated silicon carbide MOSFET device of claim 2 wherein said first junction field effect and said second schottky contact region comprise a junction region between said first cell and said second cell; and a plurality of P-type injection regions are arranged in the connection region along the second P-well region.
5. The schottky diode-integrated silicon carbide MOSFET device of claim 4 wherein said P-type implant region extends from said N-epitaxial layer toward said substrate, one side of said P-type implant region being connected to said second p+ region, the other side of said P-type implant region being connected to said first P-well region.
6. The schottky diode-integrated silicon carbide MOSFET device of claim 4 wherein said P-type implant region extends from said N-epitaxial layer toward said substrate, one side of said P-type implant region being connected to said second p+ region, the other side of said P-type implant region being a predetermined distance from said first P-well region.
7. The schottky diode-integrated silicon carbide MOSFET device of claim 6 wherein said predetermined distance is less than a width of said first junction field region along an alignment between said first cell and said second cell.
8. A schottky diode integrated silicon carbide MOSFET device comprising:
a drain electrode;
a substrate on the drain electrode;
an N-epitaxial layer disposed on the substrate;
the N-epitaxial layer comprises a plurality of doped regions which are arranged in the N-epitaxial layer at intervals, wherein the doped regions comprise: a P-well region and a P+ region, both extending from the N-epitaxial layer to the substrate;
forming a junction field region and a Schottky contact region between adjacent doped regions, wherein the junction field region is connected with the Schottky contact region, the junction field region is connected with the P well region, and the Schottky contact region is connected with the P+ region;
the N+ regions are respectively arranged in one corresponding doping region, are connected with the corresponding P+ regions and extend from the N-epitaxial layer to the substrate;
the Schottky contact metals are respectively arranged on a corresponding Schottky contact area;
The ohmic contact metals are respectively arranged on one corresponding P+ region and are arranged on the corresponding part of the N+ region in an extending way;
a plurality of gate structures respectively disposed on a corresponding one of the junction field regions and extending over a corresponding portion of the n+ regions, the gate structures comprising: the gate oxide layer extends from the corresponding part of the junction field region to the corresponding N+ region and extends to the corresponding part of the N+ region;
and the source electrode is arranged on the Schottky contact metal, the ohmic contact metal and the interlayer medium.
9. The schottky diode-integrated silicon carbide MOSFET device of claim 8 wherein said P-well regions are stripe-shaped.
10. The schottky diode-integrated silicon carbide MOSFET device of claim 9 wherein said p+ regions are stripe-shaped.
11. The schottky diode-integrated silicon carbide MOSFET device of claim 8 wherein said junction field region forms a junction region with said schottky contact region associated therewith, said MOSFET device further comprising:
The P-type doped injection structures are respectively arranged in the corresponding one of the connecting regions, and each injection structure comprises a plurality of P-type injection regions arranged along the P-well region.
12. The schottky diode-integrated silicon carbide MOSFET device of claim 11 wherein the distance between adjacent two of said P-type implant regions along said P-well region is equal.
13. The schottky diode-integrated silicon carbide MOSFET device of claim 11 wherein said P-type implant region extends from said N-epitaxial layer toward said substrate, said P-type implant region having a width along an alignment between adjacent two of said doped regions equal to a width of said connection region along an alignment between adjacent two of said doped regions.
14. The schottky diode-integrated silicon carbide MOSFET device of claim 11 wherein said P-type implant region extends from said N-epitaxial layer toward said substrate, said P-type implant region having a smaller width along an alignment between adjacent two of said doped regions than said connection region has along an alignment between adjacent two of said doped regions.
15. The schottky diode-integrated silicon carbide MOSFET device of claim 14 wherein one side of said P-type implant region is connected to a corresponding p+ region and a distance between the other side of said P-type implant region and a corresponding P-well region is less than a width of said junction field region along an alignment direction between adjacent said doped regions.
16. A schottky diode integrated silicon carbide MOSFET device, wherein said MOSFET device comprises a plurality of cell structures, said cell structures comprising:
an N-epitaxial layer having a surface and a back surface;
the substrate is arranged on the back surface of the N-epitaxial layer;
the drain electrode is arranged on one surface of the substrate, which is away from the N-epitaxial layer;
the Schottky contact area and the junction field area are arranged at intervals, and extend into the N-epitaxial layer from the surface of the N-epitaxial layer;
a P-well region, one side of which is connected with the junction field region, and which extends from the surface of the N-epitaxial layer into the N-epitaxial layer;
the P+ region is positioned on one side of the P well region away from the junction field region and is connected with the Schottky contact region, and the P+ region extends from the surface of the N-epitaxial layer into the N-epitaxial layer;
the N+ region is connected with the P+ region, is arranged in the P well region and extends from the surface of the N-epitaxial layer into the P well region;
a schottky contact metal disposed on the schottky contact region;
ohmic contact metal arranged on the P+ region and on part of the N+ region;
A gate structure comprising a gate oxide layer, a polysilicon gate electrode disposed on the gate oxide layer, and an interlayer dielectric surrounding the gate oxide layer and the polysilicon gate electrode, the gate structure disposed on the junction field region and extending over a portion of the n+ region, the gate oxide layer extending from a portion of the junction field region to the n+ region and onto a portion of the n+ region;
and the source electrode is arranged on the Schottky contact metal, the ohmic contact metal and the interlayer medium.
CN202310092700.7A 2021-02-25 2021-02-25 Silicon carbide MOSFET device integrating Schottky diode Pending CN116072732A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202310092700.7A CN116072732A (en) 2021-02-25 2021-02-25 Silicon carbide MOSFET device integrating Schottky diode

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202110215037.6A CN113035955B (en) 2021-02-25 2021-02-25 Silicon carbide MOSFET device integrated with Schottky diode and preparation method thereof
CN202310092700.7A CN116072732A (en) 2021-02-25 2021-02-25 Silicon carbide MOSFET device integrating Schottky diode

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
CN202110215037.6A Division CN113035955B (en) 2021-02-25 2021-02-25 Silicon carbide MOSFET device integrated with Schottky diode and preparation method thereof

Publications (1)

Publication Number Publication Date
CN116072732A true CN116072732A (en) 2023-05-05

Family

ID=76462445

Family Applications (2)

Application Number Title Priority Date Filing Date
CN202310092700.7A Pending CN116072732A (en) 2021-02-25 2021-02-25 Silicon carbide MOSFET device integrating Schottky diode
CN202110215037.6A Active CN113035955B (en) 2021-02-25 2021-02-25 Silicon carbide MOSFET device integrated with Schottky diode and preparation method thereof

Family Applications After (1)

Application Number Title Priority Date Filing Date
CN202110215037.6A Active CN113035955B (en) 2021-02-25 2021-02-25 Silicon carbide MOSFET device integrated with Schottky diode and preparation method thereof

Country Status (2)

Country Link
CN (2) CN116072732A (en)
WO (1) WO2022179096A1 (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116072732A (en) * 2021-02-25 2023-05-05 湖南三安半导体有限责任公司 Silicon carbide MOSFET device integrating Schottky diode
CN114141884A (en) * 2021-12-14 2022-03-04 上海集成电路制造创新中心有限公司 Reconfigurable schottky diode
CN114927562B (en) * 2022-07-20 2022-10-21 深圳平创半导体有限公司 Silicon carbide JFET device structure and preparation method thereof
CN115939177B (en) * 2023-03-10 2023-06-23 江苏长晶科技股份有限公司 Silicon carbide power device and switching element

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5739813B2 (en) * 2009-09-15 2015-06-24 株式会社東芝 Semiconductor device
WO2013177552A1 (en) * 2012-05-24 2013-11-28 Microsemi Corporation Monolithically integrated sic mosfet and schottky barrier diode
US10600903B2 (en) * 2013-09-20 2020-03-24 Cree, Inc. Semiconductor device including a power transistor device and bypass diode
US9583482B2 (en) * 2015-02-11 2017-02-28 Monolith Semiconductor Inc. High voltage semiconductor devices and methods of making the devices
GB2569497B (en) * 2016-09-23 2021-09-29 Dynex Semiconductor Ltd A power MOSFET with an integrated Schottky diode
CN106784008A (en) * 2017-01-22 2017-05-31 北京世纪金光半导体有限公司 A kind of SiC MOSFET elements of integrated schottky diode
CN109742146A (en) * 2018-12-07 2019-05-10 北京大学深圳研究生院 A kind of silicon carbide MOSFET device
CN110998861B (en) * 2019-10-18 2022-03-22 香港应用科技研究院有限公司 Power transistor and method of manufacturing the same
CN112201690A (en) * 2020-09-24 2021-01-08 芜湖启源微电子科技合伙企业(有限合伙) MOSFET transistor
CN112164654B (en) * 2020-09-25 2022-03-29 深圳基本半导体有限公司 Power device integrated with Schottky diode and manufacturing method thereof
CN116072732A (en) * 2021-02-25 2023-05-05 湖南三安半导体有限责任公司 Silicon carbide MOSFET device integrating Schottky diode

Also Published As

Publication number Publication date
CN113035955A (en) 2021-06-25
WO2022179096A1 (en) 2022-09-01
CN113035955B (en) 2023-03-28

Similar Documents

Publication Publication Date Title
US7700971B2 (en) Insulated gate silicon carbide semiconductor device
US8889493B2 (en) Manufacturing method of semiconductor device
CN113035955B (en) Silicon carbide MOSFET device integrated with Schottky diode and preparation method thereof
US8039346B2 (en) Insulated gate silicon carbide semiconductor device and method for manufacturing the same
US10861965B2 (en) Power MOSFET with an integrated pseudo-Schottky diode in source contact trench
CN111081779A (en) Shielding gate trench type MOSFET and manufacturing method thereof
US20210242342A1 (en) Semiconductor device and method for manufacturing same
US20230261073A1 (en) Semiconductor power devices having multiple gate trenches and methods of forming such devices
CN112201690A (en) MOSFET transistor
JP2011210834A (en) Field effect transistor
CN113394277B (en) Cell structure of trench gate IGBT (insulated gate bipolar translator), preparation method of cell structure and trench gate IGBT
JP2008511973A (en) Power semiconductor devices
CN112466922A (en) Semiconductor device with a plurality of semiconductor chips
JP6771433B2 (en) Semiconductor device
US7683454B2 (en) MOS power component with a reduced surface area
CN111668212B (en) Semiconductor device with a semiconductor device having a plurality of semiconductor chips
CN114667609A (en) Vertical field effect transistor and method for constructing the same
US20150364585A1 (en) Power semiconductor device
CN112466923A (en) Semiconductor device with a plurality of semiconductor chips
US20210343708A1 (en) Conduction enhancement layers for electrical contact regions in power devices
US20210343847A1 (en) Diffusion and/or enhancement layers for electrical contact regions
US20220149165A1 (en) Semiconductor devices including an offset metal to polysilicon gate contact
US20230387290A1 (en) Silicon carbide metal oxide semiconductor field effect transistor device
WO2023157422A1 (en) Semiconductor device
US20240128372A1 (en) Method for manufacturing a vertical field effect transistor structure and corresponding vertical field effect transistor structure

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination