CN113035955B - Silicon carbide MOSFET device integrated with Schottky diode and preparation method thereof - Google Patents

Silicon carbide MOSFET device integrated with Schottky diode and preparation method thereof Download PDF

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CN113035955B
CN113035955B CN202110215037.6A CN202110215037A CN113035955B CN 113035955 B CN113035955 B CN 113035955B CN 202110215037 A CN202110215037 A CN 202110215037A CN 113035955 B CN113035955 B CN 113035955B
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contact metal
schottky
gate oxide
oxide layer
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CN113035955A (en
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李立均
林志东
彭志高
陶永洪
郭元旭
王敏
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Hunan Sanan Semiconductor Co Ltd
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Hunan Sanan Semiconductor Co Ltd
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Priority to PCT/CN2021/119953 priority patent/WO2022179096A1/en
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    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7803—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device
    • H01L29/7806—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device the other device being a Schottky barrier diode
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Abstract

A silicon carbide MOSFET device integrated with a Schottky diode and a preparation method thereof relate to the technical field of semiconductors. A P well region and a P + region of the device are adjacent, an N + region is positioned in the P well region, and the P + region and the N + region are adjacent; the ohmic contact metal is positioned between the Schottky contact metal and the gate oxide layer, a polycrystalline silicon gate electrode is formed on the gate oxide layer, and interlayer media are coated on the peripheries of the polycrystalline silicon gate electrode and the gate oxide layer; a source electrode covers the interlayer dielectric, the ohmic contact metal and the Schottky contact metal; the gate oxide layer covers the surface of the P well region, two sides of the gate oxide layer respectively cover the partial surfaces of the N + region and the JFET region in the N-epitaxial layer, ohmic contact metal covers partial surfaces of the P + region and the N + region, and Schottky contact metal is positioned on one side of the P + region far away from the N + region. The silicon carbide MOSFET device integrated with the Schottky diode and the preparation method thereof can reduce the grid capacitance and improve the breakdown voltage, thereby improving the device performance.

Description

Silicon carbide MOSFET device integrated with Schottky diode and preparation method thereof
Technical Field
The invention relates to the technical field of semiconductors, in particular to a silicon carbide MOSFET (metal oxide semiconductor field effect transistor) device integrated with a Schottky diode and a preparation method thereof.
Background
The silicon carbide metal oxide semiconductor field effect transistor (SiC MOSFET) is a single-pole conductive device, can work under the condition of higher frequency as a control switch, and is applied to the scenes of high voltage, large current and high power. However, because the forbidden band width of the SiC material is high, the turn-on voltage drop of the parasitic PiN diode is generally high, and the corresponding loss is also large. Therefore, the current SiC MOSFET device is often connected with a SiC Schottky diode (SBD) in an anti-parallel mode in application, the turn-on voltage of the SiC SBD is low, the reverse recovery time is shorter, and therefore the device is more suitable for the anti-parallel use of the SiC MOSFET.
At present, the SiC MOSFET device integrated with the Schottky diode mainly has two structures. The first is that the schottky contact electrode is located in the middle of the JFET region, please refer to fig. 1, the structure can reduce the gate capacitance, but at the same time, the SiC MOSFET has larger leakage current and lower breakdown voltage when in the reverse cut-off state; secondly, the schottky contact electrode is located between the ohmic contact metals, as shown in fig. 2, the gate capacitance of the structure is larger, the cell size of the device is increased, and the current density of the device is reduced.
Disclosure of Invention
The invention aims to provide a silicon carbide MOSFET device integrated with a Schottky diode and a preparation method thereof, which can reduce the grid capacitance, improve the breakdown voltage and further improve the device performance.
The embodiment of the invention is realized by the following steps:
in one aspect of the invention, a silicon carbide MOSFET device integrated with a Schottky diode is provided, which comprises a plurality of cell structures, wherein each cell structure comprises a drain electrode, a substrate positioned on the drain electrode, an N-epitaxial layer formed on the substrate, a P well region, a P + region and an N + region which are positioned in the N-epitaxial layer, the P well region is adjacent to the P + region, the N + region is positioned in the P well region, and the P + region is adjacent to the N + region; the cell structure also comprises a gate oxide layer, ohmic contact metal and Schottky contact metal which are positioned on the N-epitaxial layer and distributed side by side; the ohmic contact metal is positioned between the Schottky contact metal and the gate oxide layer, a polycrystalline silicon gate electrode is formed on the gate oxide layer, and an interlayer medium is coated on the periphery of the polycrystalline silicon gate electrode; the cell structure also comprises a source electrode covering the interlayer medium, the ohmic contact metal and the Schottky contact metal, wherein the interlayer medium is used for isolating the source electrode from the gate oxide layer and the polysilicon gate electrode respectively and isolating the ohmic contact metal from the gate oxide layer and the polysilicon gate electrode respectively; the gate oxide layer covers the surface of the P well region, the two sides of the gate oxide layer respectively cover the partial surface of the N + region and the partial surface of the junction field effect region in the N-epitaxial layer, the ohmic contact metal covers the surface of the P + region and the partial surface of the N + region, and the Schottky contact metal is formed on the N-epitaxial layer and is positioned on one side of the P + region far away from the N + region. The silicon carbide MOSFET device integrated with the Schottky diode can reduce grid capacitance, improve breakdown voltage and further improve device performance.
Optionally, the schottky diode integrated silicon carbide MOSFET device further comprises at least one P-type implant region formed within the N-epitaxial layer.
Optionally, the P-type implantation regions include a plurality of P-type implantation regions, the P-type implantation regions are arranged at intervals along a first direction, and the first direction is perpendicular to the arrangement direction of the P + region and the N + region.
Optionally, the distance between two adjacent P-type implantation regions is between 1.0 μm and 100.0 μm.
Optionally, the width of the P-type implantation region along a first direction is between 0.2 μm and 20.0 μm, and the first direction is perpendicular to the arrangement direction of the P + region and the N + region.
Optionally, one side of the P-type injection region is connected to the P + region, and the other side is connected to the P well region of the adjacent cell structure.
Optionally, one side of the P-type injection region is connected to the P + region, and the other side of the P-type injection region is spaced from the P-well region of the adjacent cell structure.
Optionally, a distance between the P-type implantation region and the P-well region of the adjacent cellular structure is smaller than a width of the jfet region along a second direction, and the second direction is parallel to the arrangement direction of the P + region and the N + region.
Optionally, the schottky contact metal comprises at least one of Ti, mo, ni, pt, or TiW.
The invention also provides a preparation method of the silicon carbide MOSFET device integrated with the Schottky diode, which comprises the following steps: forming an N-epitaxial layer on a substrate; forming a P well region above the N-epitaxial layer by ion implantation; forming two P + regions and an N + region which are adjacently arranged on one side above the P well region through ion implantation; forming a gate oxide layer on the P well region, wherein the gate oxide layer covers the upper surface of the P well region, part of the surface of the N + region in the P well region and the surface of the junction field effect region; forming a polysilicon gate electrode on the gate oxide layer; depositing an interlayer dielectric on the polysilicon gate electrode, and forming an ohmic contact hole exposing the P + region and the N + region by etching; respectively depositing ohmic contact metal in the ohmic contact holes and on one surface of the substrate far away from the N-epitaxial layer, and forming ohmic contact through a tempering process; etching the interlayer medium to form a Schottky contact hole exposed on the N-epitaxial layer, wherein the Schottky contact hole is positioned on one side of the P + region, which is far away from the N + region; depositing Schottky contact metal in the Schottky contact holes, and forming Schottky contact through a tempering process; and depositing front metal on the Schottky contact metal and the ohmic contact metal to form a source electrode, and depositing back metal on one side of the substrate far away from the N-epitaxial layer to form a drain electrode.
The embodiment provides a silicon carbide MOSFET device integrated with a Schottky diode, which comprises a plurality of cell structures, wherein each cell structure comprises a drain, a substrate positioned on the drain, an N-epitaxial layer formed on the substrate, and a P well region, a P + region and an N + region which are positioned in the N-epitaxial layer, the P well region is adjacent to the P + region, the N + region is positioned in the P well region, and the P + region is adjacent to the N + region; the cellular structure also comprises a gate oxide layer, ohmic contact metal and Schottky contact metal which are positioned on the N-epitaxial layer and distributed side by side; the ohmic contact metal is positioned between the Schottky contact metal and the gate oxide layer, a polycrystalline silicon gate electrode is formed on the gate oxide layer, and an interlayer medium is coated on the periphery of the polycrystalline silicon gate electrode; the cell structure also comprises a source electrode covering the interlayer medium, the ohmic contact metal and the Schottky contact metal, wherein the interlayer medium is used for isolating the source electrode from the gate oxide layer and the polysilicon gate electrode respectively and isolating the ohmic contact metal from the gate oxide layer and the polysilicon gate electrode respectively; the gate oxide layer covers the surface of the P well region, the two sides of the gate oxide layer respectively cover the partial surface of the N + region and the partial surface of the junction field effect region in the N-epitaxial layer, the ohmic contact metal covers the partial surface of the P + region and the partial surface of the N + region, the Schottky contact metal is formed on the N-epitaxial layer and is positioned on one side of the P + region far away from the N + region, and the Schottky contact metal structure has the advantages that:
(1) According to the junction field effect transistor, the device is arranged to be an asymmetric structure, so that a junction field effect region is formed in a region of an N-epitaxial layer between P well regions of two adjacent cellular structures, and therefore the junction field effect region is shared by a forward conduction current flowing region and a reverse diode freewheeling flowing region, and the size of a cellular can be reduced.
(2) Meanwhile, because the polycrystalline silicon gate electrode and the gate oxide layer above the junction field effect region are partially removed to form Schottky contact metal, the area of the polycrystalline silicon gate electrode covering the junction field effect region can be reduced, the gate capacitance (namely the Miller capacitance of the MOSFET) is greatly reduced, and the switching frequency characteristic of the device is improved.
(3) In addition, the width of the junction field effect region is reduced, and meanwhile, the region where the Schottky contact metal is located is close to the P + region, so that the electric field at the Schottky contact position when the device is in reverse cut-off can be greatly reduced, the leakage of a body diode is reduced, and the breakdown voltage is improved; the diode has smaller forward voltage drop of the body diode, reduces the conduction loss of the body diode and improves the reverse recovery characteristic of the diode; and the cellular structure of the device is optimized, and the current density of the device is improved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present invention and therefore should not be considered as limiting the scope, and those skilled in the art can also obtain other related drawings based on the drawings without inventive efforts.
Fig. 1 is one of schematic structural diagrams of a prior art schottky diode integrated silicon carbide MOSFET device;
fig. 2 is a second schematic structural diagram of a prior art schottky diode integrated silicon carbide MOSFET device;
fig. 3 is a schematic structural diagram of a schottky diode integrated silicon carbide MOSFET device according to an embodiment of the present invention;
fig. 4 is one of the schematic diagrams of a P-type implanted region in a schottky diode integrated silicon carbide MOSFET device according to an embodiment of the present invention;
fig. 5 is a second schematic diagram of a P-type implant region in a schottky diode integrated silicon carbide MOSFET device according to an embodiment of the present invention;
fig. 6 is a schematic flow chart of a method for fabricating a schottky diode integrated silicon carbide MOSFET device according to an embodiment of the present invention;
fig. 7 is one of the state diagrams of a schottky diode integrated silicon carbide MOSFET device according to an embodiment of the present invention;
fig. 8 is a second state diagram of a schottky diode integrated silicon carbide MOSFET device according to a second embodiment of the present invention;
fig. 9 is a third state diagram of a schottky diode integrated silicon carbide MOSFET device according to an embodiment of the present invention.
Icon: 10-a substrate; a 20-N-epitaxial layer; a 21-junction field effect region; a 30-P well region; a 40-P + region; a 50-N + region; 61-gate oxide layer; 62-a polysilicon gate electrode; 70-schottky contact metal; 80-source electrode; 90-a drain electrode; 93-interlayer dielectric; 94-ohmic contact metal; a 95-P type implant region; a width of the b-P type implant region along a first direction; a-the distance between two adjacent P-type injection regions; the distance between the c-P type injection region and the P well region of the adjacent cellular structure.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. The components of embodiments of the present invention generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations.
Thus, the following detailed description of the embodiments of the present invention, presented in the figures, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures.
In the description of the present invention, it should be noted that the terms "center", "upper", "lower", "left", "right", "inner", "outer", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings or the orientations or positional relationships that the products of the present invention are usually placed in when used, and are only used for convenience of describing the present invention and simplifying the description, but do not indicate or imply that the devices or elements referred to must have specific orientations, be constructed in specific orientations, and be operated, and thus, should not be construed as limiting the present invention. Furthermore, the terms "first," "second," and the like are used merely to distinguish one description from another, and are not to be construed as indicating or implying relative importance.
The existing silicon carbide MOSFET devices integrated with schottky diodes are all in a bilateral symmetrical structure, and a typical structure can be seen in fig. 1 and 2. In fig. 1, the schottky contact metal 70 is located in the middle of the JFET region (i.e., JFET region, the same below), which can reduce the gate capacitance, but at the same time, can result in a larger leakage current and a lower breakdown voltage when the device is in the reverse off state; the schottky contact metal 70 is located between the left and right ohmic contact metals 94 in fig. 2, which results in a separate area through which forward and reverse currents flow, thereby increasing the cell size of the device, and the polysilicon gate electrode 62 covers the entire JFET region, resulting in a larger gate capacitance and a lower current density of the device. Therefore, the embodiment provides a new silicon carbide MOSFET device integrated with a schottky diode, so as to reduce the forward voltage drop of the body diode, reduce the gate capacitance, reduce the leakage of the diode, improve the breakdown voltage, optimize the cell structure of the device, and improve the current density of the device.
Referring to fig. 3, the present embodiment provides a schottky diode-integrated sic MOSFET device, which includes a plurality of cell structures, each of the cell structures includes a drain 90, a substrate 10 disposed on the drain 90, an N-epitaxial layer 20 formed on the substrate 10, and a P-well region 30, a P + region 40, and an N + region 50 disposed in the N-epitaxial layer 20, the P-well region 30 is adjacent to the P + region 40, the N + region 50 is disposed in the P-well region 30, and the P + region 40 is adjacent to the N + region 50; the cellular structure further comprises a gate oxide layer 61, ohmic contact metal 94 and Schottky contact metal 70 which are positioned on the N-epitaxial layer 20 and distributed in parallel; ohmic contact metal 94 is positioned between the Schottky contact metal 70 and the gate oxide layer 61, a polysilicon gate electrode 62 is formed on the gate oxide layer 61, and the periphery of the polysilicon gate electrode 62 is coated with an interlayer medium 93; the cell structure further comprises a source 80 covering the interlayer dielectric 93, the ohmic contact metal 94 and the schottky contact metal 70, wherein the interlayer dielectric 93 is used for isolating the source 80 from the gate oxide layer 61 and the polysilicon gate electrode 62 respectively, and isolating the ohmic contact metal 94 from the gate oxide layer 61 and the polysilicon gate electrode 62 respectively (the interlayer dielectric 93 covers the peripheries of the gate oxide layer 61 and the polysilicon gate electrode 62); wherein, the gate oxide 61 covers the surface of the P well region 30, and both sides thereof respectively cover a part of the surface of the N + region 50 and a part of the surface of the junction field effect region 21 in the N-epitaxial layer 20, the ohmic contact metal 94 covers the surface of the P + region 40 and a part of the surface of the N + region 50, and the schottky contact metal 70 is formed on the N-epitaxial layer 20 and is located at one side of the P + region 40 far away from the N + region 50.
It should be noted that the gate oxide layer 61, the ohmic contact metal 94 and the schottky contact metal 70 are all formed on the N-epitaxial layer 20, and the ohmic contact metal 94 is located between the schottky contact metal 70 and the gate oxide layer 61, as shown in fig. 3.
The gate oxide layer 61 and the ohmic contact metal 94 are isolated, i.e., insulated, by an interlayer dielectric 93, wherein the manner in which the gate oxide layer 61 and the ohmic contact metal 94 are insulated is not limited. For example, gate oxide layer 61 and ohmic contact metal 94 may be spaced apart to provide insulation. Here, the interlayer dielectric 93 is not conductive. The specific insulation method adopted can be determined by those skilled in the art according to actual conditions.
Shown in fig. 3 is a schottky diode integrated sic MOSFET device in which two cell structures are connected in parallel, wherein the junction field effect region 21 of each cell structure is located on opposite sides of the cell structure, and the schottky contact region (i.e., the region where the schottky contact metal 70 is located) is located on the left side of the cell structure, so that the connection of the two cell structures in parallel is achieved as shown in fig. 3, so that the junction field effect region 21 is shared by the forward conduction current and the reverse diode current, and thus, the cell size can be reduced.
A P-well region 30, an N + region 50 located in the P-well region 30, and a P + region 40 located on the left side of the P-well region 30 are formed in the N-epitaxial layer 20, wherein the N + region 50 and the P + region 40 are respectively located above the N-epitaxial layer 20 (the N + region 50 and the P + region 40 expose the N-epitaxial layer 20 on the upper surface), the N + region 50 and the P-well region 30 are adjacent to the P + region 40, and the N + region 50 and the P-well region 30 are located on the same side of the P + region 40. It should be understood that since the cell structures of the present application are asymmetric structures, the location of the N + region 50, the P + region 40, and the P well region 30 of each cell structure within the N-epi layer 20 of the cell structure is the same. In the present embodiment, N + region 50 is located on the right side of P-well region 30, and P + region 40 is located in the upper left corner of P-well region 30.
In the present embodiment, the orthographic projection of gate oxide layer 61 on N-epitaxial layer 20 covers the upper surface of P well region 30 (i.e., the upper surface of P well region 30 is the portion of P well region 30 exposed to N-epitaxial layer 20), a partial region of N + region 50, and a partial region of junction field region 21.
The schottky contact metal 70 is located above the N-epitaxial layer 20, so that compared to the prior art provided in fig. 2 (where the JFET region is separated from the schottky region), the forward conduction current and the reverse diode current of this embodiment share the JFET region 21, and by removing a portion of the gate oxide layer 61 and the polysilicon gate electrode 62 above the JFET region 21 and forming the schottky contact metal 70 (which may form a schottky contact region), the area of the polysilicon gate electrode 62 covering the JFET region 21 can be reduced, thereby greatly reducing the gate capacitance and further improving the switching frequency characteristics of the device. Meanwhile, because the forward conducting current and the reverse diode current share the junction field effect region 21, the width of the junction field effect region 21 can be further reduced, and meanwhile, the Schottky contact region is close to the P + region 40, so that the electric field at the Schottky contact position when the device is reversely cut off can be greatly reduced, and the disadvantages of large leakage current and reduced breakdown voltage when the device is reversely cut off are further improved compared with the prior art provided by the figure 1.
In the present embodiment, the source electrode 80 is in contact connection with the schottky contact metal 70 and the ohmic contact metal 94, and the source electrode 80 may be formed above the interlayer dielectric 93, for example, as shown in fig. 3. Of course, in other embodiments, the source electrode 80 may be formed only on the schottky contact metal 70 and the ohmic contact metal 94, i.e. the portion on the interlayer dielectric 93 may be etched away. When the source 80 is formed only on the schottky contact metal 70 and the ohmic contact metal 94, the interlayer dielectric 93 may not be provided and the gate oxide layer 61 and the ohmic contact metal 94 may be spaced apart from each other, so that the gate oxide layer 61 and the polysilicon gate electrode 62 on the gate oxide layer 61 may not be short-circuited in contact with the ohmic contact metal 94.
In summary, the present embodiment provides a schottky diode-integrated sic MOSFET device, which includes a plurality of cell structures, each of which includes a drain 90, a substrate 10 disposed on the drain 90, an N-epitaxial layer 20 formed on the substrate 10, and a P-well region 30, a P + region 40, and an N + region 50 disposed in the N-epitaxial layer 20, wherein the P-well region 30 is adjacent to the P + region 40, the N + region 50 is disposed in the P-well region 30, and the P + region 40 is adjacent to the N + region 50; the cellular structure further comprises a gate oxide layer 61, ohmic contact metal 94 and Schottky contact metal 70 which are positioned on the N-epitaxial layer 20 and distributed in parallel; the ohmic contact metal 94 is positioned between the Schottky contact metal 70 and the gate oxide layer 61, a polysilicon gate electrode 62 is formed on the gate oxide layer 61, and the periphery of the polysilicon gate electrode 62 is coated with an interlayer medium 93; the cell structure further comprises a source 80 overlying the interlayer dielectric 93, the ohmic contact metal 94 and the schottky contact metal 70, the interlayer dielectric 93 being used to isolate the source 80 from the gate oxide 61 and the polysilicon gate electrode 62, respectively, and to isolate the ohmic contact metal 94 from the gate oxide 61 and the polysilicon gate electrode 62, respectively (the interlayer dielectric 93 should be a material that covers the outer periphery of the gate oxide 61 and the outer periphery of the polysilicon gate electrode 62); wherein, the gate oxide 61 covers the surface of the P well region 30, and both sides thereof respectively cover a part of the surface of the N + region 50 and a part of the surface of the junction field effect region 21 in the N-epitaxial layer 20, the ohmic contact metal 94 covers the surface of the P + region 40 and a part of the surface of the N + region 50, and the schottky contact metal 70 is formed on the N-epitaxial layer 20 and is located at one side of the P + region 40 far away from the N + region 50. Thus, the device is arranged in an asymmetric structure, so that the junction field effect region 21 is formed in the region of the N-epitaxial layer 20 between the P well regions 30 of two adjacent cell structures (wherein, the region where the schottky contact metal 70 is located is also located in the junction field effect region 21), and therefore, the region through which the forward conducting current flows and the region through which the reverse diode freewheels can share the region, and the size of the cell structure of the present application can be reduced; meanwhile, the Schottky contact metal 70 is formed by removing a part of the polysilicon gate electrode 62 and the gate oxide layer 61 above the junction field effect region 21, so that the area of the polysilicon gate electrode 62 covering the junction field effect region 21 can be reduced, the gate capacitance is greatly reduced, and the switching frequency characteristic of the device is improved; in addition, the width of the junction field effect region 21 is reduced, and the region where the schottky contact metal 70 is located is close to the P + region 40, so that the electric field at the schottky contact position when the device is in reverse cut-off can be greatly reduced, and the disadvantages of large leakage current and reduced breakdown voltage when the device is in reverse cut-off are further improved.
Referring again to fig. 4 and 5 in combination, to further reduce the magnitude of leakage current caused by schottky contacts when the device is in the reverse off state, the schottky diode integrated silicon carbide MOSFET device optionally further includes at least one P-type implant region 95 formed in the N-epitaxial layer 20. Thus, due to the arrangement of the P-type implantation region 95, when the device is in a reverse cut-off state, depletion of the jfet region 21 in the second direction (where the second direction is the same direction as the arrangement direction of the P + region 40 and the N + region 50) can be enhanced, and an electric field peak at the schottky contact can be reduced, so that a leakage current when the device is in the reverse cut-off state can be reduced.
For example, the P-type implantation region 95 may be formed by P ion implantation or P + ion implantation. When the P-type implantation region 95 is formed by P + ion implantation, it may be formed by itself or together with the P + region 40.
Alternatively, the P-type implantation region 95 may include a plurality of P-type implantation regions 95, and the plurality of P-type implantation regions 95 are arranged at intervals along a first direction, which is perpendicular to the arrangement direction of the P + region 40 and the N + region 50.
In addition, the distance a between two adjacent P-type implantation regions can be between 1.0 μm and 100.0 μm, for example, 1.0 μm, 5 μm, 10 μm, 30 μm, 50 μm, 80 μm, 100 μm, etc., which are not listed.
Also, the P-type implant region has a width in a first direction between 0.2 μm and 20 μm, wherein the first direction is perpendicular to the arrangement direction of the P + region 40 and the N + region 50. Illustratively, the width b of each P-type implantation region along the first direction may be between 0.2 μm and 20.0 μm, such as 0.2 μm, 0.5 μm, 2 μm, 3 μm, 5 μm, 10 μm, 16 μm, 20 μm, etc., which are not listed.
In one embodiment, referring to fig. 4, optionally, one side of the P-type implantation region 95 is connected to the P + region 40, and the other side is connected to the P-well region 30 of the adjacent cell structure.
In another embodiment, referring to fig. 5, one side of the P-type implantation region 95 is connected to the P + region 40, and the other side is spaced apart from the P-well region 30 of the adjacent cell structure.
When one side of the P-type injection region 95 is spaced apart from the P-well region 30 of the adjacent cell structure, the distance c between the P-type injection region and the P-well region of the adjacent cell structure is smaller than the width of the jfet region 21 along the second direction, wherein the second direction is parallel to the arrangement direction of the P + region 40 and the N + region 50. That is, the width direction of the junction field region 21 is the same as the arrangement direction of the P + region 40 and the N + region 50 (i.e., the left-right direction of the orientation shown in fig. 5).
In the present embodiment, the material of the schottky contact metal 70 includes at least one of Ti, mo, ni, pt, and TiW.
Referring to fig. 6 to 9, the present embodiment further provides a method for manufacturing a schottky diode-integrated silicon carbide MOSFET device, including the following steps:
s110, an N-epitaxial layer 20 is formed on the substrate 10.
S120, forming a P-well region 30 over the N-epitaxial layer 20 by ion implantation.
The P-well region 30 is located in the N-epitaxial layer 20 and above the N-epitaxial layer 20, i.e., the upper surface of the P-well region 30 is exposed from the N-epitaxial layer 20.
S130, two P + regions 40 and N + regions 50 are formed adjacent to each other on one side above the P well region 30 by ion implantation.
That is, the P + region 40 and the N + region 50 are located above the P-well region 30 and are exposed to the P-well region 30 respectively. Meanwhile, the P + region 40 and the N + region 50 are in contact connection and are respectively located on the same side of the P well region 30, as shown in fig. 7, in the present embodiment, the P + region 40 and the N + region 50 are located on the leftmost side of the P well region 30, the P + region 40 is located on the left side of the N + region 50, and the N + region 50 is located on the right side of the P + region 40.
S140, forming a gate oxide layer 61 on the P-well region 30, and making the gate oxide layer 61 cover the upper surface of the P-well region 30, the partial surface of the N + region 50 located in the P-well region 30, and the surface of the junction field effect region 21.
That is, the orthographic projection of gate oxide layer 61 on N-epitaxial layer 20 covers the upper surface of P-well region 30 (i.e., the surface exposed to N-epitaxial layer 20), a portion of the surface of N + region 50 within P-well region 30, and the surface of junction field region 21. Junction field region 21 is located on a side of P-well region 30 away from P + region 40 (i.e., the right side of the cell structure) and opposite to the orthographic projection of gate oxide 61 on N-epitaxial layer 20.
And S150, forming a polysilicon gate electrode 62 on the gate oxide layer 61.
Note that the polysilicon gate electrode 62 covers only the gate oxide layer 61. The specific implementation manner of this embodiment is not limited, and for example, the implementation may be performed by first depositing a whole layer and then etching.
S160, depositing an interlayer dielectric 93 on the polysilicon gate electrode 62, and forming ohmic contact holes exposing the P + region 40 and the N + region 50 by etching.
And S170, respectively depositing ohmic contact metal 94 in the ohmic contact holes and on the surface of the substrate 10 far away from the N-epitaxial layer 20, and forming ohmic contact through a tempering process.
Thus, after the ohmic contact metal 94 is deposited in the ohmic contact hole, the ohmic contact metal 94 covers the upper surface of the P + region 40 and a portion of the surface of the N + region 50. It should be noted that, an ohmic contact metal (not shown) is deposited on the side of the substrate 10 away from the N-epitaxial layer 20 to form an ohmic contact for subsequently preparing the drain 90.
And S180, etching the interlayer medium 93 to form a Schottky contact hole exposed on the N-epitaxial layer 20, wherein the Schottky contact hole is positioned on one side of the P + region 40 far away from the N + region 50.
S190, depositing a schottky contact metal 70 in the schottky contact hole, and forming a schottky contact through a tempering process.
As shown in fig. 8, depositing an interlayer dielectric 93 may consist in insulating the polysilicon gate electrode 62 from the ohmic contact metal 94.
Meanwhile, the interlayer dielectric 93 may also be used to insulate the source 80 from the polysilicon gate electrode 62 after the source 80 is subsequently formed.
S200, depositing a front metal on the schottky contact metal 70 and the ohmic contact metal 94 to form a source electrode 80, and depositing a back metal on a side of the substrate 10 away from the N-epitaxial layer 20 to form a drain electrode 90.
Referring again to fig. 9, the source 80 is located above the device (i.e., also overlying the interlayer dielectric 93), and the drain 90 is located below the device. Of course, in other embodiments, the source electrode 80 may be deposited only on the schottky contact metal 70 and the ohmic contact metal 94.
The above description is only an alternative embodiment of the present invention and is not intended to limit the present invention, and various modifications and variations of the present invention may occur to those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
It should be noted that, in the above embodiments, the various features described in the above embodiments may be combined in any suitable manner, and in order to avoid unnecessary repetition, the present invention does not separately describe various possible combinations.

Claims (10)

1. The silicon carbide MOSFET device integrated with the Schottky diode comprises a plurality of cell structures, wherein each cell structure is an asymmetric structure and comprises a drain, a substrate positioned on the drain, an N-epitaxial layer formed on the substrate, a P well region, a P + region and an N + region, wherein the P well region is adjacent to the P + region, the N + region is positioned in the P well region, and the P + region is adjacent to the N + region; the cell structure also comprises a gate oxide layer, ohmic contact metal and Schottky contact metal which are positioned on the N-epitaxial layer and distributed side by side; the ohmic contact metal is positioned between the Schottky contact metal and the gate oxide layer, a polycrystalline silicon gate electrode is formed on the gate oxide layer, and an interlayer medium is coated on the periphery of the polycrystalline silicon gate electrode; the cell structure also comprises a source electrode covering above an interlayer medium, ohmic contact metal and Schottky contact metal, wherein the interlayer medium is used for isolating the source electrode from the gate oxide layer and the polysilicon gate electrode respectively and isolating the ohmic contact metal from the gate oxide layer and the polysilicon gate electrode respectively;
the gate oxide layer extends to a part of the N + region from the junction field effect region of the N-epitaxial layer to the P well region, the ohmic contact metal covers the surface of the P + region and a part of the surface of the N + region, and the Schottky contact metal is formed on the N-epitaxial layer and is positioned on one side of the P + region far away from the N + region.
2. The schottky diode-integrated silicon carbide MOSFET device of claim 1 further comprising at least one P-type implant region formed within the N-epitaxial layer.
3. The schottky diode-integrated sic MOSFET device of claim 2 wherein the P-type implant region includes a plurality of P-type implant regions spaced apart along a first direction that is perpendicular to the direction of arrangement of the P + region and the N + region.
4. The schottky diode integrated silicon carbide MOSFET device of claim 3 wherein the distance between two adjacent P-type implant regions is between 1.0 μm and 100.0 μm.
5. The Schottky diode integrated silicon carbide MOSFET device of claim 2 or 4, wherein the width of the P-type implanted region along a first direction is between 0.2 μm and 20.0 μm, and the first direction is perpendicular to the arrangement direction of the P + region and the N + region.
6. The schottky diode integrated silicon carbide MOSFET device of claim 2 wherein the P-type implant region is connected on one side to the P + region and on the other side to a P-well region of an adjacent cell structure.
7. The schottky diode integrated silicon carbide MOSFET of claim 2 wherein the P-type implant region is connected on one side to a P + region and on the other side spaced from a P-well region of an adjacent cell structure.
8. The schottky diode-integrated sic MOSFET device of claim 7, wherein the distance between the P-type implant region and the P-well region of the adjacent cell structure is less than the width of the junction field effect region along a second direction, the second direction being parallel to the direction of arrangement of the P + region and the N + region.
9. The schottky diode integrated silicon carbide MOSFET device of claim 1 wherein the schottky contact metal comprises at least one of Ti, mo, ni, pt, and TiW.
10. A preparation method of a silicon carbide MOSFET device integrated with a Schottky diode is characterized in that the silicon carbide MOSFET device integrated with the Schottky diode comprises a plurality of cellular structures, each cellular structure is an asymmetric structure, and the method comprises the following steps:
forming an N-epitaxial layer on a substrate;
forming a P well region above the N-epitaxial layer by ion implantation;
forming two P + regions and an N + region which are adjacently arranged on one side above the P well region through ion implantation;
forming a gate oxide layer on the P well region, and enabling the gate oxide layer to extend from the junction field effect region of part of the N-epitaxial layer to the direction of the P well region to part of the N + region;
forming a polysilicon gate electrode on the gate oxide layer;
depositing an interlayer dielectric on the polysilicon gate electrode, and forming an ohmic contact hole exposing the P + region and the N + region by etching;
respectively depositing ohmic contact metal in the ohmic contact holes and on one surface of the substrate far away from the N-epitaxial layer, and forming ohmic contact through a tempering process;
etching the interlayer dielectric to form a Schottky contact hole exposed on the N-epitaxial layer, wherein the Schottky contact hole is positioned on one side of the P + region far away from the N + region;
depositing Schottky contact metal in the Schottky contact holes, and forming Schottky contact through a tempering process;
and depositing front metal on the Schottky contact metal and the ohmic contact metal to form a source electrode, and depositing back metal on one side of the substrate far away from the N-epitaxial layer to form a drain electrode.
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