CN113394277B - Cell structure of trench gate IGBT (insulated gate bipolar translator), preparation method of cell structure and trench gate IGBT - Google Patents
Cell structure of trench gate IGBT (insulated gate bipolar translator), preparation method of cell structure and trench gate IGBT Download PDFInfo
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- CN113394277B CN113394277B CN202010165425.3A CN202010165425A CN113394277B CN 113394277 B CN113394277 B CN 113394277B CN 202010165425 A CN202010165425 A CN 202010165425A CN 113394277 B CN113394277 B CN 113394277B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
- H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
- H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
- H01L29/66333—Vertical insulated gate bipolar transistors
- H01L29/66348—Vertical insulated gate bipolar transistors with a recessed gate
Abstract
The disclosure provides a cell structure of a trench gate IGBT, a preparation method thereof and a trench gate IGBT, wherein the cell structure comprises a first conductive type substrate; a first conductivity type drift layer over the substrate; the first trench gate is positioned in the drift layer and at the center of the cellular structure, and the second trench gate penetrates through the first trench gate; an emitter metal layer located above the drift layer; the first groove grid is connected to the emitting electrode metal layer through a first connecting hole, and the second groove grid is isolated from the emitting electrode metal layer through an interlayer dielectric layer. Under the condition of not changing the area of the unit cell, the problem of chip area increase caused by the false grid is solved by integrating the true and false grids in one unit cell. The distance between the grooves and the conducting channel cannot be influenced, the contact area of the emitting electrode is increased, the conductance modulation effect is improved, and the conducting voltage drop is reduced while the blocking voltage is unchanged.
Description
Technical Field
The disclosure relates to the technical field of semiconductor devices, in particular to a cell structure of a trench gate IGBT, a preparation method of the cell structure and the trench gate IGBT.
Background
An Insulated Gate Bipolar Transistor (IGBT) is a composite fully-controlled voltage-driven power semiconductor device composed of BJTs (Bipolar transistors) and MOSFETs (metal oxide semiconductor field effect transistors), combines the low on-resistance and high voltage-withstanding characteristics of BJTs and MOSFETs, and has many excellent characteristics of voltage control, large input impedance, small driving power, small on-resistance, low switching loss, and the like, and is widely used in medium and high power electronic systems.
However, the trench gate IGBT with the conventional structure has a relatively small size, resulting in a high current density and a relatively concentrated current, which is likely to cause a short circuit. As shown in fig. 1, the existing Trench gate IGBT adopts a Dummy gate (Dummy gate Poly) structure to improve the contradictory relationship between the on-state voltage drop and the blocking voltage. The dummy gate is used for increasing the contact area of the emitter, so that the conduction voltage drop is obviously reduced, and the conductance modulation effect is improved. However, since the dummy gate cell does not have any electrical function but only serves to increase the contact area of the emitter, this method wastes a cell area, thereby reducing the effective area of the whole chip by 50%, and if the required current is the same, the chip area is greatly increased.
Disclosure of Invention
In order to solve the problems, the disclosure provides a cell structure of a trench gate IGBT, a preparation method thereof and the trench gate IGBT, and solves the problem of chip area increase caused by a false gate in the prior art.
In a first aspect, the present disclosure provides a cell structure of a trench gate IGBT, including:
a first conductive type substrate;
a first conductive type drift layer over the substrate;
the first trench gate is positioned in the surface of the drift layer and at the center of the cellular structure, and the second trench gate penetrates through the first trench gate;
the second conductive type well region is positioned in the surface of the drift layer, positioned on two sides of the first trench gate and the second trench gate and contacted with the first trench gate and the second trench gate;
the first conductive type source region is positioned in the surface of the well region, positioned on two sides of the first trench gate and the second trench gate and contacted with the first trench gate and the second trench gate;
an emitter metal layer located over the drift layer;
the first trench gate is connected to the emitter metal layer through a first connecting hole, the source region is connected to the emitter metal layer through a second connecting hole, and the second trench gate is isolated from the emitter metal layer through an interlayer dielectric layer.
According to the embodiment of the present disclosure, preferably, the depth of the first trench gate is smaller than the depth of the second trench gate.
According to the embodiment of the present disclosure, preferably, the width of the first trench gate is greater than the width of the second trench gate; the length of the first trench gate is smaller than that of the second trench gate.
According to the embodiment of the present disclosure, preferably, the well region is in contact with a side portion and a bottom portion of the first trench gate and a side portion of the second trench gate.
According to the embodiment of the present disclosure, preferably, a depth of the second trench gate is greater than a depth of the well region.
According to the embodiment of the present disclosure, preferably, the first trench gate includes a first gate trench located in the drift layer surface, a first gate disposed in the first gate trench, and a first gate insulating layer disposed between the first gate trench and the first gate.
According to the embodiment of the present disclosure, preferably, the second trench gate includes a second gate trench located in the drift layer surface, a second gate disposed in the second gate trench, and a second gate insulating layer disposed between the second gate trench and the second gate.
According to an embodiment of the present disclosure, preferably, the cellular structure further includes:
a second conductivity type collector region located under the substrate;
a collector metal layer located below and electrically connected to the collector region.
In a second aspect, the present disclosure provides a method for preparing a cell structure of a trench gate IGBT according to any one of the first aspect, including:
providing a first conductive type substrate;
forming a first conductive type drift layer over the substrate;
forming a first trench gate in the surface of the drift layer at the center of the cellular structure;
forming a second trench gate penetrating through the first trench gate at the central position of the cellular structure in the surface of the drift layer;
injecting second conductive type high-energy ions above the drift layer to form a second conductive type well region which is contacted with the first trench gate and the second trench gate on two sides of the first trench gate and the second trench gate in the surface of the drift layer;
injecting first conductive type high-energy ions into the well region so as to form a first conductive type source region which is contacted with the first trench gate and the second trench gate on two sides of the first trench gate and the second trench gate in the surface of the well region;
forming an interlayer dielectric layer which covers the first trench gate, the second trench gate and the source region simultaneously above the drift layer;
etching the interlayer dielectric layer through a mask to form a first connecting hole penetrating through the interlayer dielectric layer and extending into the first grid electrode of the first trench grid and a second connecting hole penetrating through the interlayer dielectric layer and extending into the source region;
and forming an emitter metal layer above the drift layer, and enabling the emitter metal layer to be connected with the first trench gate through the first connecting hole and the source region through the second connecting hole.
According to the embodiment of the present disclosure, after the step of forming the emitter metal layer over the drift layer, the method further includes the following steps:
implanting second conductivity type high energy ions under the substrate to form a second conductivity type collector region under the substrate;
a collector metal layer electrically connected to the collector region is formed under the collector region.
In a third aspect, the present disclosure provides a cell structure comprising several trench gate IGBTs according to any of the first aspects.
By adopting the technical scheme, the following technical effects can be at least achieved:
the invention provides a cell structure of a trench gate IGBT, a preparation method thereof and a trench gate IGBT, wherein the cell structure comprises a first trench gate and a second trench gate, wherein the first trench gate is positioned in the surface of a drift layer and at the center of the cell structure; the first trench gate is connected to the emitter metal layer through a first connecting hole, and the second trench gate is isolated from the emitter metal layer through an interlayer dielectric layer. Under the condition of not changing the area of the unit cell, the problem of chip area increase caused by the false gate is solved by integrating the true and false gates in one unit cell. The distance between the grooves and the conducting channel cannot be influenced, the contact area of the emitting electrode is increased, the conductance modulation effect is improved, and the conducting voltage drop is reduced while the blocking voltage is unchanged.
Drawings
The accompanying drawings, which are included to provide a further understanding of the disclosure and are incorporated in and constitute a part of this specification, illustrate embodiments of the disclosure and together with the description serve to explain the disclosure without limiting the disclosure. In the drawings:
fig. 1 is a schematic cross-sectional structure diagram of a conventional trench gate IGBT with a dummy gate;
fig. 2 is a schematic diagram of a cell structure of a trench gate IGBT according to an exemplary embodiment of the present disclosure;
fig. 3 is a schematic cross-sectional structure diagram illustrating a cell structure of a trench gate IGBT according to an exemplary embodiment of the present disclosure;
fig. 4 is a schematic flow chart illustrating a method for manufacturing a cell structure of a trench gate IGBT according to an exemplary embodiment of the present disclosure;
fig. 5-15 are schematic diagrams of a front plan view and a cross-sectional structure formed by relevant steps of a method for manufacturing a cell structure of a trench gate IGBT according to an exemplary embodiment of the present disclosure;
fig. 16 is a graph illustrating blocking voltages of a trench gate IGBT and a conventional trench gate IGBT according to an exemplary embodiment of the present disclosure;
fig. 17 is a graph illustrating saturation voltage curves of a trench gate IGBT and a conventional trench gate IGBT according to an exemplary embodiment of the present disclosure.
Detailed Description
Embodiments of the present disclosure will be described in detail with reference to the accompanying drawings and examples, so that how to apply technical means to solve technical problems and achieve the corresponding technical effects can be fully understood and implemented. The embodiments and the features of the embodiments of the present disclosure can be combined with each other without conflict, and the formed technical solutions are all within the protection scope of the present disclosure. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity. Like reference numerals refer to like elements throughout.
It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present disclosure.
It will be understood that spatial relationship terms, such as "above", "below", "beneath", and the like, may be used herein for ease of description to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, then elements or features described as "below" other elements would then be oriented "above" the other elements or features. Thus, the exemplary terms "under" and "under" can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.
Embodiments of the present disclosure are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the present disclosure. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments of the present disclosure should not be limited to the particular shapes of regions illustrated herein, but are to include deviations in shapes that result, for example, from manufacturing. For example, an implanted region shown as a rectangle will typically have rounded or curved features and/or implant concentration gradients at its edges rather than a binary change from implanted to non-implanted region. Also, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation is performed. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the present disclosure.
In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the present disclosure. The following detailed description of the preferred embodiments of the present disclosure, however, the present disclosure may have other embodiments in addition to these detailed descriptions.
Example one
As shown in fig. 2 and fig. 3, the present disclosure provides a cell structure 200 of a trench gate IGBT, which includes a substrate 201, a drift layer 202, a first trench gate 203, a second trench gate 204, a well region 205, a source region 206, a second source region 206, an interlayer dielectric layer 207, a first connection hole 208, a second connection hole 209, an emitter metal layer 210, a collector region 211, and a collector metal layer 212.
It should be noted that, in order to clearly show the shapes and positions of the first trench gate 203, the second trench gate 204, the source region 206, the first connection hole 208 and the second connection hole 209 in fig. 2, the substrate 201, the drift layer 202, the interlayer dielectric layer 207, the emitter metal layer 210, the collector region 211 and the collector metal layer 212 are not shown in fig. 2. The shape and location of the substrate 201, drift layer 202, interlayer dielectric layer 207, emitter metal layer 210, collector region 211, and collector metal layer 212 can be understood in conjunction with fig. 3.
Illustratively, the substrate 201 is a first conductivity type substrate.
The drift layer 102 is a drift layer of the first conductivity type, is located above the substrate 201, and can define the thickness and ion doping concentration of the drift layer 102 formed epitaxially according to different device withstand voltage capabilities.
The first trench gate 203 is disposed in the surface of the drift layer 202 and located at the center of the cell structure 200, the first trench gate 203 includes a first gate trench (not labeled in the figure) in the surface of the drift layer 202, a first gate 2032 disposed in the first gate trench, and a first gate insulating layer 2031 disposed between the first gate trench and the first gate 2032, and the first gate insulating layer 2031 isolates the first gate 2032 from the drift layer 202.
The second trench gate 204 is disposed in the surface of the drift layer 202 and penetrates the first trench gate 203, the second trench gate 204 includes a second gate trench (not labeled in the figure) in the surface of the drift layer 202, a second gate 2042 disposed in the second gate trench, and a second gate insulating layer 2041 disposed between the second gate trench and the second gate 2042, and the second gate insulating layer 2041 isolates the second gate 2042 from the drift layer 202.
The width of the first trench gate 203 is greater than the width of the second trench gate 204, that is, the width of the first gate trench of the first trench gate 203 along the X direction is greater than the width of the second gate trench of the second trench gate 204 along the X direction. The depth of the first trench gate 203 is smaller than the depth of the second trench gate 204, that is, the depth of the first gate trench of the first trench gate 203 in the Z direction is greater than the depth of the second gate trench of the second trench gate 204 in the Z direction. The length of the first trench gate 203 is smaller than that of the second trench gate 204, that is, the length of the first gate trench of the first trench gate 203 in the Y direction is greater than that of the second gate trench of the second trench gate 204 in the Y direction.
The well region 205 is a well region of the second conductivity type, and the well region 205 is located at two sides of the first trench gate 203 and the second trench gate 204, and has a depth smaller than that of the second trench gate 204. The upper surface of the well region 205 is flush with the upper surface of the drift layer 202 and the well region 205 is in contact with the first trench gate 203 and the second trench gate 204. Specifically, the well region 205 is in contact with the side and bottom of the first trench gate 203 and the side of the second trench gate 204.
The source region 206 is a source region of the first conductivity type, the source region 206 is located in the surface of the well region 205 and located at two sides of the first trench gate 203 and the second trench gate 204, one end of the source region 206 close to the center of the cell structure 200 is in contact with the first trench gate 203 and the second trench gate 204, and the upper surface of the source region 206 is flush with the upper surface of the drift layer 202.
An interlayer dielectric layer 207 is located above the drift layer 202 and covers the upper surfaces of the second trench gate 204, the first gate insulating layer 2031, a portion of the first gate 2032 and a portion of the source region 206, so that the second trench gate 204, the first gate insulating layer 2031, a portion of the first gate 2032 and a portion of the source region 206 are isolated from the emitter metal layer 210.
The first gate 2032 of the first trench gate 203 is connected to the emitter metal layer 210 through a first connection hole 208, and the source region 206 is connected to the emitter metal layer 210 through a second connection hole 209. The first gate 2032 is a dummy gate and the second gate 2042 is a true gate, i.e., an active gate. The first connection hole 208 and the second connection hole 209 may be at positions as shown in fig. 2 and 3, or may be at any positions of the first gate 2032 and the source region 206 of the first trench gate 203 as long as the connection of the first gate 2032 and the source region 206 of the first trench gate 203 with the emitter metal layer 210 is achieved.
An emitter metal layer 210 is positioned above the substrate 202 and covers the interlayer dielectric layer 207, the first connection hole 208 and the upper surface of the second connection hole 209.
The structure in which the first gate 2032 is connected to the emitter metal layer 210 through the first connection hole 208 increases an emitter contact area, thereby improving a conductance modulation effect and reducing a turn-on voltage drop without changing a blocking voltage. Under the condition of not changing the area of the unit cell, the real and false gates are integrated in one unit cell, so that the problem of chip area increase caused by the false gates is solved, and the space between the grooves of the real gates and a conducting channel are not influenced.
The collector region 211 is a collector region substrate 201 of the second conductivity type, located below the substrate 201.
A collector metal layer 212 is located below the substrate 201 and forms an electrical connection with the substrate 201.
In this embodiment, the first conductivity type is opposite to the second conductivity type. For example, when the first conductivity type is N-type, the second conductivity type is P-type; when the first conductive type is P type, the second conductive type is N type. Specifically, the type of the device to be manufactured may be selected appropriately according to actual needs.
In the present embodiment, a cell structure 200 of a trench gate IGBT is provided, the cell structure including a first trench gate 203 located in a drift layer 202 and at a central position of the cell structure 200, and a second trench gate 204 penetrating the first trench gate 203; the first trench gate 203 is connected to the emitter metal layer 210 through the first connection hole 208, and the second trench gate 204 is isolated from the emitter metal layer 210 by the interlayer dielectric layer 207. Under the condition of not changing the area of the unit cell, the problem of chip area increase caused by the false gate is solved by integrating the true and false gates in one unit cell. The distance between the grooves and the conducting channel cannot be influenced, the contact area of the emitting electrode is increased, the conductance modulation effect is improved, and the conducting voltage drop is reduced while the blocking voltage is unchanged.
Example two
On the basis of the first embodiment, the present embodiment provides a method for manufacturing the cell structure 200 of the trench gate IGBT. Fig. 4 is a schematic flow chart of a method for manufacturing a cell structure 200 of a trench gate IGBT according to an embodiment of the present disclosure. Fig. 5-15 are schematic front plan views and cross-sectional structural diagrams formed by relevant steps of a method for manufacturing a cell structure 200 of a trench gate IGBT according to an embodiment of the disclosure. Fig. 6, 8 and 10 are schematic front top views formed in relevant steps of a method for manufacturing a cell structure 200 of a trench gate IGBT. Next, detailed steps of an exemplary method for manufacturing the cell structure 200 of the trench gate IGBT according to the embodiment of the present disclosure are described with reference to fig. 4 and fig. 5 to fig. 15.
As shown in fig. 4, the method for manufacturing the cell structure 200 of the trench gate IGBT of the present embodiment includes the following steps:
step S101: a first conductivity type substrate 201 is provided.
The substrate 201 is an epitaxial silicon wafer or a silicon wafer grown by a floating zone method (i.e., FZ method).
Step S102: as shown in fig. 5, a first conductive type drift layer 202 is formed over a substrate 201.
The drift layer 202 is formed by CVD epitaxy.
Step S103: as shown in fig. 6 and 7, a first trench gate 203 is formed in the surface of the drift layer 202 at the center of the cell structure.
Specifically, a first gate trench (not labeled in the figure) is formed in the surface of the drift layer 202 by a reticle etching, a first gate insulating layer 2031 covering the wall and the bottom of the first gate trench is formed, and then polysilicon is filled in the first gate trench to form a first gate 2032.
Step S104: as shown in fig. 8 and 9, a second trench gate 204 penetrating the first trench gate 203 is formed in the drift layer 202 at the center of the cell structure.
Specifically, a second gate trench (not labeled in the figure) penetrating through the first trench gate 203 is formed in the drift layer 202 by mask etching, in this process, a portion of the first gate insulating layer 2031 and the first gate 2032 are etched away, then a second gate insulating layer 2041 covering the wall and the bottom of the second gate trench is formed, and then polysilicon is filled in the second gate trench to form the second gate 2042.
The width of the first trench gate 203 is greater than the width of the second trench gate 204, and the width is the width of the first trench gate 203 and the second trench gate 204 along the X direction. The depth of the first trench gate 203 is smaller than that of the second trench gate 204, and the depth is the depth of the first trench gate 203 and the second trench gate 204 in the Z direction. The length of the first trench gate 203 is smaller than that of the second trench gate 204, and the length is the length of the first trench gate 203 and the second trench gate 204 in the Y direction.
Step S105: second conductivity type high energy ions are implanted over the drift layer 202 to form second conductivity type well regions 205 in the drift layer 202 in contact with the first trench gate 203 and the second trench gate 204 on both sides of the first trench gate 203 and the second trench gate 204.
Specifically, second conductivity type high energy ions are implanted above the drift layer 202, and a drive-in process is performed to form a second conductivity type well region 205 in the drift layer 202 on both sides of the first trench gate 203 and the second trench gate 204. The depth of the well region 205 is smaller than the depth of the second trench gate 204. The upper surface of the well region 205 is flush with the upper surface of the drift layer 202 and the well region 205 is in contact with the first trench gate 203 and the second trench gate 204.
Step S106: as shown in fig. 10 and 11, first conductivity type high energy ions are implanted in the well region 205 to form first conductivity type source regions 206 in contact with the first trench gate 203 and the second trench gate 204 on both sides of the first trench gate 203 and the second trench gate 204 in the well region 205, respectively.
Specifically, first conductivity type high energy ions are implanted into the well region 205, and a rapid annealing process is performed to form first conductivity type source regions 206 on two sides of the first trench gate 203 and the second trench gate 204 in the surface of the well region 205, respectively. One end of the source region 206 close to the center of the cell structure 200 is in contact with the first trench gate 20 and the second trench gate 204, and the upper surface of the source region 206 is flush with the upper surface of the drift layer 202.
Step S107: as shown in fig. 12, an interlayer dielectric layer 207 is formed over the drift layer 202 while covering the first trench gate 203, the second trench gate 204, and the source region 206.
Specifically, an interlayer dielectric layer 207 is formed over the drift layer 202 by chemical vapor deposition, and covers the first trench gate 203, the second trench gate 204, and the source region 206.
Step S108: as shown in fig. 13, the interlayer dielectric layer 207 is etched by a reticle to form a first connection hole 208 penetrating the interlayer dielectric layer 207 and extending into the first gate 2032 of the first trench gate 203, and a second connection hole 209 penetrating the interlayer dielectric layer 207 and extending into the source region 206.
Step S109: as shown in fig. 14, an emitter metal layer 210 is formed over the drift layer 202, and the emitter metal layer 210 is connected to the first trench gate 203 through the first connection hole 208 and to the source region 206 through the second connection hole 209.
Specifically, an emitter metal layer 210 is formed over the drift layer 202 by a sputtering method, and in this process, the first connection hole 208 and the second connection hole 209 are filled with the material of the emitter metal layer 210. And the emitter metal layer 210 is isolated from the second trench gate 204 by the interlayer dielectric layer 207.
The first gate 2032 is connected to the emitter metal layer 210 through the first connection hole 208, so that the emitter contact area is increased, the conductance modulation effect is improved, and the on-state voltage drop is reduced without changing the blocking voltage. Under the condition of not changing the area of the unit cell, the real and false gates are integrated in one unit cell, so that the problem of chip area increase caused by the false gates is solved, and the space between the grooves of the real gates and a conducting channel are not influenced.
Step S110: second conductive-type high-energy ions are implanted under the substrate 201 to form a second conductive-type collector region 211 under the substrate 201.
Step S111: as shown in fig. 15, a collector metal layer 212 electrically connected to the collector region 211 is formed below the collector region 211.
Specifically, a collector metal layer 212 electrically connected to the collector region 211 is formed below the collector region 211 by a sputtering method. The collector metal layer 212 may be a metal such as titanium, nickel, gold, or the like.
In this embodiment, the first conductivity type is opposite to the second conductivity type. For example, when the first conductivity type is N-type, the second conductivity type is P-type; when the first conductive type is P type, the second conductive type is N type. Specifically, the type of the device to be manufactured may be selected appropriately according to actual needs.
In the present embodiment, a method for manufacturing a cell structure 200 of a trench gate IGBT is provided, including forming a first trench gate 203 in a drift layer 202 at a center of the cell structure and forming a second trench gate 204 penetrating the first trench gate 203 in the drift layer 202 at the center of the cell structure, where the first trench gate 203 is connected to an emitter metal layer 210 through a first connection hole 208, a source region 206 is electrically connected to the emitter metal layer 210 through a second connection hole 209, and the emitter metal layer 210 is separated from the second trench gate 204 by an interlayer dielectric layer 207. Under the condition of not changing the area of the unit cell, the problem of chip area increase caused by the false gate is solved by integrating the true and false gates in one unit cell. The distance between the grooves and the conducting channel cannot be influenced, the contact area of the emitting electrode is increased, the conductance modulation effect is improved, and the conducting voltage drop is reduced while the blocking voltage is unchanged.
EXAMPLE III
On the basis of the first embodiment, the present embodiment provides a trench gate IGBT including a plurality of cell structures 200 of the trench gate IGBT according to the first embodiment.
Fig. 16 is a graph illustrating the blocking voltage of a trench gate IGBT and a conventional trench gate IGBT according to an exemplary embodiment of the present disclosure, and as shown in fig. 16, two curves substantially coincide to illustrate that the trench gate IGBT and the conventional trench gate IGBT provided by the present disclosure have the same blocking voltage capability, and therefore the structure of integrating the first trench gate 203 and the second trench gate 204 provided by the present disclosure in one cell does not affect the blocking voltage capability of the trench gate IGBT.
Fig. 17 is a graph illustrating saturation voltage curves of a trench gate IGBT and a conventional trench gate IGBT according to an exemplary embodiment of the disclosure, and as shown in fig. 17, compared with the conventional trench gate IGBT, the trench gate IGBT provided by the present embodiment has a lower saturation voltage and thus a lower turn-on voltage drop at the same current.
It should be noted that the conventional trench gate IGBT is a typical structure trench gate IGBT without a dummy gate.
In summary, the present disclosure provides a cell structure of a trench gate IGBT, a method for manufacturing the same, and a trench gate IGBT, where the cell structure includes a first trench gate located in a drift layer and at a center of the cell structure, and a second trench gate penetrating through the first trench gate; the first trench gate is connected to the emitter metal layer through the first connecting hole, and the interlayer dielectric layer between the second trench gate and the emitter metal layer is isolated. Under the condition of not changing the area of the unit cell, the problem of chip area increase caused by the false gate is solved by integrating the true and false gates in one unit cell. The distance between the grooves and the conducting channel cannot be influenced, the contact area of the emitting electrode is increased, the conductance modulation effect is improved, and the conducting voltage drop is reduced while the blocking voltage is unchanged.
The above is merely a preferred embodiment of the present disclosure and is not intended to limit the present disclosure, which may be variously modified and varied by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present disclosure should be included in the protection scope of the present disclosure. Although the embodiments disclosed in the present disclosure are described above, the embodiments are merely used for understanding the present disclosure, and are not intended to limit the present disclosure. It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the disclosure, and that the scope of the disclosure is to be limited only by the appended claims.
Claims (11)
1. A cell structure of a trench gate IGBT, comprising:
a first conductive type substrate;
a first conductive type drift layer over the substrate;
the first trench gate is positioned in the surface of the drift layer and at the center of the cellular structure, and the second trench gate penetrates through the first trench gate;
the second conductive type well region is positioned in the surface of the drift layer, positioned on two sides of the first trench gate and the second trench gate and contacted with the first trench gate and the second trench gate;
the first conductive type source region is positioned in the surface of the well region, positioned on two sides of the first trench gate and the second trench gate and contacted with the first trench gate and the second trench gate;
an emitter metal layer located over the drift layer;
the first trench gate is connected to the emitter metal layer through a first connecting hole, the source region is connected to the emitter metal layer through a second connecting hole, and the second trench gate is isolated from the emitter metal layer through an interlayer dielectric layer.
2. The cell structure of the trench gate IGBT of claim 1, wherein a depth of the first trench gate is less than a depth of the second trench gate.
3. The cell structure of the trench gate IGBT according to claim 1,
the width of the first trench gate is greater than that of the second trench gate;
the length of the first trench gate is smaller than that of the second trench gate.
4. The cell structure of the trench gate IGBT according to claim 1, wherein the well region is in contact with sides and a bottom of the first trench gate and sides of the second trench gate.
5. The cell structure of the trench gate IGBT according to claim 1, wherein the depth of the second trench gate is greater than the depth of the well region.
6. The cell structure of the trench-gate IGBT of claim 1, wherein the first trench-gate includes a first gate trench located within the drift layer surface, a first gate disposed within the first gate trench, and a first gate insulating layer disposed between the first gate trench and the first gate.
7. The cell structure of the trench-gate IGBT of claim 1, wherein the second trench-gate includes a second gate trench located within the drift layer surface, a second gate disposed within the second gate trench, and a second gate insulating layer disposed between the second gate trench and the second gate.
8. The cell structure of the trench gate IGBT according to claim 1, further comprising:
a second conductivity type collector region located under the substrate;
a collector metal layer located below and electrically connected to the collector region.
9. A preparation method of the cell structure of the trench gate IGBT according to any one of claims 1 to 8, characterized by comprising the following steps:
providing a first conductive type substrate;
forming a first conductive type drift layer over the substrate;
forming a first trench gate in the surface of the drift layer at the center of the cellular structure;
forming a second trench gate penetrating through the first trench gate at the central position of the cellular structure in the surface of the drift layer;
injecting second conductive type high-energy ions above the drift layer to form a second conductive type well region which is contacted with the first trench gate and the second trench gate on two sides of the first trench gate and the second trench gate in the surface of the drift layer;
injecting first conductive type high-energy ions into the well region so as to form a first conductive type source region which is contacted with the first trench gate and the second trench gate on two sides of the first trench gate and the second trench gate in the surface of the well region;
forming an interlayer dielectric layer which covers the first trench gate, the second trench gate and the source region simultaneously above the drift layer;
etching the interlayer dielectric layer through a mask to form a first connecting hole penetrating through the interlayer dielectric layer and extending to the first grid electrode of the first trench grid and a second connecting hole penetrating through the interlayer dielectric layer and extending to the source region;
and forming an emitter metal layer above the drift layer, and enabling the emitter metal layer to be connected with the first trench gate through the first connecting hole and the source region through the second connecting hole.
10. The method according to claim 9, wherein after the step of forming the emitter metal layer over the drift layer, the method further comprises the steps of:
implanting second conductivity type high energy ions under the substrate to form a second conductivity type collector region under the substrate;
a collector metal layer electrically connected to the collector region is formed under the collector region.
11. A trench-gate IGBT characterized by a cell structure comprising several trench-gate IGBTs according to any of claims 1 to 8.
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| JP4817827B2 (en) * | 2005-12-09 | 2011-11-16 | 株式会社東芝 | Semiconductor device |
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| CN107004714A (en) * | 2014-11-18 | 2017-08-01 | 罗姆股份有限公司 | The manufacture method of semiconductor device and semiconductor device |
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