CN112002751A - Cellular structure of silicon carbide VDMOSFET device, preparation method of cellular structure and silicon carbide VDMOSFET device - Google Patents

Cellular structure of silicon carbide VDMOSFET device, preparation method of cellular structure and silicon carbide VDMOSFET device Download PDF

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CN112002751A
CN112002751A CN202010712289.5A CN202010712289A CN112002751A CN 112002751 A CN112002751 A CN 112002751A CN 202010712289 A CN202010712289 A CN 202010712289A CN 112002751 A CN112002751 A CN 112002751A
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gate
source region
source
ohmic contact
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戴小平
高秀秀
谢思亮
汤晓燕
齐放
李诚瞻
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Hunan Guoxin Semiconductor Technology Co ltd
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Hunan Guoxin Semiconductor Technology Co ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45—Ohmic electrodes
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41741—Source or drain electrodes for field effect devices for vertical or pseudo-vertical devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41766—Source or drain electrodes for field effect devices with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
    • H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/1608—Silicon carbide

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Abstract

The present disclosure provides a cell structure of a silicon carbide VDMOSFET device, a method of manufacturing the same, and a silicon carbide VDMOSFET device, wherein the cell structure includes a second conductive type well region located in a surface of the drift layer and disposed at both sides of the cell structure; a first conductive type source region located in the surface of the well region; the drift layer is provided with a lateral groove on the surface downwards on one side of the source region far away from the center of the cellular structure; the second conductive type ohmic contact region is arranged in the well region, is positioned at the bottom and the side wall of the side groove and is adjacent to the source region; a source metal layer disposed over the source region and within the side trench; wherein the source metal layer forms ohmic contact with the source region and the ohmic contact region simultaneously. According to the method, the groove-shaped ohmic contact region adjacent to the source region is formed in the well region in a mode of forming the groove first and then injecting the inclined ions, so that the UIS tolerance of the device is improved, and the device has higher dynamic avalanche reliability.

Description

Cellular structure of silicon carbide VDMOSFET device, preparation method of cellular structure and silicon carbide VDMOSFET device
Technical Field
The disclosure relates to the technical field of semiconductor devices, in particular to a cell structure of a silicon carbide VDMOSFET device, a preparation method of the cell structure and the silicon carbide VDMOSFET device.
Background
Silicon carbide (SiC) is a novel wide bandgap semiconductor material with excellent physical, chemical and electrical properties. The breakdown electric field intensity of the silicon carbide is 10 times that of the traditional silicon, the heat conductivity is 3 times that of the silicon, the silicon carbide has higher switching frequency, and the loss and the volume of an energy storage element in a circuit can be reduced. The silicon carbide Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) has the characteristics of low on resistance, high switching speed, high temperature resistance and the like, and has great application advantages in the fields of high-voltage frequency conversion, new energy automobiles, rail transit and the like. MOSFETs are further classified into Vertical Double-diffused MOSFETs (VDMOSFETs) and Lateral Double-diffused MOSFETs (LDMOSFETs). Among them, the silicon carbide VDMOSFET is an ideal power device for both switching and linear applications, and is often used in high-frequency high-power fast switching circuits.
In the use process of the silicon carbide VDMOSFET device, due to the unavoidable stray inductance in the circuit and the system, once the energy released by the induced electromotive force generated by the transient current on the stray inductance exceeds the limit borne by the VDMOSFET device, the device is forced to enter a reverse avalanche working mode (i.e., the parasitic transistor is turned on) and simultaneously releases the energy, and finally the device fails, namely the VDMOSFET device fails to have a non-clamped Inductive Switching (UIS), so that the whole circuit and even the system are broken down.
Disclosure of Invention
In order to solve the problems, the disclosure provides a cell structure of a silicon carbide VDMOSFET device, a preparation method of the cell structure and the silicon carbide VDMOSFET device, and solves the technical problem that dynamic avalanche reliability of the device is poor due to the fact that the silicon carbide VDMOSFET is prone to UIS failure in the prior art.
In a first aspect, the present disclosure provides a cell structure of a silicon carbide VDMOSFET device, comprising:
a first conductivity type silicon carbide substrate;
a first conductive type drift layer over the substrate;
the second conduction type well regions are positioned in the surface of the drift layer and arranged on two sides of the cellular structure; wherein, on both sides of the cellular structure, the surface of the drift layer is completely covered by the well region;
a first conductive type source region located in the surface of the well region; the drift layer is provided with a lateral groove on the surface downwards on one side of the source region far away from the center of the cellular structure;
the second conductive type ohmic contact region is arranged in the well region, is positioned at the bottom and the side wall of the side groove and is adjacent to the source region; wherein the side trench is isolated from the source region by the ohmic contact region, the bottom of the ohmic contact region being located below the bottom of the source region;
the grid structure is positioned in the center of the cellular structure and is in contact with the well region and the source region;
a source metal layer disposed over the source region and within the side trench; wherein the source metal layer forms ohmic contact with the source region and the ohmic contact region simultaneously.
According to an embodiment of the present disclosure, preferably,
one side of the surface of the well region, which is close to the center of the cellular structure, is not completely covered by the source region;
the gate structure includes a gate insulating layer over the drift layer and simultaneously in contact with the source region, the well region, and the surface of the drift layer, and a gate over the gate insulating layer.
According to an embodiment of the present disclosure, preferably,
one side of the surface of the well region, which is close to the center of the cellular structure, is completely covered by the source region;
the gate structure comprises a gate groove arranged in the drift layer and adjacent to the well region, a gate insulating layer arranged on the side wall and the bottom of the gate groove and a gate filled in the gate groove.
According to the embodiment of the present disclosure, preferably, the method further includes:
the interlayer dielectric layer is positioned above the gate structure; the gate structure is isolated from the source metal layer through the interlayer dielectric layer;
a drain metal layer located below and in ohmic contact with the substrate.
In a second aspect, the present disclosure provides a method for preparing a cell structure of a silicon carbide VDMOSFET device, including:
providing a first conductivity type silicon carbide substrate;
forming a first conductive type drift layer over the substrate;
forming second conductive type well regions on two sides of the cellular structure in the surface of the drift layer; wherein, on both sides of the cellular structure, the surface of the drift layer is completely covered by the well region;
forming a first conduction type source region in the surface of the well region;
forming a side groove on the surface of the drift layer on one side of the source region far away from the center of the cellular structure;
forming a second conductive type ohmic contact region adjacent to the source region on the bottom and the side wall of the side groove in the well region in an inclined ion implantation mode; wherein the side trench is isolated from the source region by the ohmic contact region, the bottom of the ohmic contact region being located below the bottom of the source region;
forming a gate structure in contact with the well region and the source region in the center of the cellular structure;
and forming a source metal layer above the source region and in the side groove, and simultaneously forming ohmic contact with the source region and the ohmic contact region.
According to the embodiment of the present disclosure, preferably, a side of the surface of the well region near the center of the cellular structure is not completely covered by the source region; forming a gate structure in contact with the well region and the source region at the center of the cellular structure, comprising the steps of:
forming a gate insulating layer over the drift layer at the center of the cell structure while contacting the source region, the well region, and the surface of the drift layer;
forming a polysilicon gate over the gate insulation layer; wherein the gate insulating layer and the gate electrode constitute the gate structure.
According to the embodiment of the present disclosure, preferably, a side of the surface of the well region near the center of the cellular structure is completely covered by the source region; forming a gate structure in contact with the well region and the source region at the center of the cellular structure, comprising the steps of:
forming a gate trench adjacent to the well region in the drift layer at the center of the cellular structure;
forming a gate insulating layer on the side wall and the bottom of the gate trench;
filling polycrystalline silicon in the grid groove to form a grid; wherein the gate trench, the gate insulating layer and the gate constitute the gate structure.
According to the embodiment of the present disclosure, after the step of forming the gate structure in the center of the cell structure, the step of contacting the well region and the source region preferably further comprises the following steps:
forming an interlayer dielectric layer covering the gate structure above the gate structure; and the gate structure is isolated from the source metal layer through the interlayer dielectric layer.
According to the embodiment of the present disclosure, after the step of forming a source metal layer over the source region and in the side trench, and simultaneously forming an ohmic contact with the source region and the ohmic contact region, the method further includes the steps of:
and forming a drain metal layer in ohmic contact with the substrate below the substrate.
In a third aspect, the present disclosure provides a silicon carbide VDMOSFET device comprising a number of cell structures of the silicon carbide VDMOSFET device as described in any one of the first aspects.
By adopting the technical scheme, the following technical effects can be at least achieved:
the present disclosure provides a cell structure of a silicon carbide VDMOSFET device, a method of manufacturing the same, and a silicon carbide VDMOSFET device, the cell structure including a first conductivity type drift layer over the substrate; the second conduction type well regions are positioned in the surface of the drift layer and arranged on two sides of the cellular structure; wherein, on both sides of the cellular structure, the surface of the drift layer is completely covered by the well region; a first conductive type source region located in the surface of the well region; the drift layer is provided with a lateral groove on the surface downwards on one side of the source region far away from the center of the cellular structure; the second conductive type ohmic contact region is arranged in the well region, is positioned at the bottom and the side wall of the side groove and is adjacent to the source region; the grid structure is positioned in the center of the cellular structure and is in contact with the well region and the source region; a source metal layer disposed over the source region and within the side trench; wherein the source metal layer forms ohmic contact with the source region and the ohmic contact region simultaneously. According to the method, the groove-shaped second conductive type ohmic contact region adjacent to the source region is formed in the well region in a mode of firstly forming the groove and then injecting the inclined ions, so that the ohmic contact region can extend to the lower part of the source region to the maximum extent, the series resistance of the base region of the parasitic bipolar transistor of the device can be greatly reduced, the possibility of UIS failure of the device due to the fact that the parasitic transistor is started is reduced, the UIS tolerance of the device is improved, and the device has higher dynamic avalanche reliability.
Drawings
The accompanying drawings, which are included to provide a further understanding of the disclosure and are incorporated in and constitute a part of this specification, illustrate embodiments of the disclosure and together with the description serve to explain the disclosure without limiting the disclosure. In the drawings:
fig. 1 is a schematic cross-sectional structure diagram illustrating a cell structure of a planar gate silicon carbide VDMOSFET device according to an exemplary embodiment of the present disclosure;
FIG. 2 is a schematic cross-sectional structure diagram illustrating a cell structure of a trench-gated silicon carbide VDMOSFET device, in accordance with an exemplary embodiment of the present disclosure;
FIG. 3 is a schematic flow chart illustrating a method for fabricating a cell structure of a planar gate silicon carbide VDMOSFET device according to an exemplary embodiment of the present disclosure;
FIGS. 4-10 are schematic cross-sectional structure diagrams formed at steps associated with a method of fabricating a cell structure of a planar gate silicon carbide VDMOSFET device, according to an exemplary embodiment of the present disclosure;
fig. 11 is a cross-sectional schematic structure diagram of a planar gate silicon carbide VDMOSFET device, according to an exemplary embodiment of the present disclosure.
Detailed Description
Embodiments of the present disclosure will be described in detail with reference to the accompanying drawings and examples, so that how to apply technical means to solve technical problems and achieve the corresponding technical effects can be fully understood and implemented. The embodiments and the features of the embodiments of the present disclosure can be combined with each other without conflict, and the formed technical solutions are all within the protection scope of the present disclosure. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity. Like reference numerals refer to like elements throughout.
It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present disclosure.
It will be understood that spatial relationship terms, such as "above", "below", "beneath", and the like, may be used herein for ease of description to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, then elements or features described as "below" other elements would then be oriented "above" the other elements or features. Thus, the exemplary terms "under" and "under" can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.
Embodiments of the present disclosure are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the present disclosure. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments of the present disclosure should not be limited to the particular shapes of regions illustrated herein, but are to include deviations in shapes that result, for example, from manufacturing. For example, an implanted region shown as a rectangle will typically have rounded or curved features and/or implant concentration gradients at its edges rather than a binary change from implanted to non-implanted region. Also, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation is performed. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the present disclosure.
In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the present disclosure. The following detailed description of the preferred embodiments of the present disclosure, however, the present disclosure may have other embodiments in addition to these detailed descriptions.
Example one
As shown in fig. 1, the embodiment of the present disclosure provides a cell structure 100 of a planar gate silicon carbide VDMOSFET device, which includes a substrate 101, a drift layer 102, a well region 103, a source region 104, a side trench 105, an ohmic contact region 106, a gate insulating layer 107, a gate 108, an interlayer dielectric layer 109, a source metal layer 110, and a drain metal layer 111.
Illustratively, the substrate 101 is a silicon carbide substrate of a first conductivity type. The substrate 101 has a relatively thick thickness and a relatively high ion doping concentration.
The drift layer 102 is a drift layer of the first conductivity type and is disposed above the substrate 101, and has an ion doping concentration of about 1E15 to 8E15cm-3Specifically, the chip withstand voltage needs to be optimized. When the first conductivity type is N-type, the doped ions of the N-type drift layer 102 are nitrogen ions.
The well 103 is a well of the second conductivity type, located in the drift layer 102 and disposed on two sides of the cell structure 100. The upper surface of the well region 103 is flush with the surface of the drift layer 102, and on both sides of the cell structure 100, the surface of the drift layer 102 is completely covered by the well region 103, i.e., one end of the well region 103 away from the center of the cell structure 100 is flush with the drift layer 102.
The source region 104 is a source region of the first conductivity type and is located in the surface of the well region 103, and the upper surface of the source region 104 is flush with the upper surface of the well region 103. The ion doping concentration of the source region 104 is greater than the ion doping concentration of the substrate 101. The width of the source region 104 is smaller than the width of the well region 103, and there is a width difference between the well region 103 and the source region 104 on the side close to the center of the cell structure 100, that is, the side of the surface of the well region 103 close to the center of the cell structure 100 is not completely covered by the source region 104, so as to form a conduction channel of a planar gate. And on the side of the source region 104 away from the center of the cell structure 100, the drift layer 102 is provided with a side trench 105 on its surface downward.
The ohmic contact regions 106, which are heavily doped regions of the second conductivity type, are disposed in the well region 103 at the bottom and sidewalls of the side trenches 105 and adjacent to the source regions 104. The side trench 105 is isolated from the source region 104 by the ohmic contact region 106 (i.e., the side trench 105 is not in contact with the source region 104), the bottom of the ohmic contact region 106 is located below the bottom of the source region 104, i.e., the ohmic contact region 106 extends to the maximum extent below the source region 104, and the ohmic contact region 106 is in a trench shape, so that the series resistance of the base region of the parasitic bipolar transistor of the device can be greatly reduced, thereby reducing the possibility of UIS failure of the device due to the turn-on of the parasitic transistor, and improving the UIS resistance of the device. The ion doping concentration of the ohmic contact region 106 is greater than that of the well region 103.
A gate insulating layer 107 is located over the drift layer 102 while being in contact with the source region 104, the well region 103, and the surface of the drift layer 102 to isolate the gate 108 from the source region 104, the well region 103, and the drift layer 102.
The gate 108 is located above the gate insulating layer 107, and the gate 108 is a polysilicon gate.
The gate insulating layer 107 and the gate electrode 108 constitute a planar gate structure.
An interlayer dielectric layer 109 is disposed over the gate electrode 108 and covers the planar gate structure to isolate the gate structure (mainly the gate electrode 108) from the source metal layer 110.
And a source metal layer 110 located above the source region 104 and in the side trench 105 while forming ohmic contact with the source region 104 and the ohmic contact region 106. The source metal layer 110 may be a metal having low contact resistivity, such as titanium, nickel, gold, or the like.
And a drain metal layer 111 located under the substrate 101 and forming an ohmic contact with the substrate 101.
Correspondingly, the first conductivity type and the second conductivity type are opposite. For example, when the first conductivity type is N-type, the second conductivity type is P-type; when the first conductive type is P type, the second conductive type is N type.
In the cellular structure 100 of the silicon carbide VDMOSFET device provided in this embodiment, the trench-shaped ohmic contact region 106 of the second conductivity type adjacent to the source region 104 is formed in the well region 103, so that the ohmic contact region 106 can extend to the lower side of the source region 104 to the maximum extent, which can greatly reduce the series resistance of the base region of the parasitic bipolar transistor of the device, thereby reducing the possibility of UIS failure of the device due to the turn-on of the parasitic transistor, improving the UIS resistance of the device, and enabling the device to have higher dynamic avalanche reliability.
Example two
As shown in fig. 2, the embodiment of the present disclosure provides a cell structure 200 of a trench-gate silicon carbide VDMOSFET device, which includes a substrate 201, a drift layer 202, a well region 203, a source region 204, a side trench 205, an ohmic contact region 206, a gate trench (not labeled in the figure), a gate insulating layer 207, a gate 208, an interlayer dielectric layer 209, a source metal layer 210, and a drain metal layer 211.
Illustratively, the substrate 201 is a silicon carbide substrate of a first conductivity type. The substrate 201 has a relatively thick thickness and a relatively high ion doping concentration.
The drift layer 202 is a drift layer of the first conductivity type and is disposed over the substrate 201, and has an ion doping concentration of about 1E15 to 8E15cm-3Specifically, the chip withstand voltage needs to be optimized. When the first conductivity type is N-type, the doping ions of the N-type drift layer 202 are nitrogen ions.
The well region 203 is a well region of the second conductivity type, located in the drift layer 202 and disposed on two sides of the cell structure 200. The upper surface of the well region 203 is flush with the surface of the drift layer 202, and on both sides of the cell structure 200, the surface of the drift layer 202 is completely covered by the well region 203, i.e., one end of the well region 203 away from the center of the cell structure 200 is flush with the drift layer 202.
Source region 204 is a source region of the first conductivity type and is located in the surface of well region 203, and the upper surface of source region 204 is flush with the upper surface of well region 203. The ion doping concentration of the source region 204 is greater than the ion doping concentration of the substrate 201. The well region 203 and the source region 204 have no width difference on the side close to the center of the cell structure 200, that is, the surface of the well region 203 on the side close to the center of the cell structure 200 is completely covered by the source region 204 to form a conduction channel of a trench gate. And a side trench 205 is formed on the surface of the drift layer 202 downward on the side of the source region 204 away from the center of the cell structure 200.
Ohmic contact regions 206, which are heavily doped regions of the second conductivity type, are disposed in well region 203 at the bottom and sidewalls of side trenches 205 and adjacent to source regions 204. The side trench 205 is isolated from the source region 204 by the ohmic contact region 206 (i.e. the side trench 205 is not in contact with the source region 204), the bottom of the ohmic contact region 206 is located below the bottom of the source region 204, i.e. the ohmic contact region 206 extends to the maximum extent below the source region 204, and the ohmic contact region 206 is in a trench shape, so that the series resistance of the base region of the parasitic bipolar transistor of the device can be greatly reduced, thereby reducing the possibility of UIS failure of the device due to the turn-on of the parasitic transistor, and improving the UIS tolerance of the device. The ion doping concentration of the ohmic contact region 206 is greater than that of the well region 203.
A gate trench (not labeled) is disposed in the drift layer 202 and adjacent to the well region 203. The depth of the gate trench is greater than the depth of the well region 203.
A gate insulating layer 207 is disposed on the gate trench sidewalls and bottom to isolate the gate 208 from the source region 204, the well region 203, and the drift layer 202.
The gate 208 is filled in the gate trench, and the gate 208 is a polysilicon gate.
The gate trench, the gate insulating layer 207, and the gate electrode 208 constitute a trench gate structure.
An interlayer dielectric layer 209 is disposed over the gate 208 and covers the trench gate structure to isolate the gate structure (mainly the gate 208) from the source metal layer 210.
A source metal layer 210 located over source regions 204 and within side trenches 205 and forming ohmic contacts to both source regions 204 and ohmic contact regions 206. The source metal layer 210 may be a metal having low contact resistivity, such as titanium, nickel, gold, or the like.
And a drain metal layer 211 located under the substrate 201 and forming an ohmic contact with the substrate 201.
Correspondingly, the first conductivity type and the second conductivity type are opposite. For example, when the first conductivity type is N-type, the second conductivity type is P-type; when the first conductive type is P type, the second conductive type is N type.
In the cellular structure 200 of the silicon carbide VDMOSFET device provided in this embodiment, the trench-shaped ohmic contact region 206 of the second conductivity type is formed in the well region 203 and is adjacent to the source region 204, so that the ohmic contact region 206 can extend to the lower side of the source region 204 to the maximum extent, and thus the series resistance of the base region of the parasitic bipolar transistor of the device can be greatly reduced, the possibility of UIS failure of the device due to the turn-on of the parasitic transistor is reduced, the UIS resistance of the device is improved, and the device has higher dynamic avalanche reliability.
EXAMPLE III
On the basis of the first embodiment, the present embodiment provides a method for manufacturing a cell structure 100 of a planar gate silicon carbide VDMOSFET device. Fig. 3 is a schematic flow chart illustrating a method for fabricating a cell structure 100 of a silicon carbide VDMOSFET device according to an embodiment of the present disclosure. Fig. 4-10 are schematic cross-sectional structures formed at steps associated with a method of fabricating a cell structure 100 of a silicon carbide VDMOSFET device, according to an embodiment of the present disclosure. The detailed steps of an exemplary method for fabricating the cell structure 100 of the silicon carbide VDMOSFET device proposed by the embodiments of the present disclosure are described below with reference to fig. 3 and 4-10.
As shown in fig. 3, the method for manufacturing the cell structure 100 of the silicon carbide VDMOSFET device of the present embodiment includes the following steps:
step S101: as shown in fig. 4, a first conductivity type silicon carbide substrate 101 is provided.
The substrate 101 has a relatively thick thickness and a relatively high ion doping concentration.
Step S102: a first conductive type drift layer 102 is formed over a substrate 101.
Specifically, the drift layer 102 is formed by cvd epitaxy, the drift layer 102 is a uniformly doped silicon carbide layer with an ion doping concentration of about 1E15 to 8E15cm-3Specifically, the chip withstand voltage needs to be optimized. When the first conductivity type is N-type, the doped ions of the N-type drift layer 102 are nitrogen ions.
Step S103: as shown in fig. 5, second conductive type well regions 103 are formed in the surface of the drift layer 102 on both sides of the cell structure 100; wherein, on both sides of the cellular structure 100, the surface of the drift layer 102 is completely covered by the well 103.
Specifically, a photolithography process is adopted, a part of the drift layer 102 located in the center of the cell structure 100 is selectively shielded by photoresist, and then ion implantation is adopted to implant second conductivity type high-energy ions into the surface of the drift layer 102, so that well regions 103 are formed on two sides of the cell structure 100 in the surface of the drift layer 102, and the upper surfaces of the well regions 103 are flush with the surface of the drift layer 102. On both sides of the cell structure 100, the surface of the drift layer 102 is completely covered by the well 103, i.e., the end of the well 103 away from the center of the cell structure 100 is flush with the drift layer 102.
Step S104: a first conductive type source region 104 is formed in the surface of the well region 103.
Specifically, the drift layer 102 between the well regions 103 and the portion of the well region 103 near the center of the cell structure 100 are selectively shielded by photoresist using a photolithography process, and then the first conductivity type high-energy ions are implanted into the surface of the well region 103 by ion implantation to form a source region 104 in the surface of the well region 103. That is, the surface of the well region 103 near the center of the cellular structure 100 is not completely covered by the source region 104 to form a planar gate conduction channel.
Step S105: as shown in fig. 6, a side trench 105 is formed on the surface of the drift layer 102 at a side of the source region 104 away from the center of the cell structure 100.
Specifically, by using a mask etching method, a side trench 105 is etched on the surface of the drift layer 102 on the side of the source region 104 away from the center of the cell structure 100.
In the method of forming the source region 104 and then forming the side trench 105, since the width of the source region 104 may be as wide as possible before the side trench 105 is formed, and one end of the source region 104 away from the center of the cell structure 100 may be flush with one end of the well region 103 away from the center of the cell structure 100, which may not affect the formation of the subsequent ohmic contact region 106, when the first conductive type high energy ions are implanted (to form the source region 104) in step S104, the line width of the ion implantation is large, which may avoid the influence of the small line width of the ion implantation on the device design.
Step S106: as shown in fig. 7, by means of tilted ion implantation, a second conductive type ohmic contact region 106 is formed in the well region 103 at the bottom and the sidewall of the side trench 105, and is adjacent to the source region 104; wherein the side trenches 105 are isolated from the source region 104 by ohmic contact regions 106, the bottom of the ohmic contact regions 106 being located below the bottom of the source region 104.
Specifically, all regions except the side walls and the bottom of the side trench 105 are selectively shielded by photoresist through a photolithography process, and then the second conductivity type high-energy ions are implanted into the well region 103 at the side walls and the bottom of the side trench 105 through ion implantation, so as to form the ohmic contact region 106 adjacent to the source region 104 in the well region 103 at the bottom and the side walls of the side trench 105. Wherein the side trenches 105 are isolated from the source region 104 by ohmic contact regions 106, the step forms a structure in which the source region 104 is not in contact with the side trenches 105. The bottom of the ohmic contact region 106 is located below the bottom of the source region 104, that is, the ohmic contact region 106 extends to the lower part of the source region 104 to the maximum extent, and the ohmic contact region 106 is in a trench shape, so that the series resistance of the base region of the parasitic bipolar transistor of the device can be greatly reduced, the possibility of UIS failure of the device due to the turn-on of the parasitic transistor is reduced, and the UIS tolerance of the device is improved. The ion doping concentration of the ohmic contact region 106 is greater than that of the well region 103.
Step S107: as shown in fig. 8, a gate structure contacting the well region 103 and the source region 104 is formed at the center of the cell structure 100.
In this embodiment, step S107 includes the following steps:
s107 a: forming a gate insulating layer 107 over the drift layer 102 at the center of the cell structure 100 while being in contact with the source region 104, the well region 103, and the surface of the drift layer 102;
s107 b: forming a polysilicon gate 108 over the gate insulating layer 107; the gate insulating layer 107 and the gate electrode 108 constitute a gate structure (planar gate structure) therein.
In this embodiment, as shown in fig. 9, after step S107, the following steps are further included:
forming an interlayer dielectric layer 109 covering the gate structure above the gate structure; the gate structure is isolated from the source metal layer 110 by the interlayer dielectric layer 109.
Step S108: as shown in fig. 10, a source metal layer 110 simultaneously forming ohmic contacts with the source region 104 and the ohmic contact region 106 is formed over the source region 104 and the side trench 105.
Specifically, a source metal layer 110 is formed over the source region 104 by a metallization process, wherein the source metal layer 110 is isolated from the gate 108 by an interlayer dielectric layer 109. The source metal layer 110 may be a metal having low contact resistivity, such as titanium, nickel, gold, or the like.
Step S109: a drain metal layer 111 is formed under the substrate 101 in ohmic contact with the substrate 101.
Specifically, a drain metal layer 111 in ohmic contact with the substrate 101 is formed under the substrate 101 through a metallization process.
Correspondingly, the first conductivity type and the second conductivity type are opposite. For example, when the first conductivity type is N-type, the second conductivity type is P-type; when the first conductive type is P type, the second conductive type is N type.
The embodiment provides a method for preparing a cell structure 100 of a planar gate silicon carbide VDMOSFET device, wherein a groove-shaped ohmic contact region 106 of a second conductivity type adjacent to a source region 104 is formed in a well region 103 by means of forming a groove and then performing oblique ion implantation, so that the ohmic contact region 106 can extend to the lower part of the source region 104 to the maximum extent, and thus the series resistance of a parasitic bipolar transistor base region of the device can be greatly reduced, the possibility of UIS failure of the device due to the turn-on of the parasitic transistor is reduced, the UIS tolerance of the device is improved, and the device has higher dynamic avalanche reliability.
Example four
On the basis of the second embodiment, the present embodiment provides a method for preparing a cell structure 200 of a trench-gate silicon carbide VDMOSFET device, including the following steps:
step S201: a first conductivity type silicon carbide substrate 201 is provided.
The substrate 201 has a relatively thick thickness and a relatively high ion doping concentration.
Step S202: a first conductive type drift layer 202 is formed over the substrate 201.
Specifically, the drift layer 202 is formed by cvd epitaxy, the drift layer 202 is a uniformly doped silicon carbide layer with an ion doping concentration of about 1E15 to 8E15cm-3Specifically, the chip withstand voltage needs to be optimized. When the first conductivity type is N-type, the doping ions of the N-type drift layer 202 are nitrogen ions.
Step S203: forming second conductive type well regions 203 on both sides of the cell structure 200 in the surface of the drift layer 202; wherein, on both sides of the cellular structure 200, the surface of the drift layer 202 is completely covered by the well region 203.
Specifically, a photolithography process is adopted, a part of the drift layer 202 located in the center of the cellular structure 200 is selectively shielded by photoresist, and then ion implantation is adopted to implant second conductivity type high-energy ions into the surface of the drift layer 202, so that well regions 203 are formed on two sides of the cellular structure 200 in the surface of the drift layer 202, and the upper surfaces of the well regions 203 are flush with the surface of the drift layer 202. On both sides of the cell structure 200, the surface of the drift layer 202 is completely covered by the well region 203, i.e., one end of the well region 203 away from the center of the cell structure 200 is flush with the drift layer 202.
Step S204: a first conductive type source region 204 is formed in the surface of the well region 203.
Specifically, a photolithography process is adopted, the drift layer 202 between the well regions 203 is selectively shielded by photoresist, and then ion implantation is adopted to implant first conductivity type high-energy ions into the surface of the well region 203, so as to form a source region 204 in the surface of the well region 203. That is, one side of the surface of the well region 203 close to the center of the cellular structure 200 is completely covered by the source region 204 to form a conduction channel of the trench gate.
Step S205: a side trench 205 is formed in the surface of the drift layer 202 at a side of the source region 204 away from the center of the cell structure 200.
Specifically, by using a mask etching method, a side trench 205 is etched on the surface of the drift layer 202 at a side of the source region 204 away from the center of the cell structure 200.
In the method of forming the source region 204 first and then forming the side trench 205, since the width of the source region 204 may be as wide as possible before the side trench 205 is formed, and one end of the source region 204 away from the center of the cell structure 200 may be flush with one end of the well region 203 away from the center of the cell structure 200, which may not affect the formation of the subsequent ohmic contact region 206, in step S204, when the first conductive type high energy ions are implanted (to form the source region 204), the line width of the ion implantation is large, which may avoid the influence of the small line width of the ion implantation on the device design.
Step S206: forming second conductive type ohmic contact regions 206 adjacent to the source regions 204 in the well region 203 at the bottom and sidewalls of the side trenches 205 by means of tilted ion implantation; wherein the side trenches 205 are isolated from source region 204 by ohmic contact regions 206, the bottom of ohmic contact regions 206 being located below the bottom of source region 204.
Specifically, all regions except the side walls and the bottom of the side trench 205 are selectively shielded by photoresist through a photolithography process, and then ions of the second conductivity type are implanted into the well region 203 at the side walls and the bottom of the side trench 205 through ion implantation, so as to form ohmic contact regions 206 adjacent to the source region 204 in the well region 203 at the bottom and the side walls of the side trench 205. Wherein side trenches 205 are isolated from source regions 204 by ohmic contact regions 206, the structure formed at this step is such that source regions 204 do not contact side trenches 205. The bottom of the ohmic contact region 206 is located below the bottom of the source region 204, that is, the ohmic contact region 206 extends to the lower part of the source region 204 to the maximum extent, and the ohmic contact region 206 is in a trench shape, so that the series resistance of the base region of the parasitic bipolar transistor of the device can be greatly reduced, the possibility of UIS failure of the device due to the turn-on of the parasitic transistor is reduced, and the UIS tolerance of the device is improved. The ion doping concentration of the ohmic contact region 206 is greater than that of the well region 203.
Step S207: a gate structure is formed in the center of the cell structure 200 in contact with the well region 203 and the source region 204.
In this embodiment, step S207 includes the following steps:
s207 a: forming a gate trench in the center of the cell structure 200 in the drift layer 202, wherein the gate trench is adjacent to the well region 203 and the source region 204;
s207 b: forming a gate insulating layer 207 on sidewalls and a bottom of the gate trench;
s207 c: filling polysilicon in the gate trench to form a gate 208; wherein the gate trench, the gate insulating layer 207, and the gate electrode 208 constitute a gate structure (trench gate structure).
Wherein the depth of the gate trench is greater than the depth of the well region 203.
In this embodiment, after step S207, the following steps are further included:
forming an interlayer dielectric layer 209 covering the gate structure above the gate structure; wherein the gate structure is isolated from the source metal layer 210 by the interlayer dielectric layer 209.
Step S208: a source metal layer 210 that forms ohmic contacts to both source regions 204 and ohmic contact regions 206 is formed over source regions 204 and within side trenches 205.
Specifically, a source metal layer 210 is formed over the source region 204 by a metallization process, wherein the source metal layer 210 is isolated from the gate 208 by an interlayer dielectric layer 209. The source metal layer 210 may be a metal having low contact resistivity, such as titanium, nickel, gold, or the like.
Step S209: a drain metal layer 211 is formed under the substrate 201 in ohmic contact with the substrate 201.
Specifically, a drain metal layer 211 is formed under the substrate 201 in ohmic contact with the substrate 201 through a metallization process.
Correspondingly, the first conductivity type and the second conductivity type are opposite. For example, when the first conductivity type is N-type, the second conductivity type is P-type; when the first conductive type is P type, the second conductive type is N type.
The embodiment provides a preparation method of a cell structure 200 of a trench gate silicon carbide VDMOSFET device, wherein a trench-shaped second conductive type ohmic contact region 206 adjacent to a source region 204 is formed in a well region 203 in a mode of forming a trench and then performing inclined ion implantation, so that the ohmic contact region 206 can extend to the lower part of the source region 204 to the maximum extent, and thus the series resistance of a parasitic bipolar transistor base region of the device can be greatly reduced, the possibility of UIS failure of the device due to the turn-on of a parasitic transistor is reduced, the UIS tolerance of the device is improved, and the device has higher dynamic avalanche reliability.
EXAMPLE five
On the basis of the first embodiment, as shown in fig. 11, the present embodiment provides a planar gate silicon carbide VDMOSFET device, which includes a cell structure 100 provided in the first embodiment, and specifically includes a substrate 101, a drift layer 102, a well 103, a source region 104, a side trench 105, an ohmic contact region 106, a gate insulating layer 107, a gate 108, an interlayer dielectric layer 109, a source metal layer 110, and a drain metal layer 111.
The positional relationship of the above parts is the same as that in the first embodiment, and will not be described herein again.
In summary, the present disclosure provides a cell structure of a silicon carbide VDMOSFET device, a method for fabricating the same, and a silicon carbide VDMOSFET device, wherein the cell structure includes a first conductive type drift layer located above a substrate; the second conduction type well regions are positioned in the surface of the drift layer and arranged on two sides of the cellular structure; wherein, on both sides of the cellular structure, the surface of the drift layer is completely covered by the well region; a first conductive type source region located in the surface of the well region; the drift layer is provided with a lateral groove on the surface downwards on one side of the source region far away from the center of the cellular structure; the second conductive type ohmic contact region is arranged in the well region, is positioned at the bottom and the side wall of the side groove and is adjacent to the source region; the grid structure is positioned in the center of the cellular structure and is in contact with the well region and the source region; a source metal layer disposed over the source region and within the side trench; wherein the source metal layer forms ohmic contact with the source region and the ohmic contact region simultaneously. According to the method, the groove-shaped second conductive type ohmic contact region adjacent to the source region is formed in the well region in a mode of firstly forming the groove and then injecting the inclined ions, so that the ohmic contact region can extend to the lower part of the source region to the maximum extent, the series resistance of the base region of the parasitic bipolar transistor of the device can be greatly reduced, the possibility of UIS failure of the device due to the fact that the parasitic transistor is started is reduced, the UIS tolerance of the device is improved, and the device has higher dynamic avalanche reliability.
The above is merely a preferred embodiment of the present disclosure and is not intended to limit the present disclosure, which may be variously modified and varied by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present disclosure should be included in the protection scope of the present disclosure. Although the embodiments disclosed in the present disclosure are described above, the embodiments are merely used for understanding the present disclosure, and are not intended to limit the present disclosure. It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the disclosure, and that the scope of the disclosure is to be limited only by the appended claims.

Claims (10)

1. A cell structure for a silicon carbide VDMOSFET device, comprising:
a first conductivity type silicon carbide substrate;
a first conductive type drift layer over the substrate;
the second conduction type well regions are positioned in the surface of the drift layer and arranged on two sides of the cellular structure; wherein, on both sides of the cellular structure, the surface of the drift layer is completely covered by the well region;
a first conductive type source region located in the surface of the well region; the drift layer is provided with a lateral groove on the surface downwards on one side of the source region far away from the center of the cellular structure;
the second conductive type ohmic contact region is arranged in the well region, is positioned at the bottom and the side wall of the side groove and is adjacent to the source region; wherein the side trench is isolated from the source region by the ohmic contact region, the bottom of the ohmic contact region being located below the bottom of the source region;
the grid structure is positioned in the center of the cellular structure and is in contact with the well region and the source region;
a source metal layer disposed over the source region and within the side trench; wherein the source metal layer forms ohmic contact with the source region and the ohmic contact region simultaneously.
2. The cell structure of a silicon carbide VDMOSFET device according to claim 1, wherein:
one side of the surface of the well region, which is close to the center of the cellular structure, is not completely covered by the source region;
the gate structure includes a gate insulating layer over the drift layer and simultaneously in contact with the source region, the well region, and the surface of the drift layer, and a gate over the gate insulating layer.
3. The cell structure of a silicon carbide VDMOSFET device according to claim 1, wherein:
one side of the surface of the well region, which is close to the center of the cellular structure, is completely covered by the source region;
the gate structure comprises a gate groove arranged in the drift layer and adjacent to the well region, a gate insulating layer arranged on the side wall and the bottom of the gate groove and a gate filled in the gate groove.
4. The cell structure of a silicon carbide VDMOSFET device according to claim 1, further comprising:
the interlayer dielectric layer is positioned above the gate structure; the gate structure is isolated from the source metal layer through the interlayer dielectric layer;
a drain metal layer located below and in ohmic contact with the substrate.
5. A preparation method of a cellular structure of a silicon carbide VDMOSFET device is characterized by comprising the following steps:
providing a first conductivity type silicon carbide substrate;
forming a first conductive type drift layer over the substrate;
forming second conductive type well regions on two sides of the cellular structure in the surface of the drift layer; wherein, on both sides of the cellular structure, the surface of the drift layer is completely covered by the well region;
forming a first conduction type source region in the surface of the well region;
forming a side groove on the surface of the drift layer on one side of the source region far away from the center of the cellular structure;
forming a second conductive type ohmic contact region adjacent to the source region on the bottom and the side wall of the side groove in the well region in an inclined ion implantation mode; wherein the side trench is isolated from the source region by the ohmic contact region, the bottom of the ohmic contact region being located below the bottom of the source region;
forming a gate structure in contact with the well region and the source region in the center of the cellular structure;
and forming a source metal layer above the source region and in the side groove, and simultaneously forming ohmic contact with the source region and the ohmic contact region.
6. The method as claimed in claim 5, wherein the surface of the well region is not completely covered by the source region at a side close to the center of the cell structure; forming a gate structure in contact with the well region and the source region at the center of the cellular structure, comprising the steps of:
forming a gate insulating layer over the drift layer at the center of the cell structure while contacting the source region, the well region, and the surface of the drift layer;
forming a polysilicon gate over the gate insulation layer; wherein the gate insulating layer and the gate electrode constitute the gate structure.
7. The method as claimed in claim 5, wherein the surface of the well region is completely covered by the source region on a side close to the center of the cell structure; forming a gate structure in contact with the well region and the source region at the center of the cellular structure, comprising the steps of:
forming a gate trench in the center of the cellular structure and in the drift layer, wherein the gate trench is adjacent to the well region and the source region;
forming a gate insulating layer on the side wall and the bottom of the gate trench;
filling polycrystalline silicon in the grid groove to form a grid; wherein the gate trench, the gate insulating layer and the gate constitute the gate structure.
8. The method of claim 5, wherein after the step of forming a gate structure in the center of the cell structure in contact with the well region and the source region, the method further comprises the steps of:
forming an interlayer dielectric layer covering the gate structure above the gate structure; and the gate structure is isolated from the source metal layer through the interlayer dielectric layer.
9. The method of fabricating a cell structure for a silicon carbide VDMOSFET device according to claim 5, further comprising, after the step of forming a source metal layer over the source regions and within the side trenches that simultaneously forms ohmic contacts to the source regions and the ohmic contact regions, the steps of:
and forming a drain metal layer in ohmic contact with the substrate below the substrate.
10. A silicon carbide VDMOSFET device comprising a plurality of cell structures of the silicon carbide VDMOSFET device of any of claims 1 to 4.
CN202010712289.5A 2020-07-22 2020-07-22 Cellular structure of silicon carbide VDMOSFET device, preparation method of cellular structure and silicon carbide VDMOSFET device Pending CN112002751A (en)

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