CN118198115A - High-voltage low-power-consumption SOI LIGBT - Google Patents
High-voltage low-power-consumption SOI LIGBT Download PDFInfo
- Publication number
- CN118198115A CN118198115A CN202410622788.3A CN202410622788A CN118198115A CN 118198115 A CN118198115 A CN 118198115A CN 202410622788 A CN202410622788 A CN 202410622788A CN 118198115 A CN118198115 A CN 118198115A
- Authority
- CN
- China
- Prior art keywords
- region
- groove
- cathode
- drift region
- anode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 23
- 229920005591 polysilicon Polymers 0.000 claims abstract description 23
- 239000004020 conductor Substances 0.000 claims description 25
- 239000000463 material Substances 0.000 claims description 11
- 239000000758 substrate Substances 0.000 claims description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 4
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(iv) oxide Chemical compound O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 claims description 4
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 2
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 claims description 2
- HFGPZNIAWCZYJU-UHFFFAOYSA-N lead zirconate titanate Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ti+4].[Zr+4].[Pb+2] HFGPZNIAWCZYJU-UHFFFAOYSA-N 0.000 claims description 2
- 229910052451 lead zirconate titanate Inorganic materials 0.000 claims description 2
- 235000012239 silicon dioxide Nutrition 0.000 claims description 2
- 239000000377 silicon dioxide Substances 0.000 claims description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 2
- VEALVRVVWBQVSL-UHFFFAOYSA-N strontium titanate Chemical compound [Sr+2].[O-][Ti]([O-])=O VEALVRVVWBQVSL-UHFFFAOYSA-N 0.000 claims description 2
- OGIDPMRJRNCKJF-UHFFFAOYSA-N titanium oxide Inorganic materials [Ti]=O OGIDPMRJRNCKJF-UHFFFAOYSA-N 0.000 claims description 2
- 230000005684 electric field Effects 0.000 abstract description 22
- 238000009826 distribution Methods 0.000 abstract description 21
- 238000000034 method Methods 0.000 abstract description 7
- 230000000903 blocking effect Effects 0.000 abstract description 5
- 238000002347 injection Methods 0.000 abstract description 5
- 239000007924 injection Substances 0.000 abstract description 5
- 239000004065 semiconductor Substances 0.000 abstract description 5
- 239000012535 impurity Substances 0.000 abstract description 4
- 239000000969 carrier Substances 0.000 abstract description 3
- 238000010586 diagram Methods 0.000 description 8
- 230000015556 catabolic process Effects 0.000 description 5
- 238000013459 approach Methods 0.000 description 3
- 238000002360 preparation method Methods 0.000 description 3
- 230000007423 decrease Effects 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 238000004458 analytical method Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Landscapes
- Thin Film Transistor (AREA)
Abstract
The invention belongs to the technical field of power semiconductors, and discloses a high-voltage low-power-consumption SOI LIGBT, which is characterized in that a medium groove gradually reduced from a cathode to an anode is introduced into a drift region, a polysilicon groove is arranged in the medium groove close to a main grid structure and is used as an auxiliary groove grid, and the groove grid is in short circuit with the main grid. When in blocking, the width-widening medium groove enables the impurity distribution in the drift region to be increased from the cathode to the anode, so that a uniform surface electric field is obtained, and the withstand voltage of the device is greatly improved; during forward conduction, the dielectric groove forms a narrow table surface near the cathode end of the drift region, so that injection enhancement and low conduction voltage drop are realized; in the switching-off process, under the same voltage withstand level, the excessive carriers in the drift region are small, and the fast switching-off and the low switching-off loss are realized. The invention can realize high withstand voltage and has lower turn-off loss under the condition of not increasing turn-on voltage drop.
Description
Technical Field
The invention belongs to the technical field of power semiconductors, and particularly relates to a high-voltage low-power-consumption SOI LIGBT.
Background
The power semiconductor device is used as a core device in chips such as a power supply, a driving device and a control device, wherein a transverse insulated gate bipolar transistor (Lateral Insulated Gate Bipolar Transistor, LIGBT) has the advantages of low on-state voltage, high on-state current, high input impedance of a MOS unipolar device, low driving power and the like of the BJT bipolar device. In addition, compared with a longitudinal IGBT, the LIGBT is easier to integrate on a silicon substrate and an SOI substrate, and the LIGBT on the SOI substrate can realize complete electrical isolation of devices and has the advantages of small leakage current, good insulating property and the like, so that the LIGBT is widely applied to high-voltage integrated circuits. In the research of LIGBT, the voltage-withstanding capability and the turn-off loss are performance parameters which are widely focused by researchers; by using the withstand voltage increasing technique, the device drift region can be further shortened under the same withstand voltage condition, and thus increasing the withstand voltage is one of effective means for reducing the turn-off loss. YIng-CHIEH TSAI et al, in 2014, in paper "Design and Analysis of a Double RESURF 700V LIGBT with quasi-vertical DMOSFET in Junction Isolation Technology" published by the 26 th IEEE International Power semiconductor device and Integrated Circuit conference (ISPSD) disclose: a P-type buried layer is introduced into an N-type drift region of the LIGBT, the buried layer is connected with a cathode P-well region, and the N-type drift region is assisted to be depleted, so that a longitudinal electric field of the device is higher than a transverse electric field, and high withstand voltage and low turn-off loss are obtained; however, the introduction of the P-type buried layer increases the process complexity and the preparation cost.
Disclosure of Invention
In order to solve the technical problems, the invention provides the high-voltage low-power-consumption SOI LIGBT which can optimize the electric field distribution of the device and improve the withstand voltage of the device on the premise of not increasing the complexity of the preparation process of the device.
The invention relates to a high-voltage low-power-consumption SOI LIGBT, which comprises a P substrate, an insulating medium buried layer and an N-type drift region which are sequentially stacked from bottom to top along the vertical direction of a device, wherein a cathode structure, a main grid structure, a drift region structure and an anode structure are sequentially arranged from left to right along the transverse direction of the device;
the cathode structure comprises a P well region, a P+ body contact region, an N+ cathode region and a cathode conductive material; the P well region is positioned at the upper part of the N-type drift region, the P+ body contact region and the N+ cathode region are in contact with each other and are arranged at one end of the upper surface of the P well region far away from the N-type drift region in parallel, the N+ cathode region is positioned at one side close to the N-type drift region, and the P+ body contact region is positioned at one side far away from the N-type drift region; the upper surfaces of the P+ body contact region and the N+ cathode region jointly lead out cathode conductive materials to be used as cathodes;
The anode structure comprises an N-type buffer layer, a P+ anode region and an anode conductive material; the P+ anode region is positioned on the inner upper surface of the N-type buffer layer; the leading-out end of the anode conductive material on the upper surface of the P+ anode region is an anode;
The main grid structure comprises a grid dielectric layer, a polysilicon material positioned above the grid dielectric layer and a main grid conductive material;
The drift region structure sequentially comprises an N-type drift region, a polysilicon groove, a first insulating medium groove and a second insulating medium groove, wherein the polysilicon groove is positioned in the N-type drift region, the first insulating medium groove is positioned at one side close to the main grid structure, the polysilicon groove is arranged at the inner side of the first insulating medium groove along the longitudinal direction of the first insulating medium groove, and a common leading-out end of the polysilicon groove and the main grid conductive material is a grid; the second insulating medium groove extends from the grid electrode to the anode structure direction and is connected with the first insulating medium groove integrally.
Further, the length of the second insulating medium groove along the longitudinal direction of the device gradually decreases from the cathode to the anode.
Further, the second insulating medium groove is in a ladder shape, a trapezoid shape or a triangle shape.
Further, when in blocking, a new electric field peak value is introduced into the step-shaped second insulating medium groove at the step, so that the impurity distribution in the drift region is increased from the cathode to the anode; when the number of steps of the second insulating medium slot approaches infinity, the shape of the second insulating medium slot is similar to a trapezoid or a triangle.
Further, the materials of the first insulating medium groove and the second insulating medium groove are one or more of silicon dioxide, silicon nitride, hafnium dioxide, titanium oxide, strontium titanate or lead zirconate titanate.
Further, the main gate structure is a planar gate, the planar gate is formed by a gate dielectric layer, a polysilicon material on the gate dielectric layer and a main gate conductive material, the gate dielectric layer is positioned on the upper surface of the P well region, and two ends of the gate dielectric layer are respectively overlapped with the N-type drift region and the N+ cathode region.
Further, the main gate structure is a trench gate, the trench gate is composed of a main gate conductive material, a gate dielectric layer and a polysilicon material filled in the groove, the side wall of one side of the trench gate far away from the drift region is sequentially contacted with the N+ cathode region and the P well region from top to bottom, and the depth of the trench gate exceeds the depth of the P well region.
The beneficial effects of the invention are as follows: according to the invention, a medium groove gradually reduced from a cathode to an anode is introduced into a drift region to improve the withstand voltage of the device, a polysilicon groove is arranged in the medium groove close to a main grid structure as an auxiliary groove grid, and the groove grid is in short circuit with the main grid. The designed insulating medium groove is in a ladder shape or a trapezoid shape or a triangle shape, wherein the ladder-shaped insulating medium groove can introduce a new electric field peak value at a ladder position so as to optimize surface electric field distribution, and when the number of the ladder is increased, the voltage resistance of the device is increased; meanwhile, when the number of steps of the insulating medium groove approaches infinity, the shape of the insulating medium groove is similar to a trapezoid or a triangle; therefore, the linear distribution of the charge density of the drift region can be further realized by changing the shape of the insulating medium groove, so that the surface electric field distribution is optimized, the optimal distribution is achieved, the breakdown voltage of the device is improved, and the higher withstand voltage can be realized only by using smaller drift region length. When in blocking, the width-widening medium groove enables the impurity distribution in the drift region to be increased from the cathode to the anode, so that a uniform surface electric field is obtained, and the withstand voltage of the device is greatly improved; during forward conduction, the dielectric groove forms a narrow table surface near the cathode end of the drift region, so that injection enhancement and low conduction voltage drop are realized; in the switching-off process, under the same voltage withstand level, the excessive carriers in the drift region are small, and the fast switching-off and the low switching-off loss are realized. Compared with the conventional device, the invention not only can reduce the cost of device preparation, but also can realize high withstand voltage, and has lower turn-off loss under the condition of not increasing the turn-on voltage drop.
Drawings
FIG. 1 is a schematic structural diagram of embodiment 1 of the present invention;
FIG. 2 is a cross-sectional view along AA' of example 1 of the present invention;
FIG. 3 is a front sectional view of embodiment 2 of the present invention;
FIG. 4 is a schematic structural diagram of embodiment 3 of the present invention;
FIG. 5 is a cross-sectional view taken along line AA' of embodiment 3 of the present invention;
FIG. 6 is a cross-sectional view taken along BB' of embodiment 3 of the present invention;
FIG. 7 is a graph showing the comparison of electric field distribution in the blocking state of the SOI LIGBT according to embodiment 3 of the present invention;
FIG. 8 is a graph showing the comparison of the forward conduction characteristics of SOI LIGBT of embodiment 3 and a dielectric tank according to the present invention;
Wherein: the semiconductor device comprises a 1-P substrate, a 2-insulating medium buried layer, a 3-N type drift region, a 4-P well region, a 5-P+ body contact region, a 61-cathode conductive material, a 62-main gate conductive material, a 63-anode conductive material, a 7-N+ cathode region, an 8-gate dielectric layer, a 9-polysilicon material, a 10-polysilicon groove, a 11-first insulating medium groove, a 12-second insulating medium groove, a 13-N type buffer layer and a 14-P+ anode region.
Detailed Description
In order that the invention may be more readily understood, a more particular description of the invention will be rendered by reference to specific embodiments that are illustrated in the appended drawings.
Example 1
As shown in fig. 1 and fig. 2, the high-voltage low-power-consumption SOI LIGBT according to the present invention comprises a P substrate 1, an insulating medium buried layer 2 and an N drift region 3 sequentially stacked from bottom to top along the vertical direction of the device; the device comprises a cathode structure, a main grid structure, a drift region structure and an anode structure in sequence from left to right along the transverse direction of the device.
The cathode structure comprises a P well region 4, a P+ body contact region 5, an N+ cathode region 7 and a cathode conductive material 61; the P-well region 4 is located at the upper part of the N-type drift region 3, the p+ body contact region 5 and the n+ cathode region 7 are in contact with each other, and are located at one end of the upper surface of the P-well region 4 far away from the N-type drift region 3, the n+ cathode region 7 is located at one side close to the N-type drift region 3, and the p+ body contact region 5 is located at one side far away from the N-type drift region 3; the upper surfaces of the P+ body contact region 5 and the N+ cathode region 7 jointly lead out cathode conductive material 61 as a cathode.
The main gate structure is a planar gate and comprises a gate dielectric layer 8, a polysilicon material 9 and a main gate conductive material 62 which are arranged on the gate dielectric layer 8, the gate dielectric layer 8 is positioned on the upper surface of the P well region 4, and two ends of the gate dielectric layer 8 are respectively overlapped with the N-type drift region 3 and the N+ cathode region 7.
The drift region structure part comprises an N-type drift region 3, a polysilicon groove 10, a first insulating medium groove 11 and a second insulating medium groove 12 which are positioned in the N-type drift region 3, wherein the polysilicon groove 10 is arranged at the inner side of the first insulating medium groove close to one side of the main grid structure, and the common leading-out end of the polysilicon groove 10 and the main grid conductive material 62 is a grid; the second insulating medium groove is connected with the first insulating medium groove into a whole and is positioned at one side close to the anode.
The width of the second insulating medium groove 12 gradually decreases from the cathode to the anode, and the shape of the second insulating medium groove 12 is a step shape.
The anode structure comprises an N-type buffer layer 13, a P+ anode region 14 and an anode conductive material 63; the P+ anode region 14 is positioned on the inner upper surface of the N-type buffer layer 13; the anode conductive material 63 on the upper surface of the p+ anode region 14 has an anode terminal.
When the high-voltage low-power-consumption SOI LIGBT is blocked, a new electric field peak value is introduced into the stepped dielectric groove at the step position, so that the impurity distribution in the drift region is increased from the cathode to the anode, the surface electric field of the device is optimized, the withstand voltage of the device is improved, and when the number of steps is more, the surface electric field of the device is more uniform.
During forward conduction, the polysilicon groove and the groove gate of the first insulating medium groove enable the near cathode end of the drift region to form a narrow table top, injection enhancement is achieved, conductivity modulation capability of the device is enhanced, and forward conduction voltage drop is reduced.
In the turn-off process, the gate control dielectric tank voltage is reduced along with the reduction of the gate voltage, the injection is weakened and enhanced, and at the moment, the excessive carriers in the drift region are reduced, so that the device is fast in turn-off speed and low in turn-off loss are realized.
Example 2
As shown in fig. 3, compared with embodiment 1, the main gate structure in this embodiment is a trench gate, the trench gate is composed of a main gate conductive material 62, a gate dielectric layer 8 and a polysilicon material 9 filled in the trench, the sidewall of one side of the trench gate far away from the drift region is sequentially contacted with the n+ cathode region 7 and the P well region 4 from top to bottom, and the depth of the trench gate exceeds the depth of the P well region 4.
Compared with the embodiment 1, the trench gate can block the extraction of holes, increase the hole concentration of the drift region, further enhance the conductivity modulation capability and reduce the forward conduction voltage drop; and the main gate structure fabrication process is compatible with the polysilicon trench 10 fabrication process.
Example 3
As shown in fig. 4, 5 and 6, the second insulating medium tank 12 is trapezoidal in shape in this example, compared with the embodiment 1. Compared with embodiment 1, this embodiment has the advantage that the more steps the device has, the more uniform the device surface electric field is at the time of device blocking, and therefore the shape of the second insulating medium slot is analogous to a trapezoid or triangle when the number of steps of the second insulating medium slot approaches infinity. Therefore, the linear distribution of the charge density of the drift region can be further realized by changing the shape of the second insulating medium groove, so that the surface electric field distribution is optimized, the optimal distribution is achieved, and the breakdown voltage of the device is improved, as shown in fig. 7. Fig. 7 (a) is a schematic diagram of three-dimensional electric field distribution of the high-voltage low-power-consumption SOI LIGBT, (b) is a top view of the high-voltage low-power-consumption SOI LIGBT, (c) is a schematic diagram of electric field distribution of the high-voltage low-power-consumption SOI LIGBT along the AA' direction, (d) is a surface electric field distribution diagram of the high-voltage low-power-consumption SOI LIGBT and a conventional SOI LIGBT, an abscissa is a coordinate value of an x direction (an x origin is located at an upper left corner of the N-type drift region 3, a direction is along a lateral direction of the device), and an ordinate is an electric field strength. As can be seen from the figure, the electric field distribution of the conventional SOI LIGBT device is concentrated at two ends of the drift region, the electric field in the middle of the drift region is too low to bear more applied voltage, and the electric field distribution of the high-voltage low-power-consumption SOI LIGBT device is more uniform, so that the device has higher withstand voltage. The breakdown voltage of the high-voltage low-power-consumption SOI LIGBT is 470V, the breakdown voltage of the conventional SOI LIGBT is 250V, and the breakdown voltage of the high-voltage low-power-consumption SOI LIGBT is improved by 88% compared with that of the conventional SOI LIGBT. The forward conduction characteristics are shown in fig. 8; in fig. 8, (a) is a hole density distribution diagram of the high-voltage low-power-consumption SOI LIGBT, (b) is a hole density distribution diagram of the dielectric trench SOI LIGBT, (c) is a hole density distribution diagram of the high-voltage low-power-consumption SOI LIGBT and the dielectric trench SOI LIGBT, the abscissa is a coordinate value in the x direction (x origin is located at the upper left corner of the N-type drift region 3, the direction is along the lateral direction of the device), and the ordinate is a hole density. The hole density of the high-voltage low-power-consumption SOI LIGBT is higher than that of the dielectric tank SOI LIGBT in forward conduction, and particularly the hole density of the high-voltage low-power-consumption SOI LIGBT close to the main grid side is far higher than that of the dielectric tank SOI LIGBT. Therefore, the injection enhancement low-power-consumption power device has the advantages that the conductivity modulation effect is enhanced, and the forward conduction voltage drop is reduced.
The foregoing is merely a preferred embodiment of the present invention, and is not intended to limit the present invention, and all equivalent variations using the description and drawings of the present invention are within the scope of the present invention.
Claims (6)
1. A high-voltage low-power-consumption SOI LIGBT comprises a P substrate, an insulating medium buried layer and an N-type drift region which are sequentially stacked from bottom to top along the vertical direction of a device, wherein a cathode structure, a main grid structure, a drift region structure and an anode structure are sequentially arranged from left to right along the transverse direction of the device;
the cathode structure comprises a P well region, a P+ body contact region, an N+ cathode region and a cathode conductive material; the P well region is positioned at the upper part of the N-type drift region, the P+ body contact region and the N+ cathode region are in contact with each other and are arranged at one end of the upper surface of the P well region far away from the N-type drift region in parallel, the N+ cathode region is positioned at one side close to the N-type drift region, and the P+ body contact region is positioned at one side far away from the N-type drift region; the upper surfaces of the P+ body contact region and the N+ cathode region jointly lead out cathode conductive materials to be used as cathodes;
The anode structure comprises an N-type buffer layer, a P+ anode region and an anode conductive material; the P+ anode region is positioned on the inner upper surface of the N-type buffer layer; the leading-out end of the anode conductive material on the upper surface of the P+ anode region is an anode;
The main grid structure comprises a grid dielectric layer, a polysilicon material positioned above the grid dielectric layer and a main grid conductive material;
the drift region structure comprises an N-type drift region, a polysilicon groove, a first insulating medium groove and a second insulating medium groove, wherein the polysilicon groove is positioned in the N-type drift region; the second insulating medium groove extends from the grid electrode to the anode direction and is connected with the first insulating medium groove into a whole.
2. The high voltage low power SOI LIGBT as claimed in claim 1 wherein said second dielectric slot tapers in length in the longitudinal direction of the device from the cathode to the anode.
3. The high voltage low power SOI LIGBT as claimed in claim 2 wherein said second dielectric trench is stepped or trapezoidal or triangular in shape.
4. The high voltage low power SOI LIGBT as claimed in claim 1 wherein the material of said first dielectric trench and second dielectric trench is one or more of silicon dioxide, silicon nitride, hafnium dioxide, titanium oxide, strontium titanate or lead zirconate titanate.
5. The high voltage low power SOI LIGBT of claim 1, wherein said main gate structure is a planar gate, said planar gate is comprised of a gate dielectric layer and polysilicon material and a main gate conductive material thereon, said gate dielectric layer is located on an upper surface of the P-well region and both ends thereof overlap with the N-type drift region and the n+ cathode region, respectively.
6. The high-voltage low-power-consumption SOI LIGBT according to claim 1, wherein the main grid structure is a groove grid, the groove grid is composed of a main grid conductive material, a grid dielectric layer and a polysilicon material filled in the groove, the side wall of one side of the groove grid far away from the drift region is sequentially contacted with an N+ cathode region and a P well region from top to bottom, and the depth of the groove grid exceeds the depth of the P well region.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202410622788.3A CN118198115A (en) | 2024-05-20 | 2024-05-20 | High-voltage low-power-consumption SOI LIGBT |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202410622788.3A CN118198115A (en) | 2024-05-20 | 2024-05-20 | High-voltage low-power-consumption SOI LIGBT |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN118198115A true CN118198115A (en) | 2024-06-14 |
Family
ID=91400336
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202410622788.3A Pending CN118198115A (en) | 2024-05-20 | 2024-05-20 | High-voltage low-power-consumption SOI LIGBT |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN118198115A (en) |
-
2024
- 2024-05-20 CN CN202410622788.3A patent/CN118198115A/en active Pending
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN107623027B (en) | Trench gate charge storage type insulated gate bipolar transistor and manufacturing method thereof | |
| CN107731899B (en) | Trench gate charge storage type IGBT device with clamping structure and manufacturing method thereof | |
| CN110400840B (en) | RC-LIGBT device for inhibiting voltage folding phenomenon | |
| CN108122963B (en) | Potential control rapid transverse insulated gate bipolar transistor | |
| CN107731898B (en) | CSTBT device and manufacturing method thereof | |
| CN108682688B (en) | Composite gate IGBT chip with three-dimensional channel | |
| CN104701380B (en) | Dual-direction MOS-type device and manufacturing method thereof | |
| CN107482058B (en) | Thin SOI LIGBT device with carrier storage layer | |
| CN111816699A (en) | SOI LIGBT device with self-adaptability | |
| CN110504308B (en) | High-speed low-loss multi-groove-gate high-voltage power device | |
| WO2016101134A1 (en) | Bi-directional metal oxide semiconductor device and manufacturing method thereof | |
| CN110504313B (en) | Transverse groove type insulated gate bipolar transistor and preparation method thereof | |
| CN114823863B (en) | Low-power-consumption transverse power device with anode groove | |
| CN114784102B (en) | LIGBT with mixed conduction mode | |
| CN108447904B (en) | Manufacturing method of transverse IGBT | |
| CN108258041B (en) | Three-grid thin SOI LIGBT with carrier storage layer | |
| CN113707716B (en) | Self-adaptive SOI LIGBT device with multiple floating field plates | |
| CN111834450B (en) | SOI LIGBT device integrated with Zener diode | |
| CN214588866U (en) | Low-capacitance IGBT device | |
| CN118198115A (en) | High-voltage low-power-consumption SOI LIGBT | |
| CN110504315B (en) | Groove-type insulated gate bipolar transistor and preparation method thereof | |
| CN113555424A (en) | Self-adaptive low-loss power device | |
| CN112002751A (en) | Cellular structure of silicon carbide VDMOSFET device, preparation method of cellular structure and silicon carbide VDMOSFET device | |
| CN108461536B (en) | Bidirectional trench gate charge storage type IGBT and manufacturing method thereof | |
| CN113078211B (en) | Integrated MOS self-adaptive control SOI LIGBT |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination |