CN108258041B - Three-grid thin SOI LIGBT with carrier storage layer - Google Patents
Three-grid thin SOI LIGBT with carrier storage layer Download PDFInfo
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- CN108258041B CN108258041B CN201810042181.2A CN201810042181A CN108258041B CN 108258041 B CN108258041 B CN 108258041B CN 201810042181 A CN201810042181 A CN 201810042181A CN 108258041 B CN108258041 B CN 108258041B
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- 239000004065 semiconductor Substances 0.000 claims abstract description 23
- 239000004020 conductor Substances 0.000 claims description 9
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 3
- 229910052760 oxygen Inorganic materials 0.000 claims description 3
- 239000001301 oxygen Substances 0.000 claims description 3
- 239000000758 substrate Substances 0.000 claims description 3
- 230000000903 blocking effect Effects 0.000 abstract description 4
- 230000000694 effects Effects 0.000 abstract description 4
- 230000000779 depleting effect Effects 0.000 abstract description 2
- 238000002347 injection Methods 0.000 abstract description 2
- 239000007924 injection Substances 0.000 abstract description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
- 229910052710 silicon Inorganic materials 0.000 description 6
- 239000010703 silicon Substances 0.000 description 6
- 238000010586 diagram Methods 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- OBNDGIHQAIXEAO-UHFFFAOYSA-N [O].[Si] Chemical compound [O].[Si] OBNDGIHQAIXEAO-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 230000015654 memory Effects 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 238000005215 recombination Methods 0.000 description 1
- 230000006798 recombination Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7394—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET on an insulating layer or substrate, e.g. thin film device or device isolated from the bulk substrate
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
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Abstract
The invention belongs to the technical field of power semiconductors, and particularly relates to a thin SOI LIGBT with a carrier storage layer and a tri-gate. The invention is mainly characterized in that: and a triple-gate structure is adopted to increase the channel density, the bottom of the groove gate is not contacted with the buried oxide layer, and a carrier storage layer is introduced into the parts below the plane gate and the groove gate, which are close to the drift region. When the device is conducted in the forward direction, the side wall of the groove gate blocks a cavity passage, so that the injection enhancement effect is achieved, and the forward conduction voltage drop of the device is reduced; meanwhile, the N-type carrier storage layer plays a role in blocking holes, promotes electrons to be injected into a drift region, enhances the conductivity modulation effect and further reduces the forward conduction voltage drop. When the forward blocking is performed, the groove grid plays a role of depleting the carrier storage layer, so that the device can still maintain high withstand voltage under the condition of high concentration of the storage layer. The P buried layer is introduced into the cathode of the device, so that the short-circuit resistance of the device is improved. Compared with the traditional thin SOI LIGBT structure, the SOI LIGBT structure has lower forward conduction voltage drop and better short-circuit resistance.
Description
Technical Field
The invention belongs to the technical field of power semiconductors, and relates to a three-Gate thin SOILIGBT (laterally Insulated Gate Bipolar Transistor) with a carrier storage layer.
Background
LIGBT is a structure formed by mixing a lateral field effect transistor and a bipolar transistor, has the advantages of high input impedance of a MOSFET and simple driving, and has the advantages of high current density and low conduction voltage drop of a BJT device, and has become one of core electronic components in modern power electronic circuit application. The SOI LIGBT has the advantages of good insulating property, small parasitic capacitance, small leakage current, high integration level and the like, is widely applied to high-voltage integrated circuits, and has wide application prospect in the fields of memories, microwave communication, intelligent electronics, high-voltage circuits, anti-foglight and the like.
Researchers' work on optimizing SOI LIGBT has focused primarily on thick top-layer silicon, with less interest in devices with thin top-layer silicon. Compared with thick top layer silicon, the thin top layer silicon has smaller process difficulty on device isolation and chip integration and lower cost. Meanwhile, the thin top layer silicon thickness is beneficial to reducing the turn-off loss of the device and can be compared with the turn-off time of a thick-film device adopting a short-circuit anode technology. However, due to the existence of silicon-oxygen surface recombination, the conductivity modulation efficiency in the drift region is reduced, so that the SOILIGBT of thin top layer silicon has the problems of small saturation current capability and large forward conduction voltage drop, and the short-circuit resistance of the device is poor.
Disclosure of Invention
The size and power consumption of the chip are mainly determined by the current capability and forward conduction voltage drop of the SOI LIGBT. In order to improve the current capability of the thin SOI IGBT, the invention provides a tri-gate thin SOI LIGBT with a carrier storage layer. The current capability of the device is improved by introducing the tri-gate and the carrier storage layer, the forward conduction voltage drop is reduced, and meanwhile, the short-circuit resistance of the device is improved by introducing the P buried layer.
The technical scheme of the invention is as follows:
a three-grid thin SOI LIGBT device with a current carrier storage layer comprises a substrate layer 1, a buried oxide layer 2 and a top semiconductor layer which are sequentially stacked from bottom to top along the vertical direction of the device; along the transverse direction of the device, the top semiconductor layer is sequentially provided with a cathode structure, a tri-gate structure, an N-type carrier storage layer 11, an N-type semiconductor drift region 4 and an anode structure from one side to the other side;
the cathode structure comprises a P-type well region 3 and a P-type heavily doped region 5 which penetrate through the top semiconductor layer along the vertical direction of the device, the P-type well region 3 and the P-type heavily doped region 5 are in mutual contact, and the P-type well region 3 is positioned on one side close to the N-type semiconductor drift region 4; an N-type heavily doped region 6 is arranged on the upper layer of the P-type well region 3; cathodes are led out from the upper surfaces of the P-type heavily doped region 5 and the N-type heavily doped region 6;
the device transverse direction and the device vertical direction are perpendicular to each other;
the triple-gate structure is positioned between the cathode structure and the N-type semiconductor drift region 4, and comprises groove gates and plane gates which are distributed discontinuously along the longitudinal direction of the device; the groove gate extends downwards from the surfaces of the P-type well region 3 and the N-type carrier storage layer 11 and is composed of a first conductive material 7 and first insulating media 8 around the first conductive material, and the bottom of the groove gate is coated by the N-type carrier storage layer 11; the surface of the area between the discontinuously distributed groove grids is covered with a plane grid structure; the planar gate structure comprises a second insulating medium 10 and a first conductive material 9 covering the second insulating medium 10; one side of the planar gate structure is in contact with the surface of the N-type heavily doped region 6, and the other side of the planar gate structure covers the upper surfaces of the P-type well region 3 and the N-type carrier storage layer 11 and is in contact with the N-type semiconductor drift region 4;
the longitudinal direction of the device is a third dimension direction which is simultaneously vertical to both the transverse direction of the device and the vertical direction of the device;
the anode structure comprises an N-type buffer layer 12 and a P-type anode region 13, the P-type anode region 13 is positioned in the N-type buffer layer 12, and the lower surface of the N-type buffer layer 12 is connected with the oxygen buried layer 2; and an anode electrode is led out from the P-type anode region 13.
Furthermore, a P-type buried layer 14 is discontinuously distributed in the P-type well region 3 below the planar gate along the longitudinal direction of the device; the P-type buried layer 14 is positioned below the N-type heavily doped region 6 and is in contact with the buried oxide layer 2; one side of the P-type buried layer 14 is in contact with the P-type heavily doped region 5, and the other side of the P-type buried layer is not in contact with the N-type carrier storage layer 11; the P-type buried layer 14 does not extend into the gap between the bottom of the trench gate and the buried oxide layer 2 in the longitudinal direction.
Furthermore, a P-type buried layer 14 which is discontinuously distributed with the N-type heavily doped region 6 along the longitudinal direction of the device is arranged in the P-type well region 3 below the planar gate; the P-type buried layer 14 extends below the planar gate but does not contact the N-type carrier storage layer 11.
Compared with the traditional thin SOI LIGBT structure, the SOI LIGBT structure has the advantages of lower forward conduction voltage drop and better short-circuit resistance.
Drawings
FIG. 1 is a schematic structural view of example 1;
FIG. 2 is a schematic structural diagram of embodiment 2;
FIG. 3 is a schematic structural diagram of embodiment 3.
Detailed Description
The invention is described in detail below with reference to the figures and examples.
Example 1
As shown in fig. 1, the SOI LIGBT of this example includes a substrate layer 1, a buried oxide layer 2, and a top semiconductor layer stacked in this order from bottom to top in the vertical direction of the device; along the transverse direction of the device, the top semiconductor layer is sequentially provided with a cathode structure, a tri-gate structure, an N-type carrier storage layer 11, an N-type semiconductor drift region 4 and an anode structure from one side to the other side;
the cathode structure comprises a P-type well region 3 and a P-type heavily doped region 5 which penetrate through the top semiconductor layer along the vertical direction of the device, the P-type well region 3 and the P-type heavily doped region 5 are in mutual contact, and the P-type well region 3 is positioned on one side close to the N-type semiconductor drift region 4; an N-type heavily doped region 6 is arranged on the upper layer of the P-type well region 3; cathodes are led out from the upper surfaces of the P-type heavily doped region 5 and the N-type heavily doped region 6;
the device transverse direction and the device vertical direction are perpendicular to each other;
the triple-gate structure is positioned between the cathode structure and the N-type semiconductor drift region 4, and comprises groove gates and plane gates which are distributed discontinuously along the longitudinal direction of the device; the groove gate extends downwards from the surfaces of the P-type well region 3 and the N-type carrier storage layer 11 and is composed of a first conductive material 7 and a first insulating medium 8 around the first conductive material, and the bottom of the groove gate is not in contact with the buried oxide layer 2; the surface of the area between the discontinuously distributed groove grids is covered with a plane grid structure; the planar gate structure comprises a second insulating medium 10 and a first conductive material 9 covering the second insulating medium 10; one side of the planar gate structure is in contact with the surface of the N-type heavily doped region 6, and the other side of the planar gate structure covers the upper surfaces of the P-type well region 3 and the N-type carrier storage layer 11 and is in contact with the N-type semiconductor drift region 4;
the longitudinal direction of the device is a third dimension direction which is simultaneously vertical to both the transverse direction of the device and the vertical direction of the device;
the anode structure comprises an N-type buffer layer 12 and a P-type anode region 13, the P-type anode region 13 is positioned in the N-type buffer layer 12, and the lower surface of the N-type buffer layer 12 is connected with the oxygen buried layer 2; and an anode electrode is led out from the P-type anode region 13.
The working principle of the embodiment is as follows:
when the device is conducted in the forward direction, the side wall of the groove gate of the tri-gate structure blocks a cavity channel, so that the injection enhancement effect is achieved, and the forward conduction voltage drop of the device is reduced; meanwhile, the N-type carrier storage layer plays a role in blocking holes, promotes electrons to be injected into a drift region, enhances the conductivity modulation effect and further reduces the forward conduction voltage drop. When the forward blocking is performed, the groove grid plays a role of depleting the carrier storage layer, so that the device can still maintain high withstand voltage under the condition of high concentration of the storage layer. Meanwhile, the P buried layer is introduced into the cathode of the device and is in contact with the buried oxide layer, a low-resistance path of a cavity is provided, latch-up is inhibited, and short-circuit resistance of the device is improved.
Example 2
Compared with the embodiment 1, in the embodiment, the P-type buried layers 14 are discontinuously distributed in the P-type well region 3 below the planar gate along the longitudinal direction of the device; the P-type buried layer 14 is positioned below the N-type heavily doped region 6 and is in contact with the buried oxide layer 2; one side of the P-type buried layer 14 is in contact with the P-type heavily doped region 5, and the other side of the P-type buried layer is not in contact with the N-type carrier storage layer 11; the P-type buried layer 14 does not extend into the gap between the bottom of the trench gate and the buried oxide layer 2 in the longitudinal direction
Compared with embodiment 1, in a forward conduction state, hole current can be collected by P + through the P buried layer, latch-up is inhibited, and short-circuit resistance of the device is improved.
Example 3
Compared with the embodiment 1, in the embodiment, the P-type buried layer 14 is discontinuously distributed with the N-type heavily doped region 6 along the longitudinal direction of the device in the P-type well region 3 below the planar gate; the P-type buried layer 14 extends below the planar gate but does not contact the N-type carrier storage layer 11
Compared with embodiment 1, in a forward conduction state, a part of channels are sacrificed, the forward conduction voltage drop of the device is slightly increased, but the P buried layer can better collect hole current, latch-up is better inhibited, and the short-circuit resistance of the device is improved.
Claims (3)
1. A three-gate thin SOI LIGBT with a carrier storage layer comprises a substrate layer (1), a buried oxide layer (2) and a top semiconductor layer which are sequentially stacked from bottom to top along the vertical direction of a device; along the transverse direction of the device, the top semiconductor layer is sequentially provided with a cathode structure, a tri-gate structure, an N-type carrier storage layer (11), an N-type semiconductor drift region (4) and an anode structure from one side to the other side;
the cathode structure comprises a P-type well region (3) and a P-type heavily doped region (5) which penetrate through the top semiconductor layer along the vertical direction of the device, the P-type well region (3) and the P-type heavily doped region (5) are in mutual contact, and the P-type well region (3) is positioned on one side close to the N-type semiconductor drift region (4); an N-type heavily doped region (6) is arranged on the upper layer of the P-type well region (3); cathodes are led out from the upper surfaces of the P-type heavily doped region (5) and the N-type heavily doped region (6);
the device transverse direction and the device vertical direction are perpendicular to each other;
the triple-gate structure is positioned between the cathode structure and the N-type semiconductor drift region (4), and comprises groove gates and plane gates which are distributed discontinuously along the longitudinal direction of the device; the groove grid extends downwards from the surfaces of the P-type well region (3) and the N-type carrier storage layer (11) and is composed of a first conductive material (7) and first insulating media (8) around the first conductive material, and the bottom of the groove grid is coated by the N-type carrier storage layer (11); the surface of the area between the discontinuously distributed groove grids is covered with a plane grid structure; the planar gate structure comprises a second insulating medium (10) and a first conductive material (9) covering the second insulating medium (10); one side of the planar gate structure is in contact with the surface of the N-type heavily doped region (6), and the other side of the planar gate structure covers the upper surfaces of the P-type well region (3) and the N-type current carrier storage layer (11) and is in contact with the N-type semiconductor drift region (4);
the longitudinal direction of the device is a third dimension direction which is simultaneously vertical to both the transverse direction of the device and the vertical direction of the device;
the anode structure comprises an N-type buffer layer (12) and a P-type anode region (13), the P-type anode region (13) is positioned in the N-type buffer layer (12), and the lower surface of the N-type buffer layer (12) is connected with the oxygen buried layer (2); and an anode electrode is led out of the P-type anode region (13).
2. The thin SOLILIGBT with a triple gate having a carrier storage layer according to claim 1, characterized in that P-type buried layers (14) are discontinuously distributed in the longitudinal direction of the device in the P-type well region (3) under said planar gate; the P-type buried layer (14) is positioned below the N-type heavily doped region (6) and is in contact with the buried oxide layer (2); one side of the P-type buried layer (14) is in contact with the P-type heavily doped region (5), and the other side of the P-type buried layer is not in contact with the N-type carrier storage layer (11); the P-type buried layer (14) does not extend into the gap between the bottom of the trench gate and the buried oxide layer (2) in the longitudinal direction.
3. The thin SOLILIGBT with a carrier storage layer according to claim 1, characterized in that a P-type buried layer (14) is arranged in the P-type well region (3) under the planar gate and is discontinuously distributed with the N-type heavily doped region (6) along the longitudinal direction of the device; the P-type buried layer (14) extends into the lower portion of the planar gate, but is not in contact with the N-type carrier storage layer (11).
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| CN109887998A (en) * | 2019-03-07 | 2019-06-14 | 电子科技大学 | A kind of thin SOI LIGBT with folded slot grid |
| CN110504168B (en) * | 2019-08-29 | 2020-08-28 | 电子科技大学 | Manufacturing method of multi-groove-grid transverse high-voltage power device |
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| CN102842612A (en) * | 2012-09-11 | 2012-12-26 | 电子科技大学 | Insulated-gate bipolar transistor with embedded island structure |
| CN103794638A (en) * | 2012-10-26 | 2014-05-14 | 中国科学院微电子研究所 | IGBT device and manufacturing method thereof |
| CN105047704A (en) * | 2015-06-30 | 2015-11-11 | 西安理工大学 | High voltage IGBT having communicated storage layer and manufacturing method |
| CN107482058A (en) * | 2017-09-25 | 2017-12-15 | 电子科技大学 | A kind of thin SOI LIGBT devices with carrier accumulation layer |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102842612A (en) * | 2012-09-11 | 2012-12-26 | 电子科技大学 | Insulated-gate bipolar transistor with embedded island structure |
| CN103794638A (en) * | 2012-10-26 | 2014-05-14 | 中国科学院微电子研究所 | IGBT device and manufacturing method thereof |
| CN105047704A (en) * | 2015-06-30 | 2015-11-11 | 西安理工大学 | High voltage IGBT having communicated storage layer and manufacturing method |
| CN107482058A (en) * | 2017-09-25 | 2017-12-15 | 电子科技大学 | A kind of thin SOI LIGBT devices with carrier accumulation layer |
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