CN109103240B - Silicon-on-insulator lateral insulated gate bipolar transistor with low conduction power consumption - Google Patents
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- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 18
- 229920005591 polysilicon Polymers 0.000 claims description 18
- 239000000758 substrate Substances 0.000 claims description 6
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- H—ELECTRICITY
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- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
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Abstract
The invention relates to a power semiconductor technology, in particular to a silicon-on-insulator transverse insulated gate bipolar transistor with low conduction power consumption. The cathode region of the traditional transverse insulated gate bipolar transistor is improved, the device is divided into an MOS region and a traditional LIGBT structure region through an isolation oxide layer, the MOS region is divided into a first NMOS region and a second MOS region, and the first NMOS region and the second MOS region share a P + source short-circuit region. The grid electrode of the traditional LIGBT structure region and the grid electrode of the first NMOS are connected with each other through metal to serve as the grid electrode of the device, the N + drain region of the first NMOS is connected with the N + source region of the traditional LIGBT through metal to serve as the grid electrode of the device, the P + source region of the traditional LIGBT is connected with the grid electrode and the drain electrode of the second N-type MOS through metal to serve as the grid electrode of the device, the N + source region of the traditional LIGBT is connected with the N + drain region of the first N-type MOS through metal to serve as the drain electrode of the first N-type MOS, the N + source regions of the first NMOS and the second NMOS and the shared P + source short-circuit region serve as the cathode of the device through metal short circuits, and the anode of the traditional LIGBT structure region serves as the anode of the device.
Description
Technical Field
The invention belongs to the technical field of power semiconductors, and particularly relates to a silicon-on-insulator lateral insulated gate bipolar transistor with low conduction power consumption.
Background
An Insulated Gate Bipolar Transistor (IGBT) is a mixed power electronic device consisting of a power MOS field effect transistor and a bipolar transistor, and has the characteristic of combining MOS with MOS input and bipolar output functions, the MOSFET structure is used for providing base driving current for the bipolar junction transistor, and the bipolar junction transistor modulates the conductivity of a drift region of the MOSFET mechanism, so that the IGBT has the advantages of high input impedance, small control power, simple driving circuit, high switching speed and small switching loss of the MOSFET, and has the advantages of large current density, low saturation voltage and strong current processing capacity of the bipolar power transistor, and is an ideal switching device in the field of power electronics. For switching devices, it is particularly important to reduce the power consumption at the time of conduction.
Disclosure of Invention
The invention aims to provide a silicon-on-insulator lateral insulated gate bipolar transistor structure with low conduction power consumption, aiming at the problem of high conduction power consumption of the conventional lateral insulated gate bipolar transistor. The device of the invention utilizes latch-up effect to obviously reduce the on-resistance of the device when the device is conducted, thereby reducing the conducting power consumption of the device.
The technical scheme of the invention is as follows: a low-conduction power consumption transverse insulated gate bipolar transistor comprises a cell structure, a P-type substrate 1, buried oxide 2 on the P-type substrate and an N-type epitaxial layer on the buried oxide 2, and is characterized in that an isolation oxide layer 5 is arranged on the N-type epitaxial layer along the transverse direction of a device, the isolation oxide layer 5 penetrates through the N-type epitaxial layer along the vertical direction of the device, and the N-type epitaxial layer is divided into a first N-type epitaxial layer 3 and a second N-type epitaxial layer 4 along the transverse direction of the device;
a first P-type well region 6 is arranged on the upper portion of the first N-type epitaxial layer 3, two N-type MOS tubes are arranged on the upper portion of the first P-type well region 6, the two N-type MOS tubes share a P + source short-circuit region 13, the first N-type MOS region and the second NMOS region are respectively located on the left side and the right side of the P + source short-circuit region 13, namely the P + source short-circuit region 13 is located in the middle of the upper layer of the first P-type well region 6; the first N-type MOS region comprises a first N + drain region 8, a first N + source region 9 and a first gate oxide layer 110, wherein the first N + source region 9 is in contact with the P + source short-circuit region 13, and the first N + drain region 8 is positioned on one side of the upper layer of the first P-type well region 6; one end of the first gate oxide layer 110 extends to the upper surface of the first N + drain region 8, the other end extends to the upper surface of the first N + source region 9, and a first polysilicon gate 120 is arranged on the upper surface of the first gate oxide layer 110; a first cathode metal 131 is arranged above the first N + source region 9; a first anode metal 130 is arranged above the first N + drain region 8; the second N-type MOS region comprises a second N + source region 10, a second N + drain region 11 and a second gate oxide layer 111, wherein the second N + source region 10 is in contact with the P + source short-circuit region 13, and the second N + drain region 11 is positioned on the other side of the upper layer of the first P-type well region 6 and is in contact with the isolation oxide layer 5; a second cathode metal 131 is arranged above the second N + source region 10, one end of the second gate oxide layer 111 extends to the upper surface of the second N + drain region 11, the other end extends to the upper surface of the second N + source region 10, and a second polysilicon gate 121 is arranged on the upper surface of the second gate oxide layer 111; a second anode metal 133 is arranged above the second N + drain electrode;
a second P-type well region 7 and an N-type buffer layer 14 are arranged on two sides of the upper layer of the second epitaxial layer 4, wherein the second P-type well region 7 is in contact with the isolation oxide layer 5, a third P + drain region 15 is arranged on one side, far away from the second P-type well region 7, of the upper layer of the N-type buffer layer 14, and a third anode metal 136 is arranged above the third P + drain region 15; a third P + source region 16 and a third N + source region 12 are arranged on the upper part of the third P-type well region 7, and the third P + source region 16 is in contact with the isolation oxide layer 5; a third cathode metal 134 is disposed above the third P + source region 16, and a fourth cathode metal 135 is disposed above the third N + source region 12; a third gate oxide layer 112 is arranged above the third P-type well region 10, one boundary of the third gate oxide layer 112 extends to be above the third N + source region 12, and the other boundary extends to be above the third N-type epitaxial layer 4; a third polysilicon gate 122 is arranged on the third gate oxide layer 112;
the first cathode metal 131 is a device cathode; the first polysilicon gate 120 and the third polysilicon gate 122 are interconnected through metal to serve as device gates; the first anode metal 130 is connected to the fourth cathode metal 135 by metal interconnects; the second polysilicon gate 121 is connected to a second anode metal 133 and a third cathode metal 134 through metal interconnects; the third anode metal 136 is the device anode.
The invention has the beneficial effects that when the device is conducted and the anode voltage is lower, the second NMOS tube is not started, the potential of the P-type well region in the traditional LIGBT structure region is raised, the parasitic NPN transistor is started, so that the device enters a latch state, and strong conductance modulation is formed in the traditional LIGBT structure region, thereby greatly reducing the conducting resistance. With the gradual increase of the anode voltage, the second NMOS tube is conducted, so that the voltage of a P-type well region in the traditional LIGBT structure region is clamped, the parasitic NPN transistor is turned off, and the device is out of a latch state and gradually enters a saturation state.
Drawings
FIG. 1 is a cross-sectional block diagram of a conventional SOI lateral IGBT device;
FIG. 2 is a cross-sectional view (not shown) of a low turn-on power SOI lateral IGBT device according to the present invention;
FIG. 3 is a cross-sectional view (in prime) of a low turn-on power SOI lateral IGBT device according to the present invention;
FIG. 4 is a current path diagram of a low turn-on power consumption SOI lateral insulated gate bipolar transistor under a low anode voltage operating condition;
FIG. 5 is a current path diagram after saturation of a low turn-on power consumption SOI lateral insulated gate bipolar transistor according to the present invention under a large anode voltage;
FIG. 6 is an equivalent simplified circuit diagram of a conventional SOI lateral bipolar transistor and a current flow diagram when on;
FIG. 7 is an equivalent simplified circuit diagram of a low turn-on power consumption SOI lateral insulated gate bipolar transistor and its current flow diagram operating in the linear region;
FIG. 8 is an equivalent simplified circuit diagram of a low turn-on power consumption SOI lateral insulated gate bipolar transistor and its current flow diagram operating in the saturation region;
FIG. 9 is a diagram comparing the forward withstand voltage of the LIGBT device of the present invention with that of a conventional LIGBT device;
FIG. 10 is a graph comparing the forward conduction I-V characteristic curves of the LIGBT device of the present invention and a LIGBT device of a conventional structure;
FIG. 11 is a graph comparing hole concentration distributions of a LIGBT device of the present invention and a conventional LIGBT device under the same forward conduction current;
Detailed Description
The present invention will be described in detail below with reference to the accompanying drawings.
Fig. 3 is a structure of a low turn-on power consumption lateral insulated gate bipolar transistor device, as shown in the figure, the cell structure of the device includes a P-type substrate 1, an embedded oxide layer 2 on the P-type substrate, and an N-type epitaxial layer on the embedded oxide layer 2, and is characterized in that an isolation oxide layer 5 is disposed on the N-type epitaxial layer along the lateral direction of the device, the isolation oxide layer 5 penetrates through the N-type epitaxial layer along the vertical direction of the device, and the N-type epitaxial layer is divided into a first N-type epitaxial layer 3 and a second N-type epitaxial layer 4 along the lateral direction of the device; a first P-type well region 6 is arranged on the upper portion of the first N-type epitaxial layer 3, two N-type MOS tubes are arranged on the upper portion of the first P-type well region 6, the two N-type MOS tubes share a P + source short-circuit region 13, the first N-type MOS region and the second NMOS region are respectively located on the left side and the right side of the P + source short-circuit region 13, namely the P + source short-circuit region 13 is located in the middle of the upper layer of the first P-type well region 6; the first N-type MOS region comprises a first N + drain region 8, a first N + source region 9 and a first gate oxide layer 110, wherein the first N + source region 9 is in contact with the P + source short-circuit region 13, and the first N + drain region 8 is positioned on one side of the upper layer of the first P-type well region 6; one end of the first gate oxide layer 110 extends to the upper surface of the first N + drain region 8, the other end extends to the upper surface of the first N + source region 9, and a first polysilicon gate 120 is arranged on the upper surface of the first gate oxide layer 110; a first cathode metal 131 is arranged above the first N + source region 9; a first anode metal 130 is arranged above the first N + drain region 8; the second N-type MOS region comprises a second N + source region 10, a second N + drain region 11 and a second gate oxide layer 111, wherein the second N + source region 10 is in contact with the P + source short-circuit region 13, and the second N + drain region 11 is positioned on the other side of the upper layer of the first P-type well region 6 and is in contact with the isolation oxide layer 5; a second cathode metal 131 is arranged above the second N + source region 10, one end of the second gate oxide layer 111 extends to the upper surface of the second N + drain region 11, the other end extends to the upper surface of the second N + source region 10, and a second polysilicon gate 121 is arranged on the upper surface of the second gate oxide layer 111; a second anode metal 133 is arranged above the second N + drain electrode; a second P-type well region 7 and an N-type buffer layer 14 are arranged on two sides of the upper layer of the second epitaxial layer 4, wherein the second P-type well region 7 is in contact with the isolation oxide layer 5, a third P + drain region 15 is arranged on one side, far away from the second P-type well region 7, of the upper layer of the N-type buffer layer 14, and a third anode metal 136 is arranged above the third P + drain region 15; a third P + source region 16 and a third N + source region 12 are arranged on the upper part of the third P-type well region 7, and the third P + source region 16 is in contact with the isolation oxide layer 5; a third cathode metal 134 is disposed above the third P + source region 16, and a fourth cathode metal 135 is disposed above the third N + source region 12; a third gate oxide layer 112 is arranged above the third P-type well region 10, one boundary of the third gate oxide layer 112 extends to be above the third N + source region 12, and the other boundary extends to be above the third N-type epitaxial layer 4; a third polysilicon gate 122 is arranged on the third gate oxide layer 112; the first cathode metal 131 is a device cathode; the first polysilicon gate 120 and the third polysilicon gate 122 are interconnected through metal to serve as device gates; the first anode metal 130 is connected to the fourth cathode metal 135 by metal interconnects; the second polysilicon gate 121 is connected to a second anode metal 133 and a third cathode metal 134 through metal interconnects; the third anode metal 136 is the device anode.
As shown in fig. 1, is a conventional silicon-on-insulator lateral bipolar transistor. Referring to fig. 2, the present invention provides a low turn-on power consumption soi igbt. The invention is different from the traditional LIGBT structure in that the invention carries out reconstruction on the cathode region of the device. The cathode metal of the traditional LIGBT structure is simultaneously in short circuit with a P + source region and an N + source region, the metal on the P + source region and the N + source region in the traditional LIGBT structure region is separated, an N-type MOS tube is externally connected to the N + source region of the traditional LIGBT (the grid electrode of the traditional LIGBT is connected with the grid electrode of the N-type MOS tube, the N + source region of the traditional LIGBT is connected with the N + drain region of the N-type MOS tube, and the source electrode of the N-type MOS tube is used as the cathode of the invention), and another N-type MOS tube is externally connected to the P + source region of the traditional LIGBT (the P + source region of the traditional LIGBT is simultaneously connected with the N + drain region and the grid electrode of the N-type MOS tube, and the source electrode of the N-type MOS. Meanwhile, the MOS region and the conventional LIGBT region are isolated by an isolation oxide layer.
The invention provides a low-conduction power consumption silicon-on-insulator transverse insulated gate bipolar transistor, as shown in fig. 3, the working principle is as follows:
on-state linear region principle: applying a voltage larger than a threshold voltage on the grid electrode of the device, when the anode voltage of the device is smaller than the built-in potential of the PN junction, allowing electrons to sequentially flow through the first NOMS region and the N channel of the LIGBT from the cathode of the device, and finally flow into a drift region (a third N-type epitaxial layer 5) of the LIGBT to provide a base current for the parasitic PNP tube, as shown in FIG. 4; when the anode voltage of the device is smaller but larger than the built-in potential of the PN junction, holes are injected into a drift region (a third N-type epitaxial layer 5) of the LIGBT from the anode of the device, and meanwhile, because the voltage on the gate of the second NMOS tube does not reach the threshold voltage, the second NMOS tube is not turned on, the holes are prevented from flowing to the cathode of the device from a third P + source region, so that the holes are accumulated in a P well region (a third P well region 10) of the LIGBT, and the potential of the P well region (the third P well region 10) is raised. When the potential between the third P well region 10 and the third N + source region 15 is greater than the potential built in the PN junction, an NPN parasitic triode formed by the third N + source region 15, the third P well region 10, and the third N type epitaxial layer 5 triggers, and a large amount of electrons are injected into the drift layer through the P well region, so that the carrier density of the drift layer of the device is significantly increased, the current capability is improved, and low on-resistance is realized.
The principle of an on-state saturation region: when the anode voltage in the on state is further increased, the strong conductivity modulation effect of the conventional LIGBT region causes the conduction voltage drop of the conventional LIGBT region to be lower, so that the potentials of the third P-well region and the third N + source region are increased accordingly. Because the third P well region (third P well region 10) is connected to the gate and drain of the second NMOS, the gate and drain potentials of the second NMOS increase accordingly, when the potential of the P well region is greater than the threshold voltage of the second NMOS, the second NMOS is turned on, holes may flow from the third P well region 10 to the device cathode through the second NMOS, the potential of the third P well region is clamped by the second NMOS, and the potential of the third N + source region 10 may continue to be raised. When the potential between the P well region and the third N + source region is smaller than the built-in potential of the PN junction, the NPN parasitic triode formed by the third N + source region 15, the third P well region 10, and the third N type epitaxial layer 5 is turned off, the device electron current flows away through the MOS channel of the LIGBT, and the device hole current flows from the second NMOS to the device cathode through the third P well region, so that the device enters a saturation state.
In order to verify the advantages of the structure, the structure of the device is contrastively simulated by adopting semiconductor device simulation software Medici, and the results are shown in FIGS. 4-11, wherein FIG. 4 is a current flow diagram of the structure of the invention when the conventional LIGBT structure region enters a latch-up state at a lower anode voltage. As can be seen, the latch-up of the device occurs at this time, and the second NMOS is not turned on at this time. Fig. 5 is a current flow diagram when the device enters the saturation state after the anode voltage continues to increase, and the device exits the latch-up state and gradually enters the saturation operating region due to the turn-on of the second NMOS. Fig. 6 is an equivalent simplified circuit diagram of a conventional LIGBT structure and a current flow diagram thereof in a forward conducting state, and fig. 7 and 8 are current flow diagrams of the device of the present invention operating in a linear region and a saturation region, respectively. Comparing fig. 6, 7 and 8, it can be seen that the current flow direction of the device of the present invention is not consistent in the linear region and the saturation region, and fig. 7 shows that when the device of the present invention works in the linear region, the parasitic thyristor composed of the PNP transistor and the parasitic NPN transistor generates latch-up effect, so that strong conductance modulation is formed in the drift region to reduce the on-resistance of the device. Fig. 8 shows that the current flow direction when the device of the present invention operates in the saturation operating region is the same as that when the device of the conventional structure operates. Fig. 9 is a comparison graph of the voltage endurance of the device of the present invention and the conventional LIGBT structure, and it can be seen from the graph that the voltage endurance of the structure of the present invention is not obviously different from that of the conventional structure. Fig. 10 is a comparison of the forward on characteristics of the device of the present invention and the device of the conventional structure, and it can be clearly seen that the present invention has a lower on resistance and thus lower on power consumption. Fig. 11 is a comparison graph of the hole concentration distribution under the same forward conduction current of the device of the present invention and the conventional structure, the carrier distribution in the drift region of the device of the present invention is more uniform, and the concentration is one order of magnitude higher than that of the conventional structure LIGBT, which is beneficial to reducing the on-resistance of the device.
Claims (1)
1. A low-conduction power consumption transverse insulated gate bipolar transistor comprises a cell structure, a first N-type epitaxial layer and a second N-type epitaxial layer, wherein the cell structure comprises a P-type substrate (1), an oxygen burying layer (2) on the P-type substrate (1) and an N-type epitaxial layer on the oxygen burying layer (2), and the transistor is characterized in that an isolation oxide layer (5) is arranged on the N-type epitaxial layer along the transverse direction of a device, the isolation oxide layer (5) penetrates through the N-type epitaxial layer along the vertical direction of the device, and the N-type epitaxial layer is divided into the first N-type epitaxial layer (3) and the second N-type epitaxial layer;
a first P-type well region (6) is arranged on the upper portion of the first N-type epitaxial layer (3), two N-type MOS tubes are arranged on the upper portion of the first P-type well region (6), the two N-type MOS tubes share a P + source short-circuit region (13), the first N-type MOS region and the second NMOS region are respectively located on the left side and the right side of the P + source short-circuit region (13), namely the P + source short-circuit region (13) is located in the middle of the upper layer of the first P-type well region (6); the first N-type MOS region comprises a first N + drain region (8), a first N + source region (9) and a first gate oxide layer (110), wherein the first N + source region (9) is in contact with the P + source short-circuit region (13), and the first N + drain region (8) is positioned on one side of the upper layer of the first P-type well region (6); one end of the first gate oxide layer (110) extends to the upper surface of the first N + drain region (8), the other end of the first gate oxide layer extends to the upper surface of the first N + source region (9), and a first polysilicon gate (120) is arranged on the upper surface of the first gate oxide layer (110); a first cathode metal (131) is arranged above the first N + source region (9); a first anode metal (130) is arranged above the first N + drain region (8); the second N-type MOS region comprises a second N + source region (10), a second N + drain region (11) and a second gate oxide layer (111), wherein the second N + source region (10) is in contact with the P + source short-circuit region (13), and the second N + drain region (11) is positioned on the other side of the upper layer of the first P-type well region (6) and is in contact with the isolation oxide layer (5); the upper part of the second N + source region (10) is in contact with first cathode metal (131), one end of the second gate oxide layer (111) extends to the upper surface of the second N + drain region (11), the other end of the second gate oxide layer extends to the upper surface of the second N + source region (10), and a second polysilicon gate (121) is arranged on the upper surface of the second gate oxide layer (111); a second anode metal (133) is arranged above the second N + drain region (11);
a second P-type well region (7) and an N-type buffer layer (14) are arranged on two sides of the upper layer of the second N-type epitaxial layer (4), wherein the second P-type well region (7) is in contact with the isolation oxide layer (5), a third P + drain region (15) is arranged on one side, far away from the second P-type well region (7), of the upper layer of the N-type buffer layer (14), and a third anode metal (136) is arranged above the third P + drain region (15); a third P + source region (16) and a third N + source region (12) are arranged on the upper part of the second P-type well region (7), and the third P + source region (16) is in contact with the isolation oxide layer (5); a second cathode metal (134) is arranged above the third P + source region (16), and a third cathode metal (135) is arranged above the third N + source region (12); a third gate oxide layer (112) is arranged above the second P-type well region (7), one boundary of the third gate oxide layer (112) extends to be above the third N + source region (12), and the other boundary extends to be above the second N-type epitaxial layer (4); a third polysilicon gate (122) is arranged on the third gate oxide layer (112);
the first cathode metal (131) is a device cathode; the first polysilicon gate (120) and the third polysilicon gate (122) are interconnected through metal to serve as device gates; the first anodic metal (130) is connected to a third cathodic metal (135) by a metal interconnect; the second polysilicon gate (121) is connected with a second anode metal (133) and a second cathode metal (134) through metal interconnection; the third anode metal (136) is a device anode.
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| CN109920840B (en) * | 2019-03-20 | 2022-02-11 | 重庆邮电大学 | L-shaped SiO2Composite RC-LIGBT device with isolation layer |
| CN113078211B (en) * | 2021-03-25 | 2022-04-22 | 电子科技大学 | Integrated MOS self-adaptive control SOI LIGBT |
| CN113066862B (en) * | 2021-03-25 | 2022-04-22 | 电子科技大学 | Integrated MOS self-adaptive control SOI LIGBT |
| CN114784102B (en) * | 2022-05-05 | 2023-05-02 | 电子科技大学 | LIGBT with mixed conduction mode |
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|---|---|---|---|---|
| JP2002270844A (en) * | 2001-03-07 | 2002-09-20 | Toshiba Corp | Semiconductor device and manufacturing method of the same |
| CN105826367A (en) * | 2016-03-18 | 2016-08-03 | 东南大学 | Large-current silicon on insulator lateral insulated gate bipolar transistor device |
| CN106505101A (en) * | 2016-10-19 | 2017-03-15 | 东南大学 | A kind of high current silicon-on-insulator lateral insulated-gate bipolar transistor device |
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| CN109103240A (en) | 2018-12-28 |
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