CN210723040U - Large-current silicon-on-insulator lateral insulated gate bipolar transistor - Google Patents

Abstract

The utility model discloses a silicon lateral insulated gate bipolar transistor on a heavy current insulator, which belongs to the technical field of semiconductor integrated circuits and comprises an NMOS tube A and a self-biased PMOS tube B, NMOS tube C, wherein an N + drain region of the NMOS tube A is interconnected with an N + source region of the NMOS tube C through metal, the N + source region of the NMOS tube A is connected with a P + drain region of the PMOS tube B, the N + source region and the P + drain region are used as cathodes of the device of the utility model through metal short circuits, the polysilicon connected with the cathode metal is used as the grid electrode of the PMOS tube B, the anode of the traditional silicon transverse insulated gate bipolar transistor is used as the anode of the device of the utility model, compared with the silicon transverse insulated gate bipolar transistor on the insulator in the prior art, under the condition of equal conduction voltage drop, the current density is higher, the conduction loss and the chip area are smaller, and the problems in the prior art are solved.

Description

Large-current silicon-on-insulator lateral insulated gate bipolar transistor

Technical Field

The utility model relates to a silicon lateral insulated gate bipolar transistor on heavy current insulator belongs to semiconductor integrated circuit technical field.

Background

An Insulated Gate Bipolar Transistor (IGBT) is a composite power device formed by combining and evolving an MOS (metal oxide semiconductor) gate device structure and a bipolar transistor structure, has the characteristics of an MOS (metal oxide semiconductor) transistor and a bipolar transistor, has good compromise relationship between on-state current and switching loss, and has a transverse structure which is widely applied to a power integrated circuit; for example, the Chinese patent application number is: 201510998522.X, discloses a lateral insulated gate bipolar transistor, which is additionally provided with an electric field strengthening unit on the basis of a LIGBT device in the prior art, wherein the unit strengthening unit consists of an accelerating grid, an accelerating grid heavily doped region, a high-resistance conductive region, a grounding doped region and a grounding electrode, the electric field strengthening unit is used for generating an electric field pointing to the lower surface of the electric field strengthening unit from an anode, the electric field strengthening unit is isolated from a drift region through an insulating medium, and the structure can improve the current density, but has the problems of larger leakage current and additional driving circuit. For another example, in the document "amplified structured semiconductor-assisted regulated SOI-LIGBT with Low On-state Voltage", a LIGBT device with self-modulated conductance and Low On-state Voltage is proposed, but the device needs to be made with an isolation dielectric region and a complicated trench etching process is required.

In summary, how to obtain an igbt with a larger current density, smaller conduction loss and smaller chip area under the condition of equal conduction voltage drop becomes a technical problem to be solved urgently.

SUMMERY OF THE UTILITY MODEL

To the not enough that exists among the prior art, the utility model aims to provide a horizontal insulated gate bipolar transistor of silicon on heavy current insulator has solved the problem that appears among the prior art.

The utility model relates to a silicon transverse insulated gate bipolar transistor on a large-current insulator, which comprises a P-type substrate, wherein buried oxygen, an N-type epitaxial layer and an N-type buffer layer are sequentially arranged above the P-type substrate, the anode, the cathode and the grid electrode of the transistor are arranged above the N-type epitaxial layer, an NMOS (N-channel metal oxide semiconductor) tube A, a self-biased PMOS tube B and an NMOS tube C are arranged above the N-type epitaxial layer, a first P-type well region and a second P-type well region are arranged on one side above the N-type epitaxial layer, the first P-type well region and the second P-type well region are respectively close to the anode and the cathode of the transistor, the NMOS tube A is arranged in the second P-type well region, the self-biased PMOS tube B is bridged between the first P-type well region and the second P-type well region, the NMOS tube C is bridged between the first P-type well region and the N-type epitaxial layer, the NMOS tube A is connected with the self-biased PMOS tube, the self-bias PMOS tube B comprises a tube B P + drain region, the NMOS tube C comprises a tube C N + source region, the tube A N + drain region is interconnected with the tube C N + source region, the tube A N + source region is connected with the tube B P + drain region and then is led out as a cathode of a transistor through a cathode metal short circuit, the N-type buffer layer is arranged on one side of the N-type epitaxial layer, a P + anode region is arranged on one side, away from the cathode direction of the transistor, of the upper layer of the N-type buffer layer, the tube C N + source region, the first P-type well region and the N-type epitaxial layer jointly form an NPN-type parasitic triode, and the first P-type well region, the N-type epitaxial layer and the P + anode.

The utility model discloses the negative pole district of transistor is different with prior art silicon lateral insulated gate bipolar transistor's negative pole district, divide into NMOS pipe A, from bias PMOS pipe B, NMOS pipe C, and pipe A, pipe B and pipe C distribute compactly. The grid of NMOS pipe A and the grid interconnection of NMOS pipe C are as the grid (Gate) of device, and NMOS pipe A's N + drain region and NMOS pipe C's N + source region interconnect, and NMOS pipe A's N + source region links to each other with the P + drain region from biasing PMOS pipe B, and the two is regarded as through the negative pole metal short circuit the utility model discloses the negative pole (Cathode) of device, the polycrystalline silicon that links to each other with above-mentioned negative pole metal is as from biasing PMOS pipe B's grid, and prior art silicon lateral insulation grid bipolar transistor's positive pole is regarded as the utility model discloses the positive pole (Anode) of device.

Furthermore, anode metal is arranged above the P + anode region, and the anode metal is led out to be used as an anode of the transistor.

Furthermore, the NMOS tube A also comprises a tube A polysilicon gate, the NMOS tube C also comprises a tube C polysilicon gate, and the tube A polysilicon gate is connected with the tube C polysilicon gate and then led out to serve as a gate of the transistor.

Furthermore, the NMOS tube A also comprises a tube A gate oxide layer, the lower surface of the tube A gate oxide layer is respectively contacted with the N + drain region of the tube A and the upper surface of the N + source region of the tube A, the polysilicon gate of the tube A is positioned above the tube A gate oxide layer, tube A metal is arranged above the N + drain region of the tube A, and the tube A metal, the polysilicon gate of the tube A and the cathode metal are not connected with each other.

Further, the self-bias PMOS tube B also comprises a tube B polysilicon gate, and the tube B polysilicon gate is connected with cathode metal.

Furthermore, the self-bias PMOS tube B also comprises a tube B P + source region and a tube B gate oxide layer, the lower surface of the tube B gate oxide layer is respectively contacted with the upper surfaces of the tube B P + drain region and the tube B P + source region, the tube B polysilicon gate is positioned above the tube B gate oxide layer, the cathode metal is positioned above the tube B P + drain region, and the tube A N + source region and the tube B P + drain region are respectively positioned on two sides below the cathode metal.

Furthermore, the NMOS transistor C also comprises a transistor C gate oxide layer, and a transistor C polysilicon gate is positioned above the transistor C gate oxide layer.

Furthermore, a C tube N + source region is adjacent to a B tube P + source region, C tube metal is arranged above the C tube N + source region, a C tube polycrystalline silicon grid, the C tube metal and a B tube polycrystalline silicon grid are not connected with each other, and the A tube metal and the C tube metal are connected with each other.

Furthermore, a first P-type buried layer is arranged in the first P-type well region, and a P + source region of the B tube and an N + source region of the C tube are arranged above the first P-type buried layer.

Furthermore, a second P-type buried layer is arranged in the second P-type well region, and the P + drain region of the B tube, the N + source region of the A tube and the N + drain region of the A tube are arranged above the second P-type buried layer.

Compared with the prior art, the utility model, following beneficial effect has:

a horizontal insulated gate bipolar transistor of silicon on heavy current insulator, compare with the horizontal insulated gate bipolar transistor of silicon on the insulator of prior art, under the voltage drop condition that switches on that equals, have bigger current density, littleer conduction loss and chip area, when anodic voltage is 2.59V, the utility model discloses the current density of device compares prior art device and has increased 47%, and when anodic voltage was 20V, the utility model discloses the current density of device compares prior art device and has increased 103%. It is apparent that the present invention device utilizes latches to increase current density at lower voltages while maintaining a greater current density in the saturation region. Meanwhile, a complex grooving process is not needed, and the problems in the prior art are solved.

Drawings

FIG. 1 is a block diagram of a prior art SOI lateral insulated gate bipolar transistor;

fig. 2 is a structural diagram 1 of a high-current soi lateral igbt according to an embodiment of the present invention;

fig. 3 is a structural diagram 2 of a high-current soi lateral igbt according to an embodiment of the present invention;

fig. 4 is an equivalent simplified circuit diagram of a lateral insulated gate bipolar transistor of silicon in the prior art and a current flow diagram in the forward on state thereof according to an embodiment of the present invention;

fig. 5 is an equivalent simplified circuit diagram of a high-current soi bipolar transistor operating in a linear region and a current flow diagram thereof according to an embodiment of the present invention;

fig. 6 is a current flow diagram of the cathode region of a high-current soi lateral igbt according to an embodiment of the present invention, which operates in a saturation region;

fig. 7 is a current flow diagram of the cathode region when the high-current soi igbt enters the latch-up state at a lower voltage according to an embodiment of the present invention;

fig. 8 is a current flow diagram of the cathode region when the high-current soi bipolar transistor enters a saturation state after the anode voltage continues to increase according to the embodiment of the present invention;

fig. 9 is a graph comparing the breakdown voltage of a high current soi lateral igbt with a LIGBT device in the prior art according to an embodiment of the present invention;

fig. 10 is a comparison graph of the forward conduction characteristics of a high current soi igbt and a prior art LIGBT device with an anode voltage of 2.59V according to an embodiment of the present invention;

fig. 11 is a comparison graph of the forward conduction characteristics of a high-current soi igbt and a LIGBT device in the prior art when the anode voltage is 20V according to an embodiment of the present invention;

in the figure: 1. a P-type substrate; 2. burying oxygen; 3. an N-type epitaxial layer; 4. an N-type buffer layer; 5. a P + anode region; 6. an anode metal; 7. a first P-type well region; 8. a first P-type buried layer; 9. a C tube N + source region; 10. c, a tube gate oxide layer; 11. c, a polysilicon grid; 12. c, tube metal; 13. b pipe P + source area; 14. b, a polysilicon gate; 15. b, a tube gate oxide layer; 16. a cathode metal; 17. a pipe B is a P + drain region; 18. a tube A N + source region; 19. a second P-type well region; 20. an N + drain region of the A tube; 21. a, tube metal; 22. a, a polysilicon gate; 23. a, a tube gate oxide layer; 24. a second P-type buried layer; 25. an NMOS tube A; 26. a self-biased PMOS tube B; 27. and an NMOS tube C.

Detailed Description

The invention will be further described with reference to the following drawings and examples:

example 1:

as shown in fig. 2 and fig. 3, the lateral insulated gate bipolar transistor of silicon on insulator according to the present invention comprises a P-type substrate 1, a buried oxide 2, an N-type epitaxial layer 3 and an N-type buffer layer 4 are sequentially disposed above the P-type substrate 1, an anode, a cathode and a gate of the transistor are disposed above the N-type epitaxial layer 3, an NMOS transistor a25, a self-biased PMOS transistor B26 and an NMOS transistor C27 are disposed above the N-type epitaxial layer 3, a first P-type well region 7 and a second P-type well region 19 are disposed on one side above the N-type epitaxial layer 3, the first P-type well region 7 and the second P-type well region 19 are respectively close to the anode and the cathode of the transistor, wherein an NMOS transistor a25 is disposed in the second P-type well region 19, a self-biased PMOS transistor B26 is bridged between the first P-type well region 7 and the second P-type well region 19, an NMOS transistor C27 is bridged between the first P-type well region 7 and the N-type epitaxial layer 3, and an NMOS transistor a25, the NMOS transistor A25 comprises a transistor A N + drain region 20 and a transistor A N + source region 18, a self-biased PMOS transistor B26 comprises a transistor B P + drain region 17, an NMOS transistor C27 comprises a transistor C N + source region 9, the transistor A N + drain region 20 is interconnected with the transistor C N + source region 9, the transistor A N + source region 18 is connected with the transistor B P + drain region 17 and then is led out in a short circuit mode through a cathode metal 16 to serve as a cathode of the transistor, an N-type buffer layer 4 is arranged on one side of an N-type epitaxial layer 3, a P + anode region 5 is arranged on one side, away from the cathode direction of the transistor, of the upper layer of the N-type buffer layer 4, the transistor C N + source region 9, a first P-type well region 7 and the N-type epitaxial layer 3 jointly form an NPN-type parasitic triode, and the first P-type well region 7, the N-type.

An anode metal 6 is arranged above the P + anode region 5, and the anode metal 6 is led out to be used as an anode of the transistor.

The NMOS tube A25 further comprises an A tube polysilicon gate 22, the NMOS tube C27 further comprises a C tube polysilicon gate 11, and the A tube polysilicon gate 22 is connected with the C tube polysilicon gate 11 and then led out to serve as a gate of the transistor.

The NMOS tube A25 further comprises a tube A gate oxide layer 23, the lower surface of the tube A gate oxide layer 23 is respectively contacted with the N + drain region 20 of the tube A and the upper surface of the N + source region 18 of the tube A, the polysilicon gate 22 of the tube A is positioned above the tube A gate oxide layer 23, a tube A metal 21 is arranged above the N + drain region 20 of the tube A, and the tube A metal 21, the polysilicon gate 22 of the tube A and the cathode metal 16 are not connected with each other.

The self-biased PMOS transistor B26 further includes a B-transistor polysilicon gate 14, the B-transistor polysilicon gate 14 being connected to the cathode metal 16.

The self-bias PMOS transistor B26 further comprises a transistor B P + source region 13 and a transistor B gate oxide layer 15, the lower surface of the transistor B gate oxide layer 15 is respectively contacted with the transistor B P + drain region 17 and the upper surface of the transistor B P + source region 13, the transistor B polysilicon gate 14 is positioned above the transistor B gate oxide layer 15, the cathode metal 16 is positioned above the transistor B P + drain region 17, and the transistor A N + source region 18 and the transistor B P + drain region 17 are respectively positioned on two sides below the cathode metal 16.

The NMOS transistor C27 further includes a transistor C gate oxide 10, and the transistor C polysilicon gate 11 is located above the transistor C gate oxide 10.

The C tube N + source region 9 is adjacent to the B tube P + source region 13, C tube metal 12 is arranged above the C tube N + source region 9, the C tube polycrystalline silicon grid 11, the C tube metal 12 and the B tube polycrystalline silicon grid 14 are not connected with each other, and the A tube metal 21 and the C tube metal 12 are connected with each other.

A first P-type buried layer 8 is arranged in the first P-type well region 7, and a B tube P + source region 13 and a C tube N + source region 9 are arranged above the first P-type buried layer 8.

A second P-type buried layer 24 is arranged in the second P-type well region 19, and the B tube P + drain region 17, the A tube N + source region 18 and the A tube N + drain region 20 are arranged above the second P-type buried layer 24.

The working principle of the embodiment is as follows: as shown in fig. 1, the structure diagram of the prior art soi bipolar transistor of fig. 1 shows that the cathode region of the device of the present invention is different from the cathode region of the prior art soi bipolar transistor, and is divided into an NMOS transistor a25, a self-biased PMOS transistor B26, and an NMOS transistor C27. The grid of NMOS pipe A25 and the grid of NMOS pipe C27 pass through the metal interconnection and do the utility model discloses the grid (Gate) of device, NMOS pipe A25's N + drain region and NMOS pipe C27's N + source district pass through the metal interconnection, and NMOS pipe A25's N + source region links to each other with PMOS pipe B26's P + drain region, and the two regards as through the 16 short circuits of negative pole metal the utility model discloses the negative pole (Cathode) of device, the polycrystalline silicon that links to each other with above-mentioned negative pole metal 16 regards as PMOS pipe B's grid, and prior art silicon lateral insulated Gate bipolar transistor's positive pole is regarded as the utility model discloses the positive pole (Anode) of device. Compared with the prior art silicon-On-insulator lateral insulated gate bipolar transistor (such as the document "integrated structured semiconductor-assisted communication Modulation SOI-LIGBT with Low On-state Voltage"), the SOI-LIGBT has no need of manufacturing an isolation medium region, and obviously has smaller chip area.

The working principle of an on-state linear region is as follows: a voltage larger than the threshold voltage is applied to the gate of the device, and electrons flow from the cathode of the device to the channels of the NMOS tube A25 and the NMOS tube C27 in sequence and finally flow into the drift region (N-type epitaxial layer 3) of the device. When the anode voltage of the device is small, holes are injected into a drift region (an N-type epitaxial layer 3) of the device from the anode of the device, most of the injected holes are accumulated in the first P-type well region 7, so that the potential of the first P-type well region 7 is raised, but the starting voltage of the self-biased PMOS transistor B26 is not reached, and therefore, the self-biased PMOS transistor B26 is not started; when electric potential between first P type trap area 7 and NMOS pipe C27's N + source area (C pipe N + source area 9) is greater than its PN junction built-in electric potential, by C pipe N + source area 9, first P type trap area 7, the parasitic triode of NPN type that N type epitaxial layer 3 constitutes triggers, a large amount of electrons pour into N type epitaxial layer 3 into through first P type trap area 7, consequently the carrier concentration in device drift region increases by a wide margin, and the electric current increases by a wide margin, obviously works as the utility model discloses the current density of device equals with prior art device, the utility model discloses the turn-on voltage of device can be littleer, and the conduction loss is just littleer.

The principle of an on-state saturation region: when the anode voltage continues to increase in the on state, the potential of the first P-type well region 7 also continues to increase, because the P + drain region 17 of the B-transistor is connected to the polysilicon gate 14 of the B-transistor through the cathode metal 16, when the potential of the P-type well region 7 is higher than the absolute value of the threshold voltage of the self-biased PMOS transistor B26, the self-biased PMOS transistor B26 is turned on, and holes can flow into the cathode of the device through the self-biased PMOS transistor B26. In addition, the potential of the first P-well region 7 is clamped after the self-biased PMOS transistor B26 is conducted, and the potential of the N + source region 9 of the C transistor rises along with the increase of the anode voltage due to the equivalent on-resistance between the drain and the source of the NMOS transistor A25. When the potential between the P-type well region 7 and the C tube N + source region 9 is smaller than the built-in potential of the PN junction, the NPN parasitic triode formed by the C tube N + source region 9, the first P-type well region 7 and the N type epitaxial layer 3 is turned off, the electron current of the device flows away through the channel of the NMOS tube C27, the hole current flows into the cathode of the device through the PMOS tube B26, and the device enters a saturated state.

Fig. 4 is the equivalent simplified circuit diagram of the LIGBT device of the prior art and the current flow diagram when it is in the forward conducting state, and fig. 5 and fig. 6 are the equivalent simplified circuit diagram and the current flow diagram of the device of the present invention operating in the linear region and the saturation region respectively. It can be seen from comparison of fig. 5 and fig. 6 that the utility model discloses the device is at the electric current flow direction inconsistent under linear region and the saturation region operating condition, and it can be seen from comparison of fig. 4 and fig. 6, when the saturation work area the utility model discloses the electric current flow direction of device is unanimous basically with the electric current flow direction of prior art structure device. Fig. 5 shows that the device of the present invention has latch-up effect in the linear working region of the parasitic thyristor composed of the PNP type triode and the parasitic NPN type triode, so as to form strong conductance modulation effect in the drift region, and increase the current density of the device by a large margin.

In order to verify the utility model discloses the advantage of device, the utility model discloses a semiconductor simulation software has carried out contrast emulation to the device performance, and the result is as shown in figure 7 and 8. Fig. 7 is a current flow diagram of the cathode region when the device of the present invention enters the latch-up state at a lower voltage. As can be seen from fig. 7, the device latches and the self-biased PMOS transistor B26 is not turned on. Fig. 8 is the cathode region current flow diagram when the device of the present invention enters the saturation state after the anode voltage continues to increase, and the device gradually exits from the latch state and enters the saturation working area along with the turn-off of the parasitic NPN type triode and the opening of the self-biased PMOS transistor B26. Fig. 9 is the utility model discloses the device can be known from the figure with the breakdown voltage's of prior art LIGBT device contrast picture, the utility model discloses the breakdown voltage of device is slightly higher, and it is slightly low to leak current moreover, and the performance is superior to prior art device.

Fig. 10 and 11 are a comparison graph of the forward conduction characteristics of the device of the present invention and the prior art device, fig. 10 shows that when the anode voltage is 2.59V, the current density of the device of the present invention is increased by 47% compared with the prior art device, and the current density is at 500A/cm²When this happens, the anode voltage is reduced by 34.43%, and thus there is less conduction loss. Fig. 11 shows that the current density of the device of the invention increases by 103% compared to the prior art device when the anode voltage is 20V. It is apparent that the device of the present invention utilizes latches to increase current density at low voltages while maintaining a greater current density in the saturation region.

Adopt above to combine the figure description the utility model discloses a lateral insulated gate bipolar transistor of silicon on insulator of embodiment compares with the lateral insulated gate bipolar transistor of silicon on insulator of prior art, under the voltage drop condition that switches on that equals, has bigger current density, and the problem that appears among the prior art has been solved to littleer conduction loss and chip area. The present invention is not limited to the embodiments described, but rather, variations, modifications, substitutions and alterations from the embodiments described herein are possible without departing from the spirit and scope of the invention.

Claims (10)

1. The utility model provides a horizontal insulated gate bipolar transistor of silicon on heavy current insulator, includes P type substrate (1), and the top of P type substrate (1) is equipped with in proper order and buries oxygen (2), N type epitaxial layer (3) and N type buffer layer (4), and the top of N type epitaxial layer (3) is equipped with positive pole, negative pole and the grid of transistor, its characterized in that: an NMOS tube A (25), a self-biased PMOS tube B (26) and an NMOS tube C (27) are arranged above the N-type epitaxial layer (3), a first P-type well region (7) and a second P-type well region (19) are arranged on one side above the N-type epitaxial layer (3), the first P-type well region (7) and the second P-type well region (19) are respectively close to an anode and a cathode of a transistor, the NMOS tube A (25) is arranged in the second P-type well region (19), the self-biased PMOS tube B (26) is bridged between the first P-type well region (7) and the second P-type well region (19), the NMOS tube C (27) is bridged between the first P-type well region (7) and the N-type epitaxial layer (3), the NMOS tube A (25) is connected with the self-biased PMOS tube B (26), the NMOS tube A (25) comprises an A tube N + drain region (20) and an A tube N + source region (18), and the self-biased PMOS tube B (26) comprises a B tube P + drain region (17), the NMOS tube C (27) comprises a C tube N + source region (9), an A tube N + drain region (20) is connected with the C tube N + source region (9), the A tube N + source region (18) is connected with a B tube P + drain region (17) and then is short-circuited and led out to serve as a cathode of a transistor through cathode metal (16), an N-type buffer layer (4) is arranged on one side of an N-type epitaxial layer (3), a P + anode region (5) is arranged on one side, away from the cathode direction of the transistor, of the upper layer of the N-type buffer layer (4), the C tube N + source region (9), a first P-type well region (7) and the N-type epitaxial layer (3) jointly form an NPN-type parasitic triode, and the first P-type well region (7), the N-type epitaxial layer (3) and the P + anode region (5) jointly.

2. A high current soi bipolar transistor as claimed in claim 1 wherein: an anode metal (6) is arranged above the P + anode region (5), and the anode metal (6) is led out to be used as the anode of the transistor.

3. A high current soi bipolar transistor as claimed in claim 1 wherein: the NMOS tube A (25) further comprises a tube A polysilicon gate (22), the NMOS tube C (27) further comprises a tube C polysilicon gate (11), and the tube A polysilicon gate (22) is connected with the tube C polysilicon gate (11) and then serves as a gate of the transistor.

4. A high current soi bipolar transistor as claimed in claim 3 wherein: the NMOS tube A (25) further comprises an A tube gate oxide layer (23), the lower surface of the A tube gate oxide layer (23) is in contact with the upper surfaces of an A tube N + drain region (20) and an A tube N + source region (18) respectively, an A tube polycrystalline silicon gate (22) is located above the A tube gate oxide layer (23), an A tube metal (21) is arranged above the A tube N + drain region (20), and the A tube metal (21), the A tube polycrystalline silicon gate (22) and the cathode metal (16) are not connected with each other.

5. A high current SOI lateral insulated gate bipolar transistor according to claim 4, wherein: the self-bias PMOS tube B (26) further comprises a tube B polysilicon gate (14), and the tube B polysilicon gate (14) is connected with the cathode metal (16).

6. A high current SOI lateral insulated gate bipolar transistor according to claim 5, wherein: the self-bias PMOS tube B (26) further comprises a tube B P + source region (13) and a tube B gate oxide layer (15), the lower surface of the tube B gate oxide layer (15) is in contact with the upper surfaces of a tube B P + drain region (17) and the tube B P + source region (13) respectively, a tube B polysilicon gate (14) is located above the tube B gate oxide layer (15), cathode metal (16) is located above the tube B P + drain region (17), and a tube A N + source region (18) and the tube B P + drain region (17) are located on two sides below the cathode metal (16) respectively.

7. A high current SOI lateral insulated gate bipolar transistor according to claim 6, wherein: the NMOS tube C (27) further comprises a tube C gate oxide layer (10), and a tube C polysilicon gate (11) is located above the tube C gate oxide layer (10).

8. A high current soi bipolar transistor as claimed in claim 7 wherein: the transistor C is characterized in that a transistor C N + source region (9) is adjacent to a transistor B P + source region (13), a transistor C metal (12) is arranged above the transistor C N + source region (9), a transistor C polysilicon gate (11), the transistor C metal (12) and a transistor B polysilicon gate (14) are not connected with each other, and the transistor A metal (21) is connected with the transistor C metal (12).

9. A high current SOI lateral insulated gate bipolar transistor according to claim 6, wherein: a first P-type buried layer (8) is arranged in the first P-type well region (7), and a B tube P + source region (13) and a C tube N + source region (9) are arranged above the first P-type buried layer (8).

10. A high current soi bipolar transistor as claimed in claim 1 wherein: and a second P-type buried layer (24) is arranged in the second P-type well region (19), and the B tube P + drain region (17), the A tube N + source region (18) and the A tube N + drain region (20) are arranged above the second P-type buried layer (24).

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