CN109616518B - MOS grid-controlled thyristor - Google Patents
MOS grid-controlled thyristor Download PDFInfo
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- CN109616518B CN109616518B CN201811525422.5A CN201811525422A CN109616518B CN 109616518 B CN109616518 B CN 109616518B CN 201811525422 A CN201811525422 A CN 201811525422A CN 109616518 B CN109616518 B CN 109616518B
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- 238000009792 diffusion process Methods 0.000 claims abstract description 21
- 238000000034 method Methods 0.000 abstract description 6
- 238000010586 diagram Methods 0.000 description 9
- 230000003071 parasitic effect Effects 0.000 description 8
- 239000004065 semiconductor Substances 0.000 description 6
- 230000004888 barrier function Effects 0.000 description 4
- 230000002401 inhibitory effect Effects 0.000 description 3
- 239000000284 extract Substances 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/74—Thyristor-type devices, e.g. having four-zone regenerative action
- H01L29/744—Gate-turn-off devices
- H01L29/745—Gate-turn-off devices with turn-off by field effect
- H01L29/7455—Gate-turn-off devices with turn-off by field effect produced by an insulated gate structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/74—Thyristor-type devices, e.g. having four-zone regenerative action
- H01L29/749—Thyristor-type devices, e.g. having four-zone regenerative action with turn-on by field effect
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- Thyristors (AREA)
Abstract
The invention provides a MOS grid-controlled thyristor. The MOS gate-controlled thyristor comprises three electrodes of a cathode, a grid and an anode, wherein the grid comprises an NMOS and a PMOS, and the MOS gate-controlled crystalThe brake tube also comprises an N-P-N-P four-layer structure region and P + The diffusion region comprises an N + cathode region, a P base region, an N type drift region, an N + buffer layer and a P + anode region, wherein the N-P-N-P four-layer structure region comprises the N + cathode region, the P base region, the N type drift region, the N + buffer layer and the P + anode region, and the N type drift region is close to the P + And an N-type buried layer is arranged in the diffusion region. The invention can inhibit snapback phenomenon in the starting process of the base resistance control thyristor BRT and the emitter switch thyristor EST, thereby solving the problem of inconsistent starting of multiple cells and improving the working reliability of the device.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a MOS grid-controlled thyristor.
Background
Compared with an Insulated Gate Bipolar Transistor (IGBT), the MOS Gate controlled thyristor has the advantages of low on-resistance, high current density, high turn-on speed, and the like, and is widely applied in the field of pulse power and the like. The MOS grid-controlled thyristor is a thyristor structure mainly composed of N-P-N-P four layers of semiconductor materials, electronic current is injected through NMOS to start positive feedback in the thyristor to conduct a power semiconductor device, and PMOS extracts feedback current to interrupt the positive feedback to turn off the power semiconductor device.
At present, the MOS gate controlled thyristor mainly has three structures: a MOS control Thyristor (MOS Controlled Thyristor, MCT), a Base Resistance Controlled Thyristor (BRT) and an Emitter Switched Thyristor (EST), as shown in fig. 1 and 2, which are respectively a cross-sectional structure diagram and an output characteristic curve of the BRT, wherein the BRT device comprises three electrodes including an anode A, a cathode K and a grid G, when a forward bias is applied to the grid, an N-channel field effect transistor NMOS is Switched on, a P-channel field effect transistor PMOS is Switched off, and an NMOS current triggers the Thyristor structure to start internal positive feedback, so that the device is Switched on; when negative bias is applied to the grid electrode, the NMOS is turned off, the PMOS is turned on, and the PMOS extracts hole current of the P base region to destroy positive feedback in the thyristor and turn off the device. Due to the parasitic PNP triode of the device, the BRT works in an IGBT mode when the current is small, snap-back phenomenon exists in the output characteristic (as shown in figure 2), and besides, the PMOS is weak in turn-off capability, so that the BRT is slow in turn-off speed and large in turn-off power consumption.
Therefore, although compared with MCT, BRT and EST have the advantages of compatibility of the process and IGBT, the working state is switched from the IGBT mode to the thyristor mode in the starting process, strong conductance modulation occurs, the on resistance of the device is suddenly reduced, the output curve is snapback, the problem of inconsistent starting in the multi-cell device is caused, the performance of the device is limited, and the working reliability of the device is influenced.
Disclosure of Invention
The MOS grid-controlled thyristor provided by the invention can inhibit snapback phenomenon in the starting process of the base resistance control thyristor BRT and the emitter switch thyristor EST, thereby solving the problem of inconsistent starting of multiple cells and improving the working reliability of devices.
The invention provides an MOS grid-controlled thyristor, which comprises three electrodes of a cathode, a grid and an anode, wherein the grid comprises an NMOS (N-channel metal oxide semiconductor) and a PMOS (P-channel metal oxide semiconductor), and the MOS grid-controlled thyristor also comprises an N-P-N-P four-layer structure region P + The N-P-N-P four-layer structure region comprises an N + cathode region, a P base region, an N type drift region, an N + buffer layer and a P + anode region, wherein the N type drift region is close to the P type drift region + And an N-type buried layer is arranged in the diffusion region.
Optionally, the MOS gate controlled thyristor is a base resistance controlled thyristor BRT.
Optionally, the gate structure of the base resistance control thyristor BRT is a planar gate structure.
Optionally, the gate structure of the base resistance control thyristor BRT is a trench gate structure.
Optionally, the MOS-gated thyristor is an emitter-switched thyristor EST.
Optionally, the emitter switching thyristor EST is a single channel emitter switching thyristor.
Optionally, the emitter switching thyristor EST is a double-channel emitter switching thyristor
The MOS grid-controlled thyristor provided by the embodiment of the invention adopts an N-type buried layer structure, namely, an N-type drift region is close to P + Of diffusion regionsAn N-type buried layer is arranged in the region to form a strong hole barrier, so that hole current injected from the bottom anode can be effectively prevented from entering P + The diffusion region is used for inhibiting a parasitic triode, so that the starting speed of the thyristor structure can be increased to inhibit a snapback phenomenon existing in a common MOS grid-controlled thyristor.
Drawings
FIG. 1 is a cross-sectional view of a BRT in the prior art;
FIG. 2 is an output characteristic curve of the BRT;
FIG. 3 is a schematic structural diagram of a MOS-gated thyristor according to an embodiment of the invention;
FIG. 4 is a schematic diagram of hole current of a conventional MOS gated thyristor;
FIG. 5 is a schematic diagram showing the hole current of the MOS-gated thyristor according to the above embodiment;
FIG. 6 is a schematic diagram of the hole concentration in the P base region of the MOS-gated thyristor in the above embodiment;
FIG. 7 is a schematic diagram of the output characteristic curve of the MOS-gated thyristor in the above embodiment;
fig. 8 is a schematic structural diagram of a MOS-gated thyristor according to another embodiment of the invention;
fig. 9 is a schematic structural diagram of a MOS-gated thyristor according to another embodiment of the invention;
fig. 10 is a schematic structural diagram of a MOS-gated thyristor according to another embodiment of the invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The invention provides a MOS gate-controlled thyristor, as shown in FIG. 3, which is described by taking a base resistance controlled thyristor BRT as an example, wherein the gate structure of the BRT isPlanar gate structure, as can be seen from fig. 3, the base resistance controlled thyristor BRT with the planar gate structure comprises three electrodes of a cathode K, a gate G and an anode a, wherein the gate comprises an NMOS and a PMOS (as shown by the top dashed box in fig. 3), and the MOS gate controlled thyristor further comprises an N-P-N-P four-layer structure region and a P + And the diffusion region, wherein the N-P-N-P four-layer structure region includes an N + cathode region, a P base region, an N type drift region, an N + buffer layer, and a P + anode region (shown by a left dashed line frame in fig. 3), and an N type buried layer is disposed in a region (shown by a right dashed line frame in fig. 3, that is, a parasitic triode region) in the N type drift region, the region being close to the P + diffusion region.
Thus, when the gate G is forward biased, the NMOS is turned on, and an electron current is formed from N + The diffusion region flows into the N-type drift region and into the N below + Buffer layer, into N + The electron current of the buffer layer promotes P + Strong injection of holes occurs in the anode region, then the injected holes are diffused in the N-type drift region until the holes are collected by the reverse-biased PN junction and enter the P base region above the N-type drift region, and when the hole current in the P base region is large enough, the P base region and the N base region are enabled to be connected + The PN junction formed by the diffusion region is forward biased, so that the thyristor is turned on.
The MOS gate-controlled thyristor provided by the embodiment of the invention adopts an N-type buried layer structure, namely, an N-type drift region is close to P + An N-type buried layer is arranged in the diffusion region to form a strong hole barrier, so that hole current injected from the bottom anode can be effectively prevented from entering P + The diffusion region is used for inhibiting a parasitic triode, so that the starting speed of the thyristor structure can be increased to inhibit a snapback phenomenon existing in a common MOS grid-controlled thyristor.
The common MOS grid-controlled thyristor has parasitic triode structure and bottom P + Holes injected into the doped region of the anode region can be directly swept to the cathode K through the reverse-biased PN junction on the right side, the device works in an IGBT mode, as shown in figure 4, hole current distribution in the starting process of a common MOS grid-controlled thyristor is realized, and part of hole current is directly swept to the right side P + The diffusion region enters the cathode K. The MOS grid-controlled thyristor provided by the invention forms a strong hole barrier because the N-type buried layer structure is manufactured in the parasitic triode,can effectively prevent the hole current injected by the anode from entering the right side P + And the diffusion region is used for improving the hole current entering the P base region of the left thyristor so as to inhibit a parasitic triode structure and promote the starting of the thyristor. As shown in fig. 5, the N-type buried layer structure promotes the hole current to enter the P-base region, and increases the hole concentration in the P-base region of the thyristor (as shown in fig. 6), so that, compared with the ordinary MOS gate-controlled thyristor, the output characteristic curve of the MOS gate-controlled thyristor proposed by the present invention has no snapback phenomenon (as shown in fig. 7)
Optionally, as shown in fig. 8, the gate structure of the MOS control thyristor BRT is a trench gate structure, that is, the gate structure is implemented by using a trench process.
The invention provides a MOS gate-controlled thyristor, as shown in fig. 9, where an emitter switching thyristor EST is taken as an example for description, where the emitter switching thyristor EST is a single-channel emitter switching thyristor, as can be seen from fig. 9, the single-channel emitter switching thyristor includes three electrodes, namely a cathode K, a gate G, and an anode a, where the gate includes an NMOS and a PMOS, and the MOS gate-controlled thyristor further includes an N-P-N-P four-layer structure region and a P + The N-P-N-P four-layer structure region comprises an N + cathode region, a P base region, an N type drift region, an N + buffer layer and a P + anode region, wherein an N type buried layer is arranged in a region, close to the P + diffusion region, in the N type drift region.
The MOS gate-controlled thyristor provided by the embodiment of the invention adopts an N-type buried layer structure, namely, an N-type drift region is close to P + An N-type buried layer is arranged in the diffusion region to form a strong hole barrier, so that hole current injected from the bottom anode can be effectively prevented from entering P + The diffusion region is used for inhibiting a parasitic triode, so that the starting speed of the thyristor structure can be increased to inhibit a snapback phenomenon existing in a common MOS grid-controlled thyristor.
Optionally, as shown in 10, the EST is a double channel emitter switched thyristor. The double-channel emitter switch thyristor comprises three electrodes of a cathode K, a grid G and an anode A, wherein the grid comprises an NMOS and a PMOS, the MOS grid controlled thyristor further comprises an N-P-N-P four-layer structure region and a P + A diffusion region of N-P-N-P four-layer structureThe region comprises an N + cathode region, a P base region, an N type drift region, an N + buffer layer and a P + anode region, wherein the N type drift region is close to the P + And an N-type buried layer is arranged in the diffusion region.
The above description is only for the specific embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (7)
1. The MOS gate-controlled thyristor is characterized by comprising three electrodes, namely a cathode, a grid and an anode, wherein the grid is an NMOS grid and a PMOS grid, the MOS gate-controlled thyristor further comprises an N-P-N-P four-layer structure region and a P + diffusion region, the N-P-N-P four-layer structure region comprises an N + cathode region, a P base region, an N type drift region, an N + buffer layer and a P + anode region, an N type buried layer is arranged in a region, close to the P + diffusion region, in the N type drift region, and the N type buried layer is located under the P + diffusion region.
2. The MOS-gated thyristor according to claim 1, wherein the MOS-gated thyristor is a base resistance controlled thyristor, BRT.
3. The MOS-gated thyristor of claim 2, wherein the gate structure of the base resistance controlled thyristor BRT is a planar gate structure.
4. The MOS-gated thyristor according to claim 2, wherein the gate structure of the base resistance-controlled thyristor BRT is a trench gate structure.
5. The MOS-gated thyristor according to claim 1, wherein the MOS-gated thyristor is an emitter-switching thyristor EST.
6. A MOS-gated thyristor according to claim 5, characterized in that the emitter-switched thyristor EST is a single-channel emitter-switched thyristor.
7. A MOS-gated thyristor according to claim 5, characterized in that the emitter-switched thyristor EST is a double-channel emitter-switched thyristor.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201811525422.5A CN109616518B (en) | 2018-12-13 | 2018-12-13 | MOS grid-controlled thyristor |
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| CN113437143B (en) * | 2021-06-25 | 2023-05-02 | 电子科技大学 | Three-dimensional MOS gate-controlled thyristor with parasitic diode and manufacturing method thereof |
| CN113809167B (en) * | 2021-08-10 | 2024-01-09 | 西安理工大学 | BRT with buried layer and manufacturing method thereof |
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| JP3371836B2 (en) * | 1999-01-28 | 2003-01-27 | 株式会社豊田中央研究所 | Semiconductor device |
| JP2001284574A (en) * | 2000-03-30 | 2001-10-12 | Toshiba Corp | Semiconductor device having insulation gate |
| US7667268B2 (en) * | 2002-08-14 | 2010-02-23 | Advanced Analogic Technologies, Inc. | Isolated transistor |
| US7285828B2 (en) * | 2005-01-12 | 2007-10-23 | Intersail Americas Inc. | Electrostatic discharge protection device for digital circuits and for applications with input/output bipolar voltage much higher than the core circuit power supply |
| US10205017B2 (en) * | 2009-06-17 | 2019-02-12 | Alpha And Omega Semiconductor Incorporated | Bottom source NMOS triggered Zener clamp for configuring an ultra-low voltage transient voltage suppressor (TVS) |
| US8482031B2 (en) * | 2009-09-09 | 2013-07-09 | Cambridge Semiconductor Limited | Lateral insulated gate bipolar transistors (LIGBTS) |
| CN102157551A (en) * | 2011-03-10 | 2011-08-17 | 电子科技大学 | IGBT with current carrier storage layer and additional hole passage |
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