JP3371836B2 - Semiconductor device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a MOS element.

[0002]

BACKGROUND ART For example, in a MOS thyristor in which a MOSFET and a thyristor structure are combined, electrons are supplied from a cathode to a floating emitter region by using a MOS gate, and holes are further injected from an anode to a base region. As a result, the thyristor operation is performed inside the element.

FIG. 11 shows an example of a conventional MOS thyristor. This MOS thyristor has ap ⁺ type emitter layer 1
0, n ⁺ type buffer layer 12, n ⁻ type base region 14, p ⁻
It has a type base region 16, a floating emitter region 22 and an n ⁺ type impurity diffusion layer 18. Further, a gate electrode 30 is formed on the surface of the n ⁺ type impurity diffusion layer 18 and the p ⁻ type base region 16 which function as a source region or an emitter region, with a gate insulating layer 32 interposed therebetween. The gate electrode 30 drives the MOS gate to control the operation of the thyristor. That is, n
⁺ Type impurity diffusion layer (source region) 18, first channel region 20a, floating emitter region 22, second channel region 20b, n ⁻ type base region 14, n ⁺ type buffer layer 12 and p ⁺ type emitter layer 10 An IGBT for thyristor operation is constituted by.

In this MOS thyristor,
When the switch is in the operating state, n ⁺Type floating
P from the emitter region 22^-Elect to mold base area 16
Ron injection occurs and at the same time p⁺From the emitter layer 10
n^-P through the mold base region 14^-To mold base area 16
Infusion of the le occurs. However, in the device of this structure
Is n when the high injection state is reached.⁺Type emitter region 1
8, p^-Mold base region 16, n^-Mold base region 14, n⁺
Type buffer layer 12 and p⁺Formed by emitter layer 10
When the parasitic thyristor latches up, the MOS gate is controlled.
Function is lost and the thyristor cannot be turned off.
It Therefore, prevent latch-up of parasitic thyristor.
In order to reduce the p-type base region 17 just below the cathode electrode 50,
Or increase the diffusion depth.
Combing is done. However, the parasitic thyristor
Base just below the cathode electrode to prevent chill-up
Increasing the impurity concentration in the region complicates the process.
It is also possible to increase the connection depth and the diffusion depth sufficiently.
Safe operating area
Becomes narrower and the on-voltage becomes higher.

An object of the present invention is to provide a MOS having a low on-voltage.
It is to provide a semiconductor device including an element.

[0006]

A semiconductor device according to the present invention is a semiconductor device in which formation or non-formation of a channel in a channel region is controlled by a voltage applied to an insulated gate, the semiconductor device being in contact with the channel region and being in contact with the source region. A semiconductor layer functioning as, and at least an embedded insulating layer formed to face the gate insulating layer at or near an end of the channel region and the semiconductor layer or in the vicinity thereof,
And a trench gate is formed in at least the channel region in a direction along the current path.

The channel region is formed of a semiconductor layer of either the first or second conductivity type depending on the structure of the device.

According to this semiconductor device, the effective area of the MOS gate in the channel region can be increased by forming the trench gate in at least the channel region in the direction along the current path, and as a result, the channel resistance can be increased. It can be reduced and the on-voltage can be reduced.
This effect is common to the semiconductor device according to the present invention.
Further, by forming the buried insulating layer, when there is a parasitic thyristor including the semiconductor layer functioning as a source region, the latch-up operation can be prevented.

The semiconductor device of the present invention can take the following modes, for example.

(A) A semiconductor device comprises a first conductive type first semiconductor layer, a second conductive type second semiconductor layer formed on one main surface side of the first semiconductor layer, and the second semiconductor layer. A third semiconductor layer of the first conductivity type selectively formed on the surface of the second semiconductor layer, a fourth semiconductor layer of the second conductivity type selectively formed on the surface of the third semiconductor layer, and the fourth semiconductor layer A fifth semiconductor layer that is in contact with the third semiconductor layer and can form a channel region, and a fifth semiconductor layer is interposed between the fifth semiconductor layer and the third semiconductor layer, and the fifth semiconductor layer is formed separately from the fourth semiconductor layer. A second conductivity type sixth semiconductor layer, at least a gate electrode formed on the surface of the fifth semiconductor layer via a gate insulating layer, and inside the third semiconductor layer, and at least the fourth semiconductor layer; Ends of the semiconductor layer and the fifth semiconductor layer on the side of the first semiconductor layer or in the vicinity thereof. The embedded insulating layer formed on the first semiconductor layer, the first main electrode formed on the surfaces of the third semiconductor layer and the fourth semiconductor layer, and the second main surface formed on the other main surface side of the first semiconductor layer. A trench gate including a main electrode is formed in at least the fifth semiconductor layer in a direction along the current path.

In this semiconductor device, the fourth semiconductor layer that functions as a source region, the fifth semiconductor layer that can form a channel region, the drain region, and the sixth semiconductor layer that functions as a floating emitter region are used to form a MOS.
A transistor is formed. A thyristor is formed by the first, second, third and sixth semiconductor layers.

According to this semiconductor device, the effective area of the MOS gate in the channel region can be increased by forming the trench gate in at least the channel region in the direction along the current path, and as a result, the channel resistance can be increased. It can be reduced and the on-voltage can be reduced.

In this semiconductor device, the cathode electrode is formed by forming the buried insulating layer at or near the end of the fifth semiconductor layer capable of forming the fourth semiconductor layer functioning as the source region or the emitter region and the channel region. It is possible to prevent the latch-up operation of the parasitic thyristor existing immediately below the first main electrode functioning as. That is, in the lower end region of the fifth semiconductor layer capable of forming the fourth semiconductor layer functioning as the source region or the emitter region and the channel region, preferably in a state of traversing the operating region (parallel to the main surface of the first semiconductor layer). By forming the buried insulating layer (in the direction), the fourth insulating layer and the fifth semiconductor layer are formed by the buried insulating layer even in a high injection state in which a voltage is applied to the second main electrode functioning as an anode electrode. Since the layer and the second semiconductor layer are electrically separated, the operation of the parasitic thyristor formed under the first main electrode is suppressed. As a result, the on / off operation can be performed more reliably as compared with the device having the conventional structure.

(B) The semiconductor device includes a first conductivity type first semiconductor layer, a second conductivity type second semiconductor layer formed on one main surface side of the first semiconductor layer, and a second semiconductor layer. A first conductive type third semiconductor layer selectively formed on a surface portion, a second conductive type fourth semiconductor layer selectively formed on a surface portion of the third semiconductor layer, and a fourth semiconductor layer, A fifth semiconductor layer which is in contact with and can form a channel region, at least a gate electrode formed on the surface of the fifth semiconductor layer via a gate insulating layer, and inside the third semiconductor layer, and at least A buried insulating layer formed at or near the ends of the fourth semiconductor layer and the fifth semiconductor layer on the first semiconductor layer side, and formed on the surfaces of the third semiconductor layer and the fourth semiconductor layer. A first main electrode and the other main electrode of the first semiconductor layer It includes a second main electrode, which is formed on the side, at least the fifth semiconductor layer, and a trench gate is formed in a direction along the current path.

This semiconductor device has a fourth semiconductor layer functioning as a source region and an emitter region and a fifth semiconductor layer capable of forming a channel region. Also,
By the first, second, third, fifth and fourth semiconductor layers I
A GBT (Insulated Gate Bipolor Transistor) is formed.

According to this semiconductor device, the effective area of the MOS gate in the channel region can be increased by forming the trench gate in at least the channel region in the direction along the current path, and as a result, the channel resistance can be increased. It can be reduced and the on-voltage can be reduced.

In this semiconductor device, a buried insulating layer is formed at or near the end of the fourth semiconductor layer functioning as an emitter region and the fifth semiconductor layer capable of forming a channel region, thereby functioning as a cathode electrode. It is possible to prevent the latch-up operation of the parasitic thyristor existing immediately below the first main electrode. That is, in the lower end region of the fourth semiconductor layer functioning as an emitter region and the fifth semiconductor layer capable of forming a channel region, preferably in a state of traversing the operation region (in a direction parallel to the main surface of the first semiconductor layer). By forming the buried insulating layer, the buried insulating layer allows the fourth semiconductor layer and the fifth semiconductor layer to be connected to the second main electrode functioning as an anode electrode even when a high voltage is applied. Since the two semiconductor layers are electrically separated, the operation of the parasitic thyristor formed below the first main electrode is suppressed. As a result, the on / off operation can be performed more reliably as compared with the device having the conventional structure.

(C) The semiconductor device comprises a second conductive type first semiconductor layer, a second conductive type second semiconductor layer formed on one main surface side of the first semiconductor layer, and the second semiconductor layer. A third semiconductor layer of the first conductivity type selectively formed on the surface of the second semiconductor layer, a fourth semiconductor layer of the second conductivity type selectively formed on the surface of the third semiconductor layer, and the fourth semiconductor layer A fifth semiconductor layer that is in contact with a channel region and can form a channel region, at least a gate electrode formed on the surface of the fifth semiconductor layer via a gate insulating layer, and inside the third semiconductor layer, and At least the fourth semiconductor layer and the fifth semiconductor layer,
A buried insulating layer formed at or near the end of the first semiconductor layer side, a first main electrode formed on the surfaces of the third semiconductor layer and the fourth semiconductor layer, and the first
A trench gate is formed in at least the fifth semiconductor layer in a direction along the current path, including a second main electrode formed on the other main surface side of the semiconductor layer.

This semiconductor device has a second conductivity type first semiconductor layer in place of the first conductivity type first semiconductor layer of the semiconductor device of (B). That is, this semiconductor device has a fourth semiconductor layer that functions as a source region, a fifth semiconductor layer that can form a channel region, and a first semiconductor layer that functions as a drain region,
Configure a MOSFET.

According to this semiconductor device, by forming the trench gate in at least the channel region in the direction along the current path, the effective area of the MOS gate in the channel region can be increased, and as a result, the channel resistance can be increased. It can be reduced and the on-voltage can be reduced.

In the present invention, the trench gate may be formed not only in the channel region but also in a part or the whole of the region where the gate insulating layer and the gate electrode are formed. In the region where the trench gate is formed, a low resistance accumulation region is formed, and the on-voltage of the device can be reduced.

Further, in any of the semiconductor devices according to the present invention, it is desirable that a buried electrode be formed in the buried insulating layer. Then, when the element is turned off, by applying a predetermined potential to the embedded electrode, the parasitic channel region existing on the surface of the embedded insulating layer operates due to the rise of the anode potential (the potential of the second main electrode). Can be prevented, and the element can be turned off more reliably.

The semiconductor device of the present invention can be applied to a device having a MOS gate, and a MOS gate thyristor, I
In addition to the GBT, it can be applied to a power MOSFET and the like.

[0024]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS (First Embodiment) FIG. 1 is a sectional view schematically showing a thyristor 100 (MOS gate thyristor) 100 controlled by a MOS gate to which the present invention is applied. 3 is a perspective view showing a main part of the MOS gate thyristor 100 of FIG. 1, and FIG.
It is sectional drawing which shows the part along the -A line.

(Structure) This MOS gate thyristor 10
0, the p ⁺ type anode layer (first semiconductor layer) 10 functioning as an emitter region made of a low resistance semiconductor substrate
An n ⁺ type buffer layer 12 is formed on one main surface of
An n ⁻ type base region (second semiconductor layer) 14 that functions as a drift layer is formed on the surface of the buffer layer 12. A p ⁻ -type base region (third semiconductor layer) 16 is formed on the surface of the n ⁻ -type base region 14, and an n ⁺ -type impurity diffusion layer (functioning as a source region of the MOSFET) is formed in the base region 16. A fourth semiconductor layer) 18 is selectively formed. Further, an n ⁺ type floating emitter region (sixth semiconductor layer) 22 is selectively formed on the surface portion of the p ⁻ type base region 16 at a position apart from the n ⁺ type impurity diffusion layer 18. .

This n ⁺ type floating emitter region 2
2 denotes a first floating emitter region 22a formed on the surface of the p ⁻ type base region 16 and the first floating emitter region 22a.
Second floating emitter region 22b which is continuous with the lower end of the floating emitter region 22a and extends in a direction parallel to the main surface of the p ⁺ -type anode layer 10.
It consists of and.

A first channel region (fifth semiconductor layer) 20a is formed in the p ⁻ type base region 16 between the n ⁺ type impurity diffusion layer 18 and the floating emitter region 22, and the n ⁺ type floating region is formed. Emitter region 22 and n ⁻
A second channel region 20b is formed in the p ⁻ type base region 16 between the type base region 14 and the p ⁻ type base region. Also,
A p ⁺ type base region 17 is formed outside the n ⁺ type impurity diffusion layer 18 as necessary to prevent the parasitic thyristor from latching up more reliably.

The n ⁺ -type impurity diffusion layer 18, the first channel region 20a and the first floating emitter region 22a are partially in contact with the lower end portions of the p ⁺ -type anode in a state of being substantially in contact with these regions. A buried insulating layer 70 is formed in a direction parallel to the main surface of the layer 10. That is, the first channel region 20 a is partitioned by the n ⁺ type impurity diffusion layer 18, the floating emitter region 22 and the buried insulating layer 70.

Then, on the surfaces of the n ⁺ type impurity diffusion layer 18, the first channel region 20a, the n ⁺ type floating emitter region 22, and the second channel region 20b,
The gate electrode 30 is formed via the gate insulating layer 32.

In this embodiment, FIG. 2 and FIG.
As shown in an enlarged view, the region G100 including the first channel region 20a, specifically, the first channel region 20a.
And a plurality of trench gates 34 are formed in a region G100 including the n ⁺ -type impurity diffusion layer 18 and a part of the floating emitter region 22. These trench gates 34 are formed along a current path I _CH that flows through the n ⁺ type impurity diffusion layer 18, the first channel region 20 a and the floating emitter region 22. The trench gate 34 is continuous with the gate insulating layer 32 and is formed along the trench, and the trench gate insulating layer 320 is continuous with the gate electrode 30, and the conductive layer formed in the trench via the trench gate insulating layer 320. And 300.

Further, as shown in FIG. 1, a cathode electrode 50 as a first main electrode is formed on the surfaces of the n ⁺ type impurity diffusion region 18 and the p ⁺ type base region 17. An anode electrode 60, which is a second main electrode, is formed on the other main surface of the p ⁺ type anode layer 10.

In this MOS gate thyristor 100, the n ⁺ -type floating emitter region 22, the p ⁻ -type base region 16, the n ⁻ -type base region 14, the n ⁺ -type buffer layer 12 and the p ⁺ -type anode layer 10 allow the npnp thyristor. Is configured.

The n ⁺ type impurity diffusion layer (source region)
18, first channel region 20a, n ⁺ type floating emitter region 22, second channel region 20b, n ⁻
The type base region 14, the n ⁺ type buffer layer 12, and the p ⁺ type anode layer (emitter region) 10 form an IGBT.

(Operation) Next, the MOS according to the present embodiment
The operation of the gate thyristor 100 will be described.

First, the gate electrode 30 and the anode electrode 60
The IGBT is operated by applying a predetermined positive voltage to and. In the operation of the IGBT, electrons are n ⁺
From the type impurity diffusion layer 18 to the n ⁺ type floating emitter 22 via the first channel region 20a, further to the accumulation region formed along the gate insulating layer 32 of the floating emitter region 22, and then to the second Flowing into the n ⁻ type base region 14 through the channel region 20b of At the same time, since a positive voltage is applied to the anode electrode 60, holes are transferred from the p ⁺ -type anode layer 10 through the n ⁺ -type buffer layer 12 to the n ⁻ -type base region 1.
It flows into 4. In this way, the n ⁻ type base region 1
4 is filled with electrons and holes, IGB
T becomes the operation mode.

Then, in the region G100 including the first channel region 20a, the trench gate 34 is formed along the current path.
By providing, the channel region can be formed around the trench gate 34, specifically, along the upper surface, the side surface, and the bottom surface of the trench gate 34. As a result, the channel region can be dramatically increased as compared with the conventional planar insulated gate. As a result, the channel resistance can be reduced and the on-voltage can be reduced.

Furthermore, by increasing the voltage of the anode electrode 60, holes injected from the p ⁺ -type anode layer 10 is p ^- flows into -type base region 16, the p ^- resistance type base region 16 becomes lower. As a result, the p ⁺ type anode layer 10, the n ⁺ type buffer layer 12, the n ⁻ type base region 1
4, the pnpn thyristor composed of the p ⁻ type base region 16 and the n ⁺ type floating emitter region 22 is in the latch-up state, causing the thyristor operation.

Thus, the IGBT functions as a trigger for causing the thyristor operation. And IG
Since the MOSFET portion of BT is formed along the gate electrode 30 which also functions as the gate of the thyristor,
Injection of holes from the p ⁺ -type anode layer 10 can be more easily promoted, and a thyristor having a short turn-on time and capable of controlling a large current can be realized.

In the case where the thyristor and the IGBT are formed in different regions by forming the floating emitter region 22 of the thyristor on the surface of the element and further forming the IGBT operation region using the floating emitter region 22. In comparison, the chip area can be effectively used.

Further, in the MOS gate thyristor 100, the second floating emitter region 22b is formed so as to extend along the main surface direction of the p ⁺ type anode layer 10, so that the electron injection path should be widened. The ON voltage can be reduced.

When turning off the MOS gate thyristor 100, by turning off the gate electrode 30, the n ⁺ type floating emitter region 22 is electrically cut off from the cathode electrode 50, and the thyristor operation is stopped.

The first feature of this embodiment is that n functions as a source region and a cathode region.
⁺ Type impurity diffusion layer 18 and first channel region 20a
Embedded insulating layer 7 in the lower end region of the device across the operating region.
To form 0. In other words, the buried insulating layer 70 allows the n ⁺ -type impurity diffusion layer 18 and the first channel region 20 a and the n ⁻ -type base region 14 to be separated even if the voltage is applied to the anode electrode 60 in a high implantation state. Since they are electrically separated, the operation of the parasitic thyristor formed under the cathode electrode 50 is suppressed. as a result,
The on / off operation can be performed more reliably than the element having the conventional structure.

Second, by forming a plurality of trench gates 34 in the region G100 including the first channel region 20a, the effective area of the MOS gate in the first channel region 20a can be increased. as a result,
The channel resistance can be reduced and the on-voltage can be reduced.

(Second Embodiment) FIG. 4 is a sectional view schematically showing a thyristor 200 (MOS gate thyristor) 200 to which the present invention is applied and which is controlled by a MOS gate, and FIG. 5 is shown in FIG. It is sectional drawing which expands and shows the part along the BB line. This MOS gate thyristor 2
00 is the MOS gate thyristor 1 of the first embodiment.
00, and is different from the MOS gate thyristor 100 in that the buried electrode 80 is formed inside the buried insulating layer 70. In this embodiment, FIG.
˜The same reference numerals are given to the substantially same parts as those of the MOS gate thyristor 100 of the first embodiment shown in FIG. 3, and the detailed description thereof will be omitted.

In the present embodiment, the buried insulating layer 7
A buried electrode 80 is formed inside 0. The embedded electrode 80 is connected to an external terminal by a conductive portion (not shown). By forming such a buried electrode 80, it is possible to surely turn off the element.

That is, when the MOS gate thyristor 200 is turned off, the gate electrode 30 is turned off so that the n ⁺ type floating emitter region 2 is formed.
2 is cut off in potential from the cathode electrode 50, and the thyristor operation stops.

The characteristic feature of this embodiment is that
When turning off the MOS gate thyristor 200, by applying a predetermined potential, that is, a negative or zero potential to the buried electrode 80, even if the potential of the second floating emitter region 22b rises due to the rise of the anode potential, The influence is not given to the buried insulating layer 70. As a result, the parasitic channel region (back channel) formed on the surface of the buried insulating layer 70 can be prevented from operating by the anode potential, and the element can be turned off more reliably. This embedded electrode 8
0 may be formed over a wide range not only in the pn junction formed by the first channel region 20a and the n ⁺ type floating emitter region 22 but also over the first channel region 20a and the p ⁺ type base region 17. .

The other structure and operation of the present embodiment are the same as those of the first embodiment, and detailed description thereof will be omitted. Further, it goes without saying that the embedded electrode 80 which is a feature of this embodiment can be applied to other embodiments.

(Third Embodiment) FIG. 6 is a sectional view schematically showing a main part of a thyristor (MOS gate thyristor) 300 controlled by a MOS gate to which the present invention is applied, and FIG. Equivalent to. This MOS gate thyristor 300 has basically the same structure as the MOS gate thyristor 100 of the first embodiment, and has a structure in which a buried electrode 80 is formed inside the buried insulating layer 70 and a trench gate structure. It is different from the MOS gate thyristor 100 in the point. In this embodiment, FIGS.
MOS gate thyristor 10 of the first embodiment shown in FIG.
Portions substantially the same as 0 are designated by the same reference numerals, and detailed description thereof will be omitted.

In the present embodiment, the plurality of trench gates 34 formed in the region G100 including the first channel region 20a are in contact with the buried insulating layer 70. Specifically, trench gate 34 has a trench extending from the surface to buried insulating layer 70 in first channel region 20a. The trench gate 34 is continuous with the gate insulating layer 32, is formed along the trench, and is continuous with the gate electrode 30, and is formed in the trench through the trench gate insulating layer 320. And layer 300. in this way,
Since the trench gate 34 is formed in contact with the buried insulating layer 70, the first channel region 20a is
Since it is surrounded by insulating layers on all sides, it is a fully depleted type. Therefore, the trench gate is buried in the insulating layer 7
The difference is that the entire first channel region 20a can operate as a channel by applying a gate voltage to a semiconductor device of a type not in contact with 0 (for example, the semiconductor device 100 or 200).

In the semiconductor device 300 of the present embodiment, the example in which the embedded electrode 80 is formed in the embedded insulating layer 70 has been described, but the same can be applied to other embodiments of the type having no embedded electrode. Further, the function and effect of the buried electrode are similar to those of the semiconductor device 200 of the second embodiment, and therefore detailed description thereof will be omitted.

(Fourth Embodiment) FIG. 7 is a sectional view schematically showing a thyristor 400 controlled by a MOS gate (MOS gate thyristor) to which the present invention is applied. This MOS gate thyristor 400 has a first
The MOS gate thyristor 100 of the present embodiment has basically the same configuration, and is different from the MOS gate thyristor 100 in the formation region of the trench gate. In this embodiment, the MO of the first embodiment shown in FIGS.
Portions substantially the same as those of the S gate thyristor 100 are designated by the same reference numerals, and detailed description thereof will be omitted.

In this embodiment, the trench gate 34
Is formed not only over the first channel region 20a but also over substantially the entire region G200 of the formation region of the gate insulating layer 32 and the gate electrode 30. in this way,
By forming the trench gate 34 in a wide range,
First, the effective area of the MOS gate in the first channel region 20a and the second channel region 20b can be increased, and as a result, the channel resistance can be reduced. Secondly, the region other than the channel regions 20a and 20b can be reduced. In the (floating emitter region 22 and the n − type base region 14), a low resistance accumulation region is formed, and these effects can reduce the on-voltage of the device.

The region where the trench gate 34 is formed is
Although not limited to the region shown in FIG. 7, although not shown, in addition to the first channel region 20a, the n ⁺ -type impurity diffusion layer 18,
The floating emitter region 22, the second channel region 20b and the n − type base region 14 can be formed entirely or partially.

The other structure and operation of this embodiment are the same as those of the first embodiment, and therefore detailed description thereof will be omitted. Further, it goes without saying that the formation region of the trench gate, which is a feature of this embodiment, can be applied to other embodiments other than the first embodiment.

(Fifth Embodiment) FIG. 8 is a sectional view schematically showing an IGBT 500 having a MOS gate to which the present invention is applied, and FIG. 9 is taken along line CC of FIG. It is sectional drawing which expands and shows a part.

(Structure) In this IGBT 500,
On one main surface of the p ⁺ type anode layer (first semiconductor layer) 10 that functions as a collector region made of a low resistance semiconductor substrate, n ^{+ that} also functions as a drain region of the MOSFET.
The type buffer layer 12 is formed, and an n ⁻ type base region (second semiconductor layer) 14 that functions as a drift layer is formed on the surface of the buffer layer 12. A p ⁻ type base region (third semiconductor layer) 16 is formed on the surface of the n ⁻ type base region 14, and a MOS is formed in the base region 16.
An n ⁺ type impurity diffusion layer (fourth semiconductor layer) 18 functioning as a source region of the FET is selectively formed.

A channel region (fifth semiconductor layer) 2 is formed in the p ⁻ type base region 16 in contact with the n ⁺ type impurity diffusion layer 18.
0 is formed. In addition, the n ⁺ -type impurity diffusion layer 1
If necessary, a p ⁺ -type base region 1 is provided on the outer side of 8 to more securely prevent latch-up of the parasitic thyristor.
7 are formed.

At the lower end portions of the n ⁺ type impurity diffusion layer 18 and the channel region 20, a buried insulating layer is provided in a state of being in contact with these regions and in a direction parallel to the main surface of the p ⁺ type anode layer 10. 70 is formed. And n
^A gate electrode 30 is formed on the surfaces of the ⁺ type impurity diffusion layer 18 and the channel region 20 via a gate insulating layer 32.

In the present embodiment, n ⁺ type impurity diffusion layer 18, channel region 20 and n ⁻ type base region 1 are formed.
A plurality of trench gates 34 are formed in a region G300 including a part of No. 4. These trench gates 34
_Are formed along the current path I _CH in the n ⁺ -type impurity diffusion layer 18 and the channel region 20. As shown in FIG. 9, the trench gate 34 is continuous with the gate electrode 30 and the trench gate insulating layer 320 that is continuous with the gate insulating layer 32 and is formed along the trench. Conductive layer 3 formed inside
00 and 00.

Further, as shown in FIG. 8, a cathode electrode 50 as a first main electrode is formed on the surfaces of the n ⁺ type impurity diffusion region 18 and the p ⁺ type base region 17. An anode electrode 60, which is a second main electrode, is formed on the other main surface of the p ⁺ type anode layer 10.

This IGBT 500 has an n ⁺ type impurity diffusion layer 18, a channel region 20, an n ⁻ type base region 14, and an n ⁺ type region.
It is composed of the type buffer layer 12 and the p ⁺ type anode layer 10.

(Operation) IGB according to the present embodiment
The operation of T500 will be described.

First, the gate electrode 30 and the anode electrode 60
The IGBT is operated by applying a predetermined positive voltage to and. In the operation of the IGBT, electrons are n ⁺
It flows from the type impurity diffusion layer 18 into the n ⁻ type base region 14 through the channel region 20. At the same time, the anode electrode 60
Since a positive voltage is applied to the holes, holes flow from the p ⁺ type anode layer 10 to the n ⁻ type base region 14 through the n ⁺ type buffer layer 12. In this way, the n ⁻ type base region 14 is filled with electrons and holes, and
The GBT is in the operating mode.

A region G3 including the channel region 20
By providing the trench gate 34 along the current path at 00, the channel region can be formed around the trench gate 34, specifically, along the upper surface, the side surface, and the bottom surface of the trench gate 34. As a result, the channel region can be dramatically increased as compared with the conventional planar insulated gate. As a result, the channel resistance can be reduced and the on-voltage can be reduced.

When the IGBT 500 is turned off, the operation is stopped by turning off the gate electrode 30.

The feature of this embodiment is that, firstly, n which functions as a source region and a cathode region.
^The buried insulating layer 70 is formed in the lower end regions of the ⁺ type impurity diffusion layer 18 and the channel region 20 so as to cross the operation region. That is, the embedded insulating layer 70
Even in the high implantation state in which a voltage is applied to the anode electrode 60, the n ⁺ type impurity diffusion layer 18 and the channel region 20 and the n ⁻ type base region 14 are electrically separated from each other. The operation of the parasitic thyristor formed below is suppressed. As a result, the on / off operation can be performed more reliably as compared with the device having the conventional structure.

Second, the region G3 including the channel region 20
By forming a plurality of trench gates 34 in the channel region 00, the effective area of the MOS gate in the channel region 20 can be increased, and as a result, the channel resistance can be reduced. Further, a region other than the channel region 20 (n-
In a part of the mold base region 14, a low resistance accumulation region is formed along the gate insulating layer 32. These effects can reduce the on-voltage of the device.

(Sixth Embodiment) FIG. 12 is a sectional view schematically showing a MOSFET 600 to which the present invention is applied. This MOSFET 600 is the IGBT shown in FIG.
Instead of the collector region (first semiconductor layer) 10 of 500, an n ⁺ type drain region 11 is formed. Portions substantially similar to those shown in FIG. 8 are designated by the same reference numerals, and detailed description thereof will be omitted.

In this MOSFET 600, n ⁻ type drift layer (second semiconductor layer) 14 is formed on drain region (first semiconductor layer) 11. A p ⁻ type base region (third semiconductor layer) 16 is formed on the surface of the drift layer 14, and an n ⁺ type impurity diffusion layer (fourth semiconductor layer) that functions as a source region is formed in the base region 16. 18 are selectively formed. A channel region (fifth semiconductor layer) 20 is formed in the p ⁻ type base region 16 in contact with the n ⁺ type impurity diffusion layer 18.

At the lower end portions of the n ⁺ -type impurity diffusion layer 18 and the channel region 20, in a state of being in contact with these regions and in a direction parallel to the main surface of the drain region (first semiconductor layer) 11, A buried insulating layer 70 is formed. A gate electrode 30 is formed on the surfaces of the n ⁺ type impurity diffusion layer 18 and the channel region 20 with a gate insulating layer 32 interposed therebetween.

In the present embodiment, n ⁺ type impurity diffusion layer 18, channel region 20 and n ⁻ type drift layer 1 are formed.
A plurality of trench gates similar to that shown in FIG. 9 are formed in a region G300 including a part of the trench 4. These trench gates 34 are formed along the current path I _CH in the n ⁺ type impurity diffusion layer 18 and the channel region 20.

The on / off operation of the MOSFET 600 is
Since it is similar to a general MOSFET, its description is omitted. MO
In the SFET 600, the region G3 including the channel region 20
By providing the trench gate 34 along the current path at 00, the channel region can be formed around the trench gate 34, specifically, along the upper surface, the side surface, and the bottom surface of the trench gate 34. As a result, the effective area of the channel region can be dramatically increased as compared with the planar insulated gate having the conventional structure. As a result, the channel resistance can be reduced and the on-voltage can be reduced. further,
In a region other than the channel region 20 (a part of the n − type drift layer 14), a low resistance accumulation region is formed along the gate insulating layer 32. These effects can reduce the on-voltage of the device.

(Method for Forming Buried Insulating Layer) In the present invention, the method for forming the buried insulating layer 70 is not particularly limited, but a typical manufacturing method will be described below. The semiconductor layer including the buried insulating layer is an SOI (Silicon O
n Insulator) technology.

FIG. 10A shows a first technique for manufacturing an SOI substrate.
FIG. 10B is a diagram showing a method of burying an embedded insulating layer using a bonding method, and FIG. 10B is a diagram showing a method of burying an embedded insulating layer using a SIMOX method (oxygen ion implantation method). FIG. 10C is a diagram showing a method of forming a buried insulating layer using the SPE method (recrystallization method).

When the bonding method of FIG. 10A is used, the partially processed Si substrate 110 and the silicon substrate 210 having a recess in the center are bonded together while being heat-treated in an oxygen gas atmosphere. As a result, the SOI substrate 31 in which the embedded insulating layer (SiO ₂ film) 510 is embedded
Form 0.

That is, the heat treatment in the oxygen gas atmosphere promotes the oxidation of silicon in the central recess portion, so that S
An iO ₂ film 510 is formed. Since the volume of silicon expands due to oxidation, the generated SiO ₂ film 5
10 fills the recessed portion. by this,
SO with embedded insulating layer (SiO ₂ film) 510 embedded
The I substrate 310 is obtained.

When the SIMOX method of FIG. 10B is used, the mask material 140 is formed on the silicon substrate 120,
After selectively implanting oxygen ions and removing the mask material 140, the heat treatment activates the oxygen ions, so that the embedded insulating layer (SiO 2) embedded in the silicon substrate 120 is removed.
₂ film) 510 is formed.

When the SPE method (recrystallization method) of FIG. 10C is used, the buried insulating layer 510 is selectively formed on the silicon substrate 140, and the polycrystalline silicon layer 160 is formed.
Is formed, and then heat treatment is performed to form a polycrystalline silicon layer 16
0 is recrystallized to form an SOI substrate 140 in which a buried insulating layer (SiO ₂ film) 510 is buried.

In the above embodiment, the first conductivity type is p
Although the n-type semiconductor device has been described as the first and second conductivity types, the conductivity type may be the opposite.

[Brief description of drawings]

FIG. 1 is a sectional view schematically showing a MOS gate thyristor according to a first embodiment of the present invention.

FIG. 2 is a perspective view of a main part of the MOS gate thyristor shown in FIG.

3 is a cross-sectional view taken along the line AA of the MOS gate thyristor shown in FIG.

FIG. 4 is a sectional view schematically showing a MOS gate thyristor according to a second embodiment of the present invention.

5 is a sectional view taken along line BB of the MOS gate thyristor shown in FIG.

FIG. 6 is a sectional view schematically showing a main part of a MOS gate thyristor according to a third embodiment of the present invention.

FIG. 7 is a sectional view schematically showing a MOS gate thyristor according to a fourth embodiment of the present invention.

FIG. 8 is a sectional view schematically showing an IGBT according to a fifth embodiment of the present invention.

9 is a cross-sectional view taken along the line CC of the IGBT shown in FIG.

10 (a), (b) and (c) are diagrams showing an example of means for forming a buried insulating layer in a semiconductor layer.

FIG. 11 is a sectional view schematically showing a conventional MOS gate type semiconductor device.

FIG. 12 is a MOSFE according to a sixth embodiment of the present invention.
It is sectional drawing which shows T typically.

[Explanation of symbols]

10 p ⁺ type silicon substrate (p ⁺ type anode layer) 11 drain region 12 n ⁺ type buffer layer 14 n ⁻ type base region 16 p ⁻ type base region 17 p ⁺ type base region 18 n ⁺ type impurity diffusion layer 20 channel region 20a First channel region 20b Second channel region 22 Floating emitter region 30 Gate electrode 32 Gate insulating layer 50 Cathode electrode 60 Anode electrode 70 Buried insulating layer 80 Buried electrode 100, 200, 300, 400 MOS gate thyristor 500 IGBT 600 MOSFET

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI H01L 29/78 655 H01L 29/74 X 29/78 658F (56) References JP-A-5-267649 (JP, A) (58) ) Fields surveyed (Int.Cl. ⁷ , DB name) H01L 29/74

Claims (4)

(57) [Claims] 1. A first conductive type first semiconductor layer, a second conductive type second semiconductor layer formed on one main surface side of the first semiconductor layer, and a surface portion of the second semiconductor layer selected. Formed on the surface of the third semiconductor layer, a fourth semiconductor layer of the second conductivity type selectively formed on the surface portion of the third semiconductor layer, and a channel region in contact with the fourth semiconductor layer A fifth semiconductor layer capable of forming a first conductive layer, a second conductive type second layer selectively formed on the surface of the third semiconductor layer with the fifth semiconductor layer interposed therebetween. 6 semiconductor layers, at least a gate electrode formed on the surface of the fifth semiconductor layer via a gate insulating layer, inside the third semiconductor layer, and at least
The first of the fourth semiconductor layer and the fifth semiconductor layer
A buried insulating layer formed at an end on the semiconductor layer side or in the vicinity thereof, a first main electrode formed on the surfaces of the third semiconductor layer and the fourth semiconductor layer, and the other main of the first semiconductor layer A second main electrode formed on the surface side, and a trench gate is formed in at least the fifth semiconductor layer in a direction along a current path. 2. A first conductive type first semiconductor layer, a second conductive type second semiconductor layer formed on one main surface side of the first semiconductor layer, and a surface portion of the second semiconductor layer selected. Formed on the surface of the third semiconductor layer, a fourth semiconductor layer of the second conductivity type selectively formed on the surface portion of the third semiconductor layer, and a channel region in contact with the fourth semiconductor layer A fifth semiconductor layer capable of forming: a gate electrode formed on at least a surface of the fifth semiconductor layer via a gate insulating layer; and inside the third semiconductor layer, and at least:
The first of the fourth semiconductor layer and the fifth semiconductor layer
A buried insulating layer formed at an end on the semiconductor layer side or in the vicinity thereof, a first main electrode formed on the surfaces of the third semiconductor layer and the fourth semiconductor layer, and the other main of the first semiconductor layer A second main electrode formed on the surface side, and a trench gate is formed in at least the fifth semiconductor layer in a direction along a current path. 3. A second conductive type first semiconductor layer, a second conductive type second semiconductor layer formed on one main surface side of the first semiconductor layer, and a surface portion of the second semiconductor layer selected. Formed on the surface of the third semiconductor layer, a fourth semiconductor layer of the second conductivity type selectively formed on the surface portion of the third semiconductor layer, and a channel region in contact with the fourth semiconductor layer A fifth semiconductor layer capable of forming: a gate electrode formed on at least a surface of the fifth semiconductor layer via a gate insulating layer; and inside the third semiconductor layer, and at least:
The first of the fourth semiconductor layer and the fifth semiconductor layer
A buried insulating layer formed at an end on the semiconductor layer side or in the vicinity thereof, a first main electrode formed on the surfaces of the third semiconductor layer and the fourth semiconductor layer, and the other main of the first semiconductor layer A second main electrode formed on the surface side, and a trench gate is formed in at least the fifth semiconductor layer in a direction along a current path. 4. The claim 1-3, wherein the trench gate semiconductor device formed on a part or the whole of the gate insulating layer and the gate electrode is formed regions.