CN109103240A - A kind of low conducting power consumption silicon-on-insulator lateral insulated gate bipolar transistor - Google Patents
A kind of low conducting power consumption silicon-on-insulator lateral insulated gate bipolar transistor Download PDFInfo
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- CN109103240A CN109103240A CN201810954897.XA CN201810954897A CN109103240A CN 109103240 A CN109103240 A CN 109103240A CN 201810954897 A CN201810954897 A CN 201810954897A CN 109103240 A CN109103240 A CN 109103240A
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- 239000012212 insulator Substances 0.000 title abstract description 16
- 239000002184 metal Substances 0.000 claims abstract description 55
- 239000004065 semiconductor Substances 0.000 claims abstract description 16
- 238000009413 insulation Methods 0.000 claims abstract description 7
- 238000000407 epitaxy Methods 0.000 claims description 26
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 18
- 229920005591 polysilicon Polymers 0.000 claims description 17
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 9
- 229910052760 oxygen Inorganic materials 0.000 claims description 8
- 239000001301 oxygen Substances 0.000 claims description 8
- 239000000758 substrate Substances 0.000 claims description 6
- 238000005516 engineering process Methods 0.000 abstract description 2
- 238000010586 diagram Methods 0.000 description 12
- 230000003071 parasitic effect Effects 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 230000005611 electricity Effects 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 238000002955 isolation Methods 0.000 description 2
- 230000024241 parasitism Effects 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000002035 prolonged effect Effects 0.000 description 1
- 229920006395 saturated elastomer Polymers 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7394—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET on an insulating layer or substrate, e.g. thin film device or device isolated from the bulk substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
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- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Thin Film Transistor (AREA)
Abstract
The present invention relates to power semiconductor technologies, in particular to a kind of low conducting power consumption silicon-on-insulator lateral insulated gate bipolar transistor.The cathodic region of traditional landscape insulation bar double-pole-type transistor is transformed in the present invention, device is divided into the area MOS and the tradition structural area LIGBT by isolating oxide layer, MOS divides into the first NMOS area and the 2nd area MOS, and the first NMOS area and the 2nd area MOS share a P+ source short area.The grid of traditional structural area LIGBT and the grid of the first NMOS are used as device grids of the present invention by metal interconnection, the drain region N+ of first NMOS is connect by metal interconnection with the N+ source region of tradition LIGBT, the P+ source region of traditional LIGBT is connected by metal interconnection with the grid of the second N-type MOS and drain electrode, the N+ source region of traditional LIGBT is connected by metal interconnection with the drain region N+ of the first N-type MOS, the N+ source region of first and second NMOS and shared P+ source short area are shorted the cathode as device of the present invention by metal, the anode of traditional structural area LIGBT is used as device anode of the present invention.
Description
Technical field
The invention belongs to power semiconductor technologies fields, and in particular to a kind of low conducting power consumption silicon-on-insulator lateral insulation
Grid bipolar junction transistor.
Background technique
Insulated gate bipolar transistor, abbreviation IGBT is a kind of by power MOS field effect transistor and bipolar junction transistor
Hybrid power electronic device, it has MOS input, the MOS of bipolar output function, the bipolar characteristic combined, MOSFET knot
Structure is used to provide ideal base drive current to bipolar junction transistor, while bipolar junction transistor modulates MOSFET mechanism drift region
Conductivity, therefore the input impedance of the existing MOSFET of IGBT is high, control power is small, driving circuit is simple, switching speed is high, opens
It closes and small advantage is lost, and that the current density with bipolar power transistor is big, saturation pressure reduces, current handling capability is strong is excellent
Point is the ideal switching device of field of power electronics.For switching device, power consumption when reducing conducting is particularly important.
Summary of the invention
The high problem of power consumption is connected aiming at current conventional landscape insulation bar double-pole-type transistor in the purpose of the present invention,
It is proposed a kind of low conducting power consumption silicon-on-insulator lateral insulated gate bipolar transistor structure.Devices use latch-up of the present invention
Conducting resistance when break-over of device is significantly reduced, to reduce the conducting power consumption of device.
Technical solution of the present invention: a kind of low conducting power consumption landscape insulation bar double-pole-type transistor, structure cell includes P
Type substrate 1, burying oxygen 2 and burying the N-type epitaxy layer on oxygen 2 in P type substrate, which is characterized in that in N-type epitaxy layer along device
Transverse direction is equipped with isolating oxide layer 5, and isolating oxide layer 5 runs through N-type epitaxy layer along device vertical direction, by N-type epitaxy layer edge
Device transverse direction is separated into the first N-type epitaxy layer 3 and the second N-type epitaxy layer 4；
It is equipped with the first P type trap zone 6 on 3 top of the first N-type epitaxy layer, is set on 6 top of the first P type trap zone there are two N
Type metal-oxide-semiconductor, two N-type metal-oxide-semiconductors share a P+ source short area 13, and the first area N-type MOS and the second NMOS area are located at P+
13 left and right sides of source short area, i.e. P+ source short area 13 are located in the middle part of 6 upper layer of the first P type trap zone；First area N-type MOS packet
The first drain region N+ 8, the first N+ source region 9, the first gate oxide 110 are included, wherein the first N+ source region 9 and P+ source short area 13 connects
Touching, the first drain region N+ 8 is located at 6 upper layer side of the first P type trap zone；One end of first gate oxide 110 extends to the first N+
8 upper surface of drain region, the other end extend to 9 upper surface of the first N+ source region, and 110 upper surface of the first gate oxide is equipped with the first polysilicon
Grid 120；The first cathodic metal 131 is equipped with above the first N+ source region 9；The first sun is equipped with above first drain region N+ 8
Pole metal 130；Second area N-type MOS includes the 2nd N+ source region 10, the 2nd drain region N+ 11 and the second gate oxide 111, wherein second
N+ source region 10 is contacted with P+ source short area 13, and the 2nd drain region N+ 11 is located at the 6 upper layer other side of the first P type trap zone and and isolation from oxygen
Change layer 5 to contact；The second cathodic metal 131 is equipped with above the 2nd N+ source region 10, one end of second gate oxide 111 is prolonged
11 upper surface of the 2nd drain region N+ is reached, the other end extends to 10 upper surface of the 2nd N+ source region, and 111 upper surface of the second gate oxide is set
There is the second polysilicon gate 121；2nd N+ drain electrode top is equipped with second plate metal 133；
Be equipped with the second P type trap zone 7 and N-type buffer layer 14 in 4 upper layer two sides of the second epitaxial layer, wherein the second P type trap zone 7 with
Isolating oxide layer 5 contacts, and is equipped with the 3rd drain region P+ 15 far from the side of the second P type trap zone 7 on 14 upper layer of N-type buffer layer,
Third anode metal 136 is equipped with above the 3rd drain region P+ 15；The 3rd source P+ is equipped on 7 top of third P type trap zone
Area 16 and the 3rd N+ source region 12, and the 3rd P+ source region 16 is contacted with isolating oxide layer 5；It is equipped with above the 3rd P+ source region 16
Third cathodic metal 134 is equipped with the 4th cathodic metal 135 above the 3rd N+ source region 12；In the third P type trap zone 10
Top is equipped with third gate oxide 112, and a boundary of third gate oxide 112 extends to 12 top of the 3rd N+ source region, another
A boundary extends to 4 top of third N-type epitaxy layer；Third polysilicon gate 122 is equipped on the third gate oxide 112；
First cathodic metal 131 is device cathodes；First polysilicon gate 120 and third polysilicon gate
122 pass through metal interconnection as device grids；The first anode metal 130 passes through metal interconnection and the 4th cathodic metal 135
It is connected；Second polysilicon gate 121 is connected by metal interconnection with second plate metal 133 and third cathodic metal 134；Institute
Stating third anode metal 136 is device anode.
Beneficial effects of the present invention are, when break-over of device of the present invention, when anode voltage is smaller, the second NMOS tube is not yet opened
It opening, the P type trap zone potential in traditional structural area LIGBT is raised, and parasitic NPN transistor is opened, and so that device is entered latch mode,
Strong conductance modulation is formed in traditional structural area LIGBT, therefore significantly reduces conducting resistance.Gradually with anode voltage
Increase, the second NMOS transistor conduction is clamped the P type trap zone voltage in traditional structural area LIGBT, to have turned off parasitism
NPN transistor, device exit latch mode, progress into saturation state.
Detailed description of the invention
Fig. 1 is the device profile structure chart of silicon landscape insulation bar double-pole-type transistor in conventional insulator；
Fig. 2 is the device profile of low conducting power consumption silicon-on-insulator lateral insulated gate bipolar transistor proposed by the present invention
Structure chart (does not mark sequence)；
Fig. 3 is the device profile of low conducting power consumption silicon-on-insulator lateral insulated gate bipolar transistor proposed by the present invention
Structure chart (mark sequence)；
Fig. 4 is low conducting power consumption silicon-on-insulator lateral insulated gate bipolar transistor proposed by the present invention compared with primary anode electricity
Press current path figure under working condition；
Fig. 5 low conducting power consumption silicon-on-insulator lateral insulated gate bipolar transistor proposed by the present invention in big anode electricity
Enter the current path figure after saturation in the case of pressure；
Current direction when Fig. 6 is equivalent simplified circuit figure and the conducting of silicon lateral bipolar transistor in conventional insulator
Figure；
Fig. 7 is the equivalent-simplification of low conducting power consumption silicon-on-insulator lateral insulated gate bipolar transistor proposed by the present invention
Circuit diagram and its work current flow diagrams under linear zone；
Fig. 8 is the equivalent-simplification of low conducting power consumption silicon-on-insulator lateral insulated gate bipolar transistor proposed by the present invention
Circuit diagram and its work current flow diagrams under saturation region；
Fig. 9 is LIGBT device of the present invention and the positive pressure-resistant comparison diagram of traditional structure LIGBT device；
Figure 10 is the forward conduction I-V characteristic curve comparison figure of LIGBT device of the present invention Yu traditional structure LIGBT device；
Figure 11 be LIGBT device of the present invention with traditional structure LIGBT device the hole concentration under identical forward conduction electric current
The comparison diagram of distribution；
Specific embodiment
The present invention is described in detail with reference to the accompanying drawing.
Fig. 3 is the low conducting power consumption landscape insulation bar double-pole-type transistor device architecture of one kind proposed by the present invention, as schemed institute
Show, structure cell includes P type substrate 1, burying oxygen 2 and burying the N-type epitaxy layer on oxygen 2 in P type substrate, and feature exists
In in N-type epitaxy layer along device transverse direction equipped with isolating oxide layer 5, isolating oxide layer 5 runs through N-type along device vertical direction
N-type epitaxy layer is separated into the first N-type epitaxy layer 3 and the second N-type epitaxy layer 4 along device transverse direction by epitaxial layer；In the first N
3 top of type epitaxial layer is equipped with the first P type trap zone 6, sets on 6 top of the first P type trap zone there are two N-type metal-oxide-semiconductor, two N-types
Metal-oxide-semiconductor shares a P+ source short area 13, and it is left that the first area N-type MOS and the second NMOS area are located at P+ source short area 13
Right two sides, i.e. P+ source short area 13 are located in the middle part of 6 upper layer of the first P type trap zone；First area N-type MOS include the first drain region N+ 8,
First N+ source region 9, the first gate oxide 110, wherein the first N+ source region 9 is contacted with P+ source short area 13, the first 8, the drain region N+
In 6 upper layer side of the first P type trap zone；One end of first gate oxide 110 extends to 8 upper surface of the first drain region N+, another
End extends to 9 upper surface of the first N+ source region, and 110 upper surface of the first gate oxide is equipped with the first polysilicon gate 120；Described first
The first cathodic metal 131 is equipped with above N+ source region 9；First anode metal 130 is equipped with above first drain region N+ 8；Second N-type
The area MOS includes the 2nd N+ source region 10, the 2nd drain region N+ 11 and the second gate oxide 111, wherein the 2nd N+ source region 10 and P+ source electrode
Shorting region 13 contacts, and the 2nd drain region N+ 11 is located at the 6 upper layer other side of the first P type trap zone and contacts with isolating oxide layer 5；Described
The second cathodic metal 131 is equipped with above two N+ source regions 10, one end of second gate oxide 111 extends to the 2nd drain region N+ 11
Upper surface, the other end extend to 10 upper surface of the 2nd N+ source region, and 111 upper surface of the second gate oxide is equipped with the second polysilicon gate
121；2nd N+ drain electrode top is equipped with second plate metal 133；The second p-type trap is equipped in 4 upper layer two sides of the second epitaxial layer
Area 7 and N-type buffer layer 14, wherein the second P type trap zone 7 is contacted with isolating oxide layer 5, it is separate on 14 upper layer of N-type buffer layer
The side of second P type trap zone 7 is equipped with the 3rd drain region P+ 15, and third anode metal 136 is equipped with above the 3rd drain region P+ 15；
The 3rd P+ source region 16 and the 3rd N+ source region 12, and the 3rd P+ source region 16 and isolation oxidation are equipped on 7 top of third P type trap zone
Layer 5 contacts；It is equipped with third cathodic metal 134 above the 3rd P+ source region 16, is equipped with above the 3rd N+ source region 12
4th cathodic metal 135；Third gate oxide 112 is equipped with above the third P type trap zone 10, third gate oxide 112
One boundary extends to 12 top of the 3rd N+ source region, another boundary extends to 4 top of third N-type epitaxy layer；In the third
Gate oxide 112 is equipped with third polysilicon gate 122；First cathodic metal 131 is device cathodes；First polycrystalline
Silicon gate 120 and third polysilicon gate 122 pass through metal interconnection as device grids；The first anode metal 130 passes through
Metal interconnection is connected with the 4th cathodic metal 135；Second polysilicon gate 121 passes through metal interconnection and second plate metal
133 and third cathodic metal 134 be connected；The third anode metal 136 is device anode.
As shown in Figure 1, for silicon lateral bipolar transistor in conventional insulator.As shown in Fig. 2, one kind proposed by the present invention
Low conducting power consumption silicon-on-insulator lateral insulated gate bipolar transistor.The present invention place different from tradition LIGBT structure exists
In device cathodes area is transformed in the present invention.Traditional its cathodic metal of LIGBT structure is short with P+ source region, N+ source region simultaneously
Connect, and the present invention by by traditional structural area LIGBT P+ source region, metal separation is opened in N+ source region, in the N+ of traditional LIGBT
An external N-type metal-oxide-semiconductor (grid of the grid connection N-type metal-oxide-semiconductor of traditional LIGBT, the N+ source region of traditional LIGBT in source region
The drain region N+ of N-type metal-oxide-semiconductor is connected, the source electrode of N-type metal-oxide-semiconductor is used as cathode of the present invention), it is external in traditional LIGBT P+ source region
(the P+ source region of traditional LIGBT connects the drain region N+ and the grid of N-type metal-oxide-semiconductor, the source electrode of N-type metal-oxide-semiconductor to another N-type metal-oxide-semiconductor simultaneously
As cathode of the present invention).The area MOS and the tradition area LIGBT are isolated by isolating oxide layer simultaneously.
The low conducting power consumption silicon-on-insulator lateral insulated gate bipolar transistor of one kind proposed by the present invention, as shown in figure 3,
Its working principles are as follows:
On-state linear zone principle: being applied more than the voltage of threshold voltage on device grids, when the anode voltage of device is less than
When PN junction Built-in potential, electronics is flowed successively through the N-channel in the first area NOMS and LIGBT by the cathode of device, finally flows into LIGBT
Drift region (third N-type epitaxy layer 5), for parasitism PNP pipe base current is provided, as shown in Figure 4；When device anode voltage compared with
It is small but be greater than PN junction Built-in potential when, hole is injected into the drift region (third N-type epitaxy layer 5) of LIGBT from the anode of device, together
When the second NMOS tube due on grid voltage be not up to threshold voltage, the second NMOS tube will not open, and prevent hole from
Three P+ source regions flow to the cathode of device, so that p-well region (third p-well region 10) of the hole in LIGBT accumulates, so that p-well region
(third p-well region 10) potential is raised.When the potential between the 3rd N+ source region 15 of third p-well region 10/ is greater than PN junction Built-in potential,
The NPN parasitic triode triggering being made of the 3rd N+ source region 15, third p-well region 10, third N-type epitaxy layer 5, a large amount of electronics are logical
It crosses p-well region and is injected into drift layer, so that the carrier density of device drift layer significantly improves, current capacity lifting is realized low
Conducting resistance.
On-state saturation region principle: when anode voltage further increases under on-state, the strong conductance modulation in traditional area LIGBT
Effect causes the conduction voltage drop in traditional area LIGBT lower, so that third p-well region and the potential of the 3rd N+ source region are lifted therewith
It rises.Since third p-well region (third p-well region 10) is connected with the grid of the 2nd NMOS and drain electrode, the grid of the 2nd NMOS and leakage
Electrode potential increases accordingly, and after the potential of p-well region is greater than the threshold voltage of the 2nd NMOS, the 2nd NMOS conducting, hole can lead to
It crosses the 2nd NMOS and flows to device cathodes from third p-well region 10, the potential of third p-well region is clamped by the 2nd NMOS, and the 3rd source N+
The potential in area 10 can continue to be lifted.When the potential between p-well region/the 3rd N+ source region is less than PN junction Built-in potential, by the 3rd N
The NPN parasitic triode shutdown that+source region 15, third p-well region 10, third N-type epitaxy layer 5 are constituted, device electronic electric current pass through
The MOS channel of LIGBT flows away, and hole current flows to device cathodes by the 2nd NMOS by third p-well region, and device enters saturation
State.
The advantages of in order to verify structure of the invention, present invention employs semiconductor devices simulation software Medici to device
Structure has carried out contrast simulation, and as a result as shown in Fig. 4~Figure 11, Fig. 4 is structure of the invention in lower anode voltage, tradition
The structural area LIGBT enters current flow diagrams when latch mode.It can be seen from the figure that latch-up has occurred in device at this time,
And the 2nd NMOS is not opened at this time.Fig. 5 is the present invention when continuing that device enters saturation state after increasing with anode voltage
Current flow diagrams, due to the unlatching of the 2nd NMOS, device exits latch mode, progresses into saturation workspace.Fig. 6 is tradition
Current flow diagrams under the equivalent simplified circuit figure of LIGBT structure and its forward conduction state, Fig. 7 and Fig. 8 are respectively the present invention
Current flow diagrams of the device work under linear zone and saturation zone state.Comparison diagram 6, Fig. 7, Fig. 8 can be seen that device of the present invention
Inconsistent in linear zone and the current direction under saturation region operation state, Fig. 7 shows that device of the present invention works in linear work area
When, latch-up is occurred by the parasitic thyristor that PNP pipe and parasitic NPN pipe form, to form strong electricity in drift region
Modulation is led so that device on-resistance reduces.Fig. 8 shows device of the present invention current direction and tradition when being saturated workspace and working
Current direction is consistent when structure devices work.Fig. 9 is the pressure-resistant comparison diagram of device of the present invention and tradition LIGBT structure, Ke Yicong
Find out in figure, the voltage endurance capability of structure of the invention and traditional structure does not have significant difference.Figure 10 is device of the present invention and conventional junction
The forward conduction Character Comparison figure of structure device, it can be clearly seen that the present invention has lower conducting resistance, therefore has lower
Conducting power consumption.Figure 11 show the present invention with traditional structure in the comparison that hole concentration is distributed under identical forward conduction electric current
Figure, more evenly, and concentration is compared with traditional structure LIGBT high an order of magnitude for Carrier Profile in device drift region of the present invention,
Advantageously reduce device on-resistance.
Claims (1)
1. a kind of low conducting power consumption landscape insulation bar double-pole-type transistor, structure cell includes P type substrate (1), in P type substrate
On bury oxygen (2) and burying the N-type epitaxy layer on oxygen (2), which is characterized in that be equipped in N-type epitaxy layer along device transverse direction
Isolating oxide layer (5), isolating oxide layer (5) run through N-type epitaxy layer along device vertical direction, by N-type epitaxy layer along device transverse direction
Direction is separated into the first N-type epitaxy layer (3) and the second N-type epitaxy layer (4)；
The first N-type epitaxy layer (3) top be equipped with the first P type trap zone (6), set on the first P type trap zone (6) top there are two
N-type metal-oxide-semiconductor, two N-type metal-oxide-semiconductors share a P+ source short area (13), and position is distinguished in the first area N-type MOS and the second NMOS area
At left and right sides of P+ source short area (13), i.e., P+ source short area (13) are located in the middle part of the first P type trap zone (6) upper layer；First N
The area type MOS includes the first drain region N+ (8), the first N+ source region (9), the first gate oxide (110), wherein the first N+ source region (9) and P
+ source short area (13) contact, the first drain region N+ (8) is located at the first P type trap zone (6) upper layer side；First gate oxide
(110) one end extends to the first drain region N+ (8) upper surface, and the other end extends to the first N+ source region (9) upper surface, the first grid oxygen
Change layer (110) upper surface and is equipped with the first polysilicon gate (120)；The first cathodic metal is equipped with above the first N+ source region (9)
(131)；First anode metal (130) are equipped with above first drain region N+ (8)；Second area N-type MOS includes the 2nd N+ source region
(10), the 2nd drain region N+ (11) and the second gate oxide (111), wherein the 2nd N+ source region (10) connects with P+ source short area (13)
Touching, the 2nd drain region N+ (11) is located at the first P type trap zone (6) the upper layer other side and contacts with isolating oxide layer (5)；2nd N+
The second cathodic metal (131) are equipped with above source region (10), one end of second gate oxide (111) extends to the 2nd drain region N+
(11) upper surface, the other end extend to the 2nd N+ source region (10) upper surface, and the second gate oxide (111) upper surface is equipped with more than second
Polysilicon gate (121)；2nd N+ drain electrode top is equipped with second plate metal (133)；
It is equipped with the second P type trap zone (7) and N-type buffer layer (14) in the second epitaxial layer (4) upper layer two sides, wherein the second P type trap zone
(7) it is contacted with isolating oxide layer (5), is equipped with the far from the side of the second P type trap zone (7) on N-type buffer layer (14) upper layer
Three drain regions P+ (15) are equipped with third anode metal (136) above the 3rd drain region P+ (15)；In the third P type trap zone
(7) top is equipped with the 3rd P+ source region (16) and the 3rd N+ source region (12), and the 3rd P+ source region (16) connects with isolating oxide layer (5)
Touching；Third cathodic metal (134) are equipped with above the 3rd P+ source region (16), are equipped with above the 3rd N+ source region (12)
4th cathodic metal (135)；Third gate oxide (112) are equipped with above the third P type trap zone (10), third gate oxide
(112) a boundary extends to above the 3rd N+ source region (12), another boundary extends to above third N-type epitaxy layer (4)；
Third polysilicon gate (122) are equipped on the third gate oxide (112)；
First cathodic metal (131) is device cathodes；First polysilicon gate (120) and third polysilicon gate
(122) by metal interconnection as device grids；The first anode metal (130) passes through metal interconnection and the 4th cathodic metal
(135) it is connected；Second polysilicon gate (121) passes through metal interconnection and second plate metal (133) and third cathodic metal
(134) it is connected；The third anode metal (136) is device anode.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109920840A (en) * | 2019-03-20 | 2019-06-21 | 重庆邮电大学 | One kind having L-type SiO2The compound RC-LIGBT device of separation layer |
| CN113066862A (en) * | 2021-03-25 | 2021-07-02 | 电子科技大学 | Integrated MOS self-adaptive control SOI LIGBT |
| CN113078211A (en) * | 2021-03-25 | 2021-07-06 | 电子科技大学 | Integrated MOS self-adaptive control SOI LIGBT |
| CN114784102A (en) * | 2022-05-05 | 2022-07-22 | 电子科技大学 | LIGBT with mixed conduction mode |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| JP2002270844A (en) * | 2001-03-07 | 2002-09-20 | Toshiba Corp | Semiconductor device and manufacturing method of the same |
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| CN109920840A (en) * | 2019-03-20 | 2019-06-21 | 重庆邮电大学 | One kind having L-type SiO2The compound RC-LIGBT device of separation layer |
| CN113066862A (en) * | 2021-03-25 | 2021-07-02 | 电子科技大学 | Integrated MOS self-adaptive control SOI LIGBT |
| CN113078211A (en) * | 2021-03-25 | 2021-07-06 | 电子科技大学 | Integrated MOS self-adaptive control SOI LIGBT |
| CN114784102A (en) * | 2022-05-05 | 2022-07-22 | 电子科技大学 | LIGBT with mixed conduction mode |
| CN114784102B (en) * | 2022-05-05 | 2023-05-02 | 电子科技大学 | LIGBT with mixed conduction mode |
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