CN113066862A - Integrated MOS self-adaptive control SOI LIGBT - Google Patents
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- CN113066862A CN113066862A CN202110317574.1A CN202110317574A CN113066862A CN 113066862 A CN113066862 A CN 113066862A CN 202110317574 A CN202110317574 A CN 202110317574A CN 113066862 A CN113066862 A CN 113066862A
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7394—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET on an insulating layer or substrate, e.g. thin film device or device isolated from the bulk substrate
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- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
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- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
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Abstract
The invention belongs to the technical field of power semiconductors, and relates to an integrated MOS self-adaptive control SOI LIGBT. The invention is mainly characterized in that: 3 MOS tubes are integrated on the cathode side of the SOI LIGBT and are isolated from each other through an oxidation isolation groove. The MOS tube can realize the self-adaptive control of the SOI LIGBT through electrical connection. When the SOI LIGBT is conducted in the forward direction, the integrated MOS self-adaptive control SOI LIGBT parasitic diode is started, the conductance modulation effect is enhanced, the conduction voltage drop of the device is reduced, and the saturation current of the device is increased; in the turn-off process, the integrated MOS self-adaptive auxiliary depletion drift region provides an additional hole extraction channel, so that the turn-off loss is effectively reduced; under the short-circuit state, the integrated MOS self-adaptively controls the cut-off of the SOI LIGBT parasitic diode, thereby inhibiting the latch-up effect and improving the short-circuit resistance of the device. Compared with the traditional SOI LIGBT structure, the SOI LIGBT structure has the advantages of lower conduction voltage drop, lower turn-off loss, higher saturation current and longer short-circuit endurance time.
Description
Technical Field
The invention belongs to the technical field of power semiconductors, and relates to an integrated MOS self-adaptive control SOI LIGBT (Lateral Insulated Gate Bipolar Transistor).
Background
As a typical representative of electronic power devices, the IGBT has the advantages of high input impedance, good gate control capability, and simple driving circuit of the MOSFET, and also has the advantages of high current density, low on-state voltage drop, and high current handling capability of the BJT, and is currently widely used in the fields of high-speed rails, power grids, smart home appliances, new energy vehicles, and the like. The SOI-based LIGBT has the advantages of small leakage current, small parasitic capacitance and strong irradiation resistance due to the adoption of medium isolation. In addition, the Lateral IGBT (LIGBT) is convenient to integrate, and the SOI LIGBT is promoted to become a core component of a monolithic power integrated chip.
The IGBT low turn-on voltage drop benefits from the conductance modulation effect in the drift region when turned on. However, when the IGBT is turned off, the electron barrier of the anode region forces the carriers stored in the drift region to disappear through recombination, which results in a slow turn-off speed and an increased turn-off loss, limiting the high-frequency application of the IGBT. Therefore, the contradiction between the turn-on voltage drop and the turn-off loss remains a fundamental problem of the IGBT. The following three typical techniques for alleviating the contradiction between the two are available. Firstly, the life control technology can make the carrier recombination speed in the drift region faster and reduce the turn-off loss of the device. However, this technique also reduces the concentration of non-equilibrium carriers in the drift region when the device is turned on, and increases the on-state voltage drop. Secondly, a storage layer with a hole blocking effect is introduced into the cathode end, so that the carrier concentration of a drift region close to one side of the cathode end is increased, the conduction voltage drop is reduced, the non-equilibrium carriers still need to disappear through recombination, and the turn-off speed is still slow. Thirdly, the short-circuit anode technology can accelerate the extraction of carriers, and a good compromise between the conduction voltage drop and the turn-off loss is obtained. However, the snapback effect brought by the short-circuit anode structure can affect the uniformity of current distribution, and is not beneficial to the parallel application of devices.
In addition, because of the high current capability of the IGBT operating in the saturation region, large power consumption is generated in a high-voltage and large-current state when a short circuit occurs, so that the IGBT has risks of latch-up, early thermal breakdown and even failure, and thus the contradiction between the high saturation current and the short-circuit time of the IGBT is also a problem to be solved by the IGBT. Typical techniques for alleviating the contradictory relationship between the two are as follows. Firstly, a highly doped P-type buried layer is introduced at the cathode end, so that the equivalent resistance value in parallel with the cathode parasitic diode is reduced, and the parasitic diode is inhibited from being opened, thereby inhibiting latch-up. However, when the IGBT conductance modulation effect is strong, this technique still has a risk of latch-up. And secondly, a hole bypass is introduced at the cathode end, holes near the cathode are extracted, so that the conductance modulation effect is weakened, and the saturation current is reduced, thereby reducing the power consumption of the device when short circuit occurs and improving the short circuit capability. The technology weakens the conductance modulation effect when the device is conducted, and the conduction voltage drop of the device is increased.
Therefore, the invention provides an integrated MOS self-adaptive control SOI LIGBT, which realizes low leakage current, low conduction voltage drop, high saturation current and long and short circuit endurance time.
Disclosure of Invention
The invention provides an integrated MOS self-adaptive control SOI LIGBT aiming at the problems.
The technical scheme of the invention is as follows:
an integrated MOS self-adaptive control SOI LIGBT comprises a P substrate 1, a buried oxide layer 2 and a top semiconductor layer which are sequentially stacked from bottom to top; the top semiconductor layer is doped in an N type mode, a P well region 5 and an N type buffer layer 4 are arranged at two ends of the upper layer of the top semiconductor layer along the transverse direction of the device, and an N type semiconductor between the P well region 5 and the N type buffer layer 4 is an N drift region 3; the upper layer of the N-type buffer layer 4 is provided with a P + anode region 6, and the leading-out end of the P + anode region 6 is an anode; an integrated MOS structure, a P + region 8 and an N + region 7 which are arranged in parallel and a fourth P type body contact region 23 are sequentially arranged on the upper layer of the P well region 5 in the direction close to the N type buffer layer 4, the integrated MOS structure and the P + region 8 are isolated through a first medium isolation groove 11, and the P + region 8 is in contact with the first medium isolation groove 11; a LIGBT trench gate structure 9 is provided between the N + region 7 and the fourth P-type body contact region 23; the groove gate structure 9 penetrates through the P well region 5 from the surface downwards to the N drift region 3 along the vertical direction of the device; one side of the side face of the groove gate structure 9, which is close to the N-type buffer layer 4, is in contact with the fourth P-type body contact region 23, the P well region 5 and the N drift region 3, and the other side of the side face of the groove gate structure is in contact with the N + region 7, the P well region 5 and the N drift region 3;
the integrated MOS structure is characterized by comprising a first MOS, a second MOS and a third MOS; the first MOS is isolated from the P + region 8 through a first dielectric isolation groove 11, the first MOS is isolated from the second MOS through a second dielectric isolation groove 17, the second MOS is isolated from the third MOS through a third dielectric isolation groove 24, and the first dielectric isolation groove 11, the second dielectric isolation groove 17 and the third dielectric isolation groove 24 penetrate through the P well region 5 and the N drift region 3 from the surface downwards along the vertical direction of the device and then are contacted with the buried oxide layer 2; the first MOS/the second MOS/the third MOS are arranged on the upper layer of the P well region 5 in parallel, and comprise a first N + drain region 12/a second N + drain region 18/a third N + drain region 25, a first N + source region 13/a second N + source region 19/a third N + source region 26, a first P + body contact region 14/a second P + body contact region 20/a third P + body contact region 27, a first N + drain region 12/a second N + drain region 18/a third N + drain region 25, and a first planar gate 10/a second planar gate 15/a third planar gate 16 above the P well 5 between the first N + source region 13/the second N + source region 19/the third N + source region 26;
the first N + drain region 12 and the first P + body contact region 14 are positioned at two ends of the upper layer of the P well region 5 between the first medium isolation groove 11 and the second medium isolation groove 17; the second N + drain region 18 and the second P + body contact region 20 are positioned at two ends of the upper layer of the P well region 5 between the second medium isolation groove 17 and the third medium isolation groove 24; the third N + drain region 25 and the third P + body contact region 27 are located at two ends of the upper layer of the P well region 5 on the side of the third dielectric isolation trench 24 away from the second dielectric isolation trench 17; the first N + drain region 12/the second N + drain region 18/the third N + drain region 25 are in contact with the first dielectric isolation groove 11/the second dielectric isolation groove 17/the third dielectric isolation groove 24; the first N + source region 13 and the first P + body contact region 14, the second N + source region 19 and the second P + body contact region 20, and the third N + source region 26 are arranged in parallel in the third P + body contact region 27;
the common leading-out end of the groove grid structure 9 and the third plane grid 16 is a grid electrode; the common leading-out ends of the first N + source region 13, the second N + source region 19, the second P + body contact region 20, the third N + source region 26 and the third P + body contact region 27 are cathodes; leading-out ends of the N + region 7, the first P + body contact region 14 and the third N + drain region 25 are connected by floating ohmic contact; the leading-out ends of the P + region 8, the first N + drain region 12 and the first planar gate 10 are connected by floating ohmic contact; and the fourth P + body contact region 23, the second N + drain region 18 and the leading-out end of the second planar gate 15 are connected by floating ohmic contact.
The invention has the beneficial effect that compared with the traditional SOI LIGBT, the invention effectively relieves Von～EoffThe contradiction relationship can realize lower forward conduction voltage drop, lower turn-off loss, higher forward saturation current and longer short circuit endurance time, and can be compatible with high-low voltage device processes of a power integrated circuit, and the preparation cost is low.
Drawings
FIG. 1 is a schematic diagram of a cellular structure according to embodiment 1 of the present invention;
Detailed Description
The technical scheme of the invention is described in detail in the following with reference to the accompanying drawings and embodiments:
example 1
As shown in fig. 1, the structure of this example includes an integrated MOS adaptive control SOI LIGBT, which includes a P-substrate 1, a buried oxide layer 2 and a top semiconductor layer stacked in sequence from bottom to top; the top semiconductor layer is doped in an N type mode, a P well region 5 and an N type buffer layer 4 are arranged at two ends of the upper layer of the top semiconductor layer along the transverse direction of the device, and an N type semiconductor between the P well region 5 and the N type buffer layer 4 is an N drift region 3; the upper layer of the N-type buffer layer 4 is provided with a P + anode region 6, and the leading-out end of the P + anode region 6 is an anode; an integrated MOS structure, a P + region 8 and an N + region 7 which are arranged in parallel and a fourth P type body contact region 23 are sequentially arranged on the upper layer of the P well region 5 in the direction close to the N type buffer layer 4, the integrated MOS structure and the P + region 8 are isolated through a first medium isolation groove 11, and the P + region 8 is in contact with the first medium isolation groove 11; a LIGBT trench gate structure 9 is provided between the N + region 7 and the fourth P-type body contact region 23; the groove gate structure 9 penetrates through the P well region 5 from the surface downwards to the N drift region 3 along the vertical direction of the device; one side of the side face of the groove gate structure 9, which is close to the N-type buffer layer 4, is in contact with the fourth P-type body contact region 23, the P well region 5 and the N drift region 3, and the other side of the side face of the groove gate structure is in contact with the N + region 7, the P well region 5 and the N drift region 3;
the integrated MOS structure is characterized by comprising a first MOS, a second MOS and a third MOS; the first MOS is isolated from the P + region 8 through a first dielectric isolation groove 11, the first MOS is isolated from the second MOS through a second dielectric isolation groove 17, the second MOS is isolated from the third MOS through a third dielectric isolation groove 24, and the first dielectric isolation groove 11, the second dielectric isolation groove 17 and the third dielectric isolation groove 24 penetrate through the P well region 5 and the N drift region 3 from the surface downwards along the vertical direction of the device and then are contacted with the buried oxide layer 2; the first MOS/the second MOS/the third MOS are arranged on the upper layer of the P well region 5 in parallel, and comprise a first N + drain region 12/a second N + drain region 18/a third N + drain region 25, a first N + source region 13/a second N + source region 19/a third N + source region 26, a first P + body contact region 14/a second P + body contact region 20/a third P + body contact region 27, a first N + drain region 12/a second N + drain region 18/a third N + drain region 25, and a first planar gate 10/a second planar gate 15/a third planar gate 16 above the P well 5 between the first N + source region 13/the second N + source region 19/the third N + source region 26;
the first N + drain region 12 and the first P + body contact region 14 are positioned at two ends of the upper layer of the P well region 5 between the first medium isolation groove 11 and the second medium isolation groove 17; the second N + drain region 18 and the second P + body contact region 20 are positioned at two ends of the upper layer of the P well region 5 between the second medium isolation groove 17 and the third medium isolation groove 24; the third N + drain region 25 and the third P + body contact region 27 are located at two ends of the upper layer of the P well region 5 on the side of the third dielectric isolation trench 24 away from the second dielectric isolation trench 17; the first N + drain region 12/the second N + drain region 18/the third N + drain region 25 are in contact with the first dielectric isolation groove 11/the second dielectric isolation groove 17/the third dielectric isolation groove 24; the first N + source region 13 and the first P + body contact region 14, the second N + source region 19 and the second P + body contact region 20, and the third N + source region 26 are arranged in parallel in the third P + body contact region 27;
the common leading-out end of the groove grid structure 9 and the third plane grid 16 is a grid electrode; the common leading-out ends of the first N + source region 13, the second N + source region 19, the second P + body contact region 20, the third N + source region 26 and the third P + body contact region 27 are cathodes; leading-out ends of the N + region 7, the first P + body contact region 14 and the third N + drain region 25 are connected by floating ohmic contact; the leading-out ends of the P + region 8, the first N + drain region 12 and the first planar gate 10 are connected by floating ohmic contact; and the fourth P + body contact region 23, the second N + drain region 18 and the leading-out end of the second planar gate 15 are connected by floating ohmic contact.
The working principle of the embodiment is as follows:
the device shown in this example uses integrated MOS adaptive control SOI LIGBT. When the SOI LIGBT is conducted in the forward direction, the integrated MOS self-adaptive control SOI LIGBT parasitic diode is started, the conductance modulation effect is enhanced, the conduction voltage drop of the device is effectively reduced, the saturation current of the device is increased, and the driving capability of the device is improved; when the integrated MOS self-adaptive control SOI LIGBT groove gate is turned off in the forward direction, the P well region on the side, close to the anode, of the integrated MOS self-adaptive control SOI LIGBT groove gate assists in depleting the drift region, an extra hole extraction channel is provided, turn-off loss is effectively reduced, and V is relievedon～EoffA contradiction relationship; under the short-circuit state, the integrated MOS self-adaptively controls the cut-off of the SOI LIGBT parasitic diode, thereby inhibiting the latch-up effect and improving the short-circuit resistance of the device.
Claims (1)
1. An integrated MOS self-adaptive control SOILIGBT comprises a P substrate (1), a buried oxide layer (2) and a top semiconductor layer which are sequentially stacked from bottom to top; the top semiconductor layer is doped in an N type mode, a P well region (5) and an N type buffer layer (4) are arranged at two ends of the upper layer of the top semiconductor layer along the transverse direction of the device, and an N type semiconductor between the P well region (5) and the N type buffer layer (4) is an N drift region (3); the upper layer of the N-type buffer layer (4) is provided with a P + anode region (6), and the leading-out end of the P + anode region (6) is an anode; an integrated MOS structure, a P + region (8) and an N + region (7) which are arranged in parallel and a fourth P type body contact region (23) are sequentially arranged on the upper layer of the P well region (5) in the direction close to the N type buffer layer (4), the integrated MOS structure and the P + region (8) are isolated through a first medium isolation groove (11), and the P + region (8) is in contact with the first medium isolation groove (11); an LIGBT groove grid structure (9) is arranged between the N + region (7) and the fourth P-type body contact region (23); the groove gate structure (9) penetrates through the P well region (5) from the surface downwards to the N drift region (3) along the vertical direction of the device; one side, close to the N-type buffer layer (4), of the side face of the groove gate structure (9) is in contact with a fourth P-type body contact region (23), a P well region (5) and an N drift region (3), and the other side of the side face of the groove gate structure is in contact with an N + region (7), the P well region (5) and the N drift region (3);
the integrated MOS structure is characterized by comprising a first MOS, a second MOS and a third MOS; the first MOS and the P + region (8) are isolated through a first dielectric isolation groove (11), the first MOS and the second MOS are isolated through a second dielectric isolation groove (17), the second MOS and the third MOS are isolated through a third dielectric isolation groove (24), and the first dielectric isolation groove (11), the second dielectric isolation groove (17) and the third dielectric isolation groove (24) penetrate through the P well region (5) and the N drift region (3) from the surface downwards along the vertical direction of the device and then are contacted with the buried oxide layer (2); the first MOS/the second MOS/the third MOS are arranged on the upper layer of the P well region (5) in parallel, and comprise a first N + drain region (12)/a second N + drain region (18)/a third N + drain region (25), a first N + source region (13)/a second N + source region (19)/a third N + source region (26), a first P + body contact region (14)/a second P + body contact region (20)/a third P + body contact region (27), a first N + drain region (12)/a second N + drain region (18)/a third N + drain region (25) and a first planar gate (10)/a second planar gate (15)/a third planar gate (16) above the P well (5) between the first N + source region (13)/the second N + source region (19)/the third N + source region (26); the first N + drain region (12) and the first P + body contact region (14) are positioned at two ends of the upper layer of the P well region (5) between the first medium isolation groove (11) and the second medium isolation groove (17); the second N + drain region (18) and the second P + body contact region (20) are positioned at two ends of the upper layer of the P well region (5) between the second medium isolation groove (17) and the third medium isolation groove (24); the third N + drain region (25) and the third P + body contact region (27) are positioned at two ends of the upper layer of the P well region (5) at one side of the third medium isolation groove (24) far away from the second medium isolation groove (17); the first N + drain region (12)/the second N + drain region (18)/the third N + drain region (25) is in contact with the first medium isolation groove (11)/the second medium isolation groove (17)/the third medium isolation groove (24); the first N + source region (13) and the first P + body contact region (14), the second N + source region (19) and the second P + body contact region (20), and the third N + source region (26) are arranged in parallel in the third P + body contact region (27);
the common leading-out end of the groove grid structure (9) and the third plane grid (16) is a grid electrode; the common leading-out ends of the first N + source region (13), the second N + source region (19), the second P + body contact region (20), the third N + source region (26) and the third P + body contact region (27) are cathodes; leading-out ends of the N + region (7), the first P + body contact region (14) and the third N + drain region (25) are connected by floating ohmic contact; the P + region (8), the first N + drain region (12) and the leading-out end of the first planar gate (10) are connected by floating ohmic contact; and the fourth P + body contact region (23), the second N + drain region (18) and the leading-out end of the second planar gate (15) are connected by floating ohmic contact.
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Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050056906A1 (en) * | 2003-07-25 | 2005-03-17 | Shinichi Jimbo | Semiconductor device |
| US20100032712A1 (en) * | 2008-08-05 | 2010-02-11 | Cambridge Semiconductor Limited | Power semiconductor device and a method of forming a power semiconductor device |
| CN106505101A (en) * | 2016-10-19 | 2017-03-15 | 东南大学 | A kind of high current silicon-on-insulator lateral insulated-gate bipolar transistor device |
| CN107342321A (en) * | 2017-08-31 | 2017-11-10 | 电子科技大学 | A kind of SOI LIGBT with controllable colelctor electrode groove |
| CN109065609A (en) * | 2018-08-21 | 2018-12-21 | 电子科技大学 | A kind of low on-resistance silicon-on-insulator lateral insulated gate bipolar transistor |
| CN109103240A (en) * | 2018-08-21 | 2018-12-28 | 电子科技大学 | A kind of low conducting power consumption silicon-on-insulator lateral insulated gate bipolar transistor |
| CN109888006A (en) * | 2019-03-12 | 2019-06-14 | 电子科技大学 | Silicon landscape insulation bar double-pole-type transistor on a kind of low power consumption insulation body |
| CN110034176A (en) * | 2019-04-22 | 2019-07-19 | 东南大学 | Solve the inverse conductivity type landscape insulation bar double-pole-type transistor of Reverse recovery failure |
| CN110783398A (en) * | 2019-12-03 | 2020-02-11 | 济宁学院 | Large-current silicon-on-insulator lateral insulated gate bipolar transistor |
| CN111816699A (en) * | 2020-08-31 | 2020-10-23 | 电子科技大学 | SOI LIGBT device with self-adaptability |
-
2021
- 2021-03-25 CN CN202110317574.1A patent/CN113066862B/en active Active
Patent Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050056906A1 (en) * | 2003-07-25 | 2005-03-17 | Shinichi Jimbo | Semiconductor device |
| US20100032712A1 (en) * | 2008-08-05 | 2010-02-11 | Cambridge Semiconductor Limited | Power semiconductor device and a method of forming a power semiconductor device |
| CN106505101A (en) * | 2016-10-19 | 2017-03-15 | 东南大学 | A kind of high current silicon-on-insulator lateral insulated-gate bipolar transistor device |
| CN107342321A (en) * | 2017-08-31 | 2017-11-10 | 电子科技大学 | A kind of SOI LIGBT with controllable colelctor electrode groove |
| CN109065609A (en) * | 2018-08-21 | 2018-12-21 | 电子科技大学 | A kind of low on-resistance silicon-on-insulator lateral insulated gate bipolar transistor |
| CN109103240A (en) * | 2018-08-21 | 2018-12-28 | 电子科技大学 | A kind of low conducting power consumption silicon-on-insulator lateral insulated gate bipolar transistor |
| CN109888006A (en) * | 2019-03-12 | 2019-06-14 | 电子科技大学 | Silicon landscape insulation bar double-pole-type transistor on a kind of low power consumption insulation body |
| CN110034176A (en) * | 2019-04-22 | 2019-07-19 | 东南大学 | Solve the inverse conductivity type landscape insulation bar double-pole-type transistor of Reverse recovery failure |
| CN110783398A (en) * | 2019-12-03 | 2020-02-11 | 济宁学院 | Large-current silicon-on-insulator lateral insulated gate bipolar transistor |
| CN111816699A (en) * | 2020-08-31 | 2020-10-23 | 电子科技大学 | SOI LIGBT device with self-adaptability |
Non-Patent Citations (2)
| Title |
|---|
| SUN, WF ET AL.: "A composite structure named self-adjusted conductivity modulation SOI-LIGBT with low on-state voltage", 《29TH INTERNATIONAL SYMPOSIUM ON POWER SEMICONDUCTOR DEVICES AND ICS (ISPSD). PROCEEDINGS》 * |
| SUN, WF ET AL.: "Investigation on Self-Adjust Conductivity Modulation SOI-LIGBT Structure (SCM-LIGBT) for Monolithic High-Voltage IC", 《IEEE TRANSACTIONS ON ELECTRON DEVICES》 * |
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