CN109888006A - Silicon landscape insulation bar double-pole-type transistor on a kind of low power consumption insulation body - Google Patents
Silicon landscape insulation bar double-pole-type transistor on a kind of low power consumption insulation body Download PDFInfo
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Abstract
The present invention relates to power semiconductor technologies, in particular to silicon landscape insulation bar double-pole-type transistor on a kind of low power consumption insulation body.The cathodic region of traditional landscape insulation bar double-pole-type transistor is transformed in the present invention, device is divided into the area MOS and the tradition structural area LIGBT, MOS divides into the first NMOS area and the 2nd area MOS, and the first NMOS area and the 2nd area MOS share a P+ source short area.The grid of traditional structural area LIGBT and the grid of the first NMOS are used as device grids of the present invention by metal interconnection, the drain region N+ of first NMOS is connect by metal interconnection with the N+ source region of tradition LIGBT, the P+ source region of traditional LIGBT is connected by metal interconnection with the grid of the second N-type MOS and drain electrode, the N+ source region of traditional LIGBT is connected by metal interconnection with the drain region N+ of the first N-type MOS, the N+ source region of first and second NMOS and shared P+ source short area are shorted the cathode as device of the present invention by metal, the anode of traditional structural area LIGBT is used as device anode of the present invention.
Description
Technical field
The invention belongs to power semiconductor technologies fields, and in particular to silicon landscape insulation bar is double on a kind of low power consumption insulation body
Bipolar transistor.
Background technique
Insulated gate bipolar transistor, abbreviation IGBT is a kind of by power MOS field effect transistor and bipolar junction transistor
Hybrid power electronic device, with input impedance is high, driving circuit is simple, current density is big, saturation pressure reduces, current processing
The strong advantage of ability is the ideal switching device of field of power electronics.Lateral insulated gate bipolar transistor, that is, LIGBT is power collection
At component very important in circuit, the power loss in LIGBT application is mainly made of conducting power consumption and shutdown power consumption.For
Reduction chip area and power loss is reduced, therefore improves the conducting current density of LIGBT, reduces conduction voltage drop and subtract
Small shutdown power consumption is particularly important.
Summary of the invention
The purpose of the present invention is proposed aiming at the high problem of current conventional landscape insulation bar double-pole-type transistor power consumption
Silicon landscape insulation bar double-pole-type transistor structure on a kind of low power consumption insulation body.Devices use latch-up of the present invention significantly reduces
Conduction voltage drop when break-over of device, improves device inside Carrier Profile, to reduce the power consumption of device.
Technical solution of the present invention: a kind of low-power consumption landscape insulation bar double-pole-type transistor, structure cell include p-type lining
Bottom 1, burying oxygen 2 and burying the N-type epitaxy layer 3 on oxygen 2 in P type substrate 1, which is characterized in that on 3 top one of N-type epitaxy layer
Side is set there are two disjunct two P type trap zones, is respectively the first P type trap zone 4 and the second P type trap zone 5 along device transverse direction.
It is equipped with the first p type buried layer 6 inside the first P type trap zone 4, is set above first p type buried layer 6 there are two N-type
Metal-oxide-semiconductor, two N-type metal-oxide-semiconductors share a first P+ source short area 11, and the first area N-type MOS and the second NMOS area are located at
First P+ source short area, 11 left and right sides, i.e. the first P+ source short area 11 is located in the middle part of 4 upper layer of the first P type trap zone；First N
The area type MOS includes the first drain region N+ 9, the first N+ source region 10, the first gate oxide 110, wherein the first N+ source region 10 and the first P+
Source short area 11 contacts, and the first drain region N+ 9 is located at 4 upper layer side of the first P type trap zone；The one of first gate oxide 110
End extends to 9 upper surface of the first drain region N+, and the other end extends to 10 upper surface of the first N+ source region, table on the first gate oxide 110
Face is equipped with the first polysilicon gate 120；The first cathodic metal 130 is equipped with above first drain region N+ 9；The first N+ source region
10 and the first the second cathodic metal 131 is equipped with above P+ source short area 11；Second area N-type MOS includes the 2nd N+ source region 12, the
Two drain regions N+ 13 and the second gate oxide 111, wherein the 2nd N+ source region 12 is contacted with the first P+ source short area 11, the 2nd N+ leakage
Area 13 is located at the 4 upper layer other side of the first P type trap zone；It is equipped with the second cathodic metal 131 above the 2nd N+ source region 12, described the
One end of two gate oxides 111 extends to 13 upper surface of the 2nd drain region N+, and the other end extends to 12 upper surface of the 2nd N+ source region, the
Two gate oxides, 111 upper surface is equipped with the second polysilicon gate 121；2nd N+ drain electrode top is equipped with third cathodic metal
132；
It is equipped with the second p type buried layer 7 inside the second P type trap zone 5, is equipped with the 2nd source P+ on 7 top of the second p type buried layer
Pole shorting region 14 and the 3rd N+ source region 15, and the 2nd P+ source short area 14 is contacted with the 3rd N+ source region 15；In the 2nd P+
It is equipped with the 4th cathodic metal 133 above source short area 14, the 5th cathodic metal is equipped with above the 3rd N+ source region 15
135；Third gate oxide 112 is equipped with above the third P type trap zone 5, a boundary of third gate oxide 112 extends to
3rd N+ source region, 15 top, another boundary extend to 3 top of N-type epitaxy layer；The is equipped on the third gate oxide 112
Three polysilicon gates 122；
Side far from the first P type trap zone 4 and the second P type trap zone 5 above epitaxial layer 3 is equipped with N-type buffer layer 8, in institute
8 upper layer of N-type buffer layer is stated equipped with P+ drain electrode 16, is equipped with first anode metal 135 above P+ drain electrode 16；
Second cathodic metal 131 is device cathodes；First polysilicon gate 120 and third polysilicon gate
122 pass through metal interconnection as device grids；First cathodic metal 130 passes through metal interconnection and the 5th cathodic metal 134
It is connected and is used as floating Ohmic electrode；Second polysilicon gate 121 passes through metal interconnection and third cathodic metal 132 and the 4th yin
Pole metal 133, which is connected, is used as floating Ohmic electrode；The first anode metal 135 is device anode.
Beneficial effects of the present invention are, when break-over of device of the present invention, when anode voltage is smaller, the second NMOS tube is not yet opened
It opens, the P type trap zone potential in traditional structural area LIGBT is raised by anode injected holes, makes the p-type trap in the structural area LIGBT
Potential is greater than 0.7V between area/N+ source region, and parasitic NPN transistor is opened, and device enters latch mode, in traditional LIGBT structure
Drift region in form strong conductance modulation, and make drift region carrier concentration distribution more uniform, therefore greatly
Reduce conducting resistance.As anode voltage gradually increases, the second NMOS transistor conduction makes the p-type trap in traditional structural area LIGBT
Area's voltage is clamped, and due to the conducting resistance of the first NMOS, as anode voltage continues to increase, traditional LIGBT knot
The potential of N+ source region in structure area will continue to rise, and finally make potential between P type trap zone/N+ source region in the structural area LIGBT
Less than 0.7V, to have turned off parasitic NPN transistor, device exits latch mode, progresses into saturation state.
Detailed description of the invention
Fig. 1 is the device profile structure chart of silicon landscape insulation bar double-pole-type transistor in conventional insulator；
Fig. 2 is the device profile structure of silicon landscape insulation bar double-pole-type transistor on low power consumption insulation body proposed by the present invention
Scheme (not marking sequence)；
Fig. 3 is the device profile structure of silicon landscape insulation bar double-pole-type transistor on low power consumption insulation body proposed by the present invention
Figure (mark sequence)；
Fig. 4 be on low power consumption insulation body proposed by the present invention silicon landscape insulation bar double-pole-type transistor compared with primary anode voltage work
Current path figure in the case of work；
Silicon landscape insulation bar double-pole-type transistor in big anode voltage feelings on Fig. 5 low power consumption insulation body proposed by the present invention
Enter the current path figure after saturation under condition；
Current direction when Fig. 6 is equivalent simplified circuit figure and the conducting of silicon lateral bipolar transistor in conventional insulator
Figure；
Fig. 7 is the equivalent simplified circuit of silicon landscape insulation bar double-pole-type transistor on low power consumption insulation body proposed by the present invention
Figure and its current flow diagrams under linear zone that work；
Fig. 8 is the equivalent simplified circuit of silicon landscape insulation bar double-pole-type transistor on low power consumption insulation body proposed by the present invention
Figure and its current flow diagrams under saturation region that work；
Fig. 9 be LIGBT device of the present invention from tradition LIGBT between the second p-well under different anode voltages/the 3rd N+ source electrode
Potential difference；
Figure 10 is LIGBT device of the present invention in different p-well spacing L3Lower conducting electric current variation diagram；
Figure 11 is LIGBT device of the present invention in different gate oxide thickness TOXLower conducting electric current variation diagram；
Figure 12 is LIGBT device of the present invention in the first different NMOS grid width L1Lower conducting electric current variation diagram；
Figure 13 is LIGBT device of the present invention in the first different NMOS grid width L2Lower conducting electric current variation diagram；
Figure 14 is LIGBT device of the present invention in different grid voltage VGLower conducting electric current variation diagram；
Figure 15 is LIGBT device of the present invention and the positive pressure-resistant comparison diagram of traditional structure LIGBT device；
Figure 16 be LIGBT device of the present invention with traditional structure LIGBT device the hole concentration under identical forward conduction electric current
The comparison diagram of distribution；
Figure 17 is LIGBT device of the present invention and traditional structure LIGBT device turn-off characteristic comparison diagram；
Figure 18 is carrier variation diagram in LIGBT device of the present invention and traditional structure LIGBT device turn off process；
Figure 19 is LIGBT device of the present invention and traditional structure LIGBT device turn-off power loss and conduction voltage drop compromise figure；
Specific embodiment
The present invention is described in detail with reference to the accompanying drawing.
Fig. 3 is the low conducting power consumption landscape insulation bar double-pole-type transistor device architecture of one kind proposed by the present invention, as schemed institute
Show, structure cell includes P type substrate 1, burying oxygen 2 and burying the N-type epitaxy layer 3 on oxygen 2 in P type substrate 1, and feature exists
In setting in 3 top side of N-type epitaxy layer there are two disjunct two P type trap zones, be respectively the first P along device transverse direction
Type well region 4 and the second P type trap zone 5.The first p type buried layer 6 is equipped with inside the first P type trap zone 4, on first p type buried layer 6
Side is set there are two N-type metal-oxide-semiconductor, and two N-type metal-oxide-semiconductors share a first P+ source short area 11, the first area N-type MOS and second
NMOS area is located at 11 left and right sides of the first P+ source short area, i.e. the first P+ source short area 11 is located at the first P type trap zone 4
In the middle part of upper layer；First area N-type MOS includes the first drain region N+ 9, the first N+ source region 10, the first gate oxide 110, wherein the first N+
Source region 10 is contacted with the first P+ source short area 11, and the first drain region N+ 9 is located at 4 upper layer side of the first P type trap zone；The first grid
One end of oxide layer 110 extends to 9 upper surface of the first drain region N+, and the other end extends to 10 upper surface of the first N+ source region, the first grid
110 upper surface of oxide layer is equipped with the first polysilicon gate 120；The first cathodic metal 130 is equipped with above first drain region N+ 9；
The second cathodic metal 131 is equipped with above the first N+ source region 10 and the first P+ source short area 11；Second area N-type MOS includes
2nd N+ source region 12, the 2nd drain region N+ 13 and the second gate oxide 111, wherein the 2nd N+ source region 12 and the first P+ source short area
11 contacts, the 2nd drain region N+ 13 is located at the 4 upper layer other side of the first P type trap zone；The second yin is equipped with above the 2nd N+ source region 12
Pole metal 131, one end of second gate oxide 111 extend to 13 upper surface of the 2nd drain region N+, and the other end extends to the 2nd N
12 upper surface of+source region, 111 upper surface of the second gate oxide are equipped with the second polysilicon gate 121；2nd N+ drain electrode top is set
There is third cathodic metal 132；It is equipped with the second p type buried layer 7 inside the second P type trap zone 5, is set on 7 top of the second p type buried layer
There are the 2nd P+ source short area 14 and the 3rd N+ source region 15, and the 2nd P+ source short area 14 is contacted with the 3rd N+ source region 15；?
It is equipped with the 4th cathodic metal 133 above 2nd P+ source short area 14, the 5th is equipped with above the 3rd N+ source region 15
Cathodic metal 135；Third gate oxide 112, a side of third gate oxide 112 are equipped with above the third P type trap zone 5
Boundary extends to 15 top of the 3rd N+ source region, another boundary extends to 3 top of N-type epitaxy layer；In the third gate oxide 112
It is equipped with third polysilicon gate 122；Side far from the first P type trap zone 4 and the second P type trap zone 5 above epitaxial layer 3 is equipped with
N-type buffer layer 8 is equipped with P+ drain electrode 16 on 8 upper layer of N-type buffer layer, first anode gold is equipped with above P+ drain electrode 16
Belong to 135；Second cathodic metal 131 is device cathodes；First polysilicon gate 120 and third polysilicon gate 122
By metal interconnection as device grids；First cathodic metal 130 is connected by metal interconnection with the 5th cathodic metal 134
As floating Ohmic electrode；Second polysilicon gate 121 passes through metal interconnection and third cathodic metal 132 and the 4th cathode gold
Belong to 133 to be connected as floating Ohmic electrode；The first anode metal 135 is device anode.
As shown in Figure 1, for silicon landscape insulation bar double-pole-type transistor in conventional insulator.As shown in Fig. 2, the present invention proposes
A kind of low power consumption insulation body on silicon landscape insulation bar double-pole-type transistor.The present invention place different from tradition LIGBT structure
It is, device cathodes area is transformed in the present invention.Traditional its cathodic metal of LIGBT structure simultaneously with P+ source short area, N
+ source region is shorted, and the present invention by by traditional structural area LIGBT P+ source short area, metal separation is opened in N+ source region,
An external N-type metal-oxide-semiconductor (grid of the grid connection N-type metal-oxide-semiconductor of traditional LIGBT, tradition in the N+ source region of traditional LIGBT
The drain region N+ of the N+ source region connection N-type metal-oxide-semiconductor of LIGBT, the source electrode of N-type metal-oxide-semiconductor are used as cathode of the present invention), in traditional LIGBT P
(the P+ source short area of traditional LIGBT connects the N+ of N-type metal-oxide-semiconductor to another external N-type metal-oxide-semiconductor in+source short area simultaneously
Drain region and grid), two NMOS tubes are made in the same p-well and share a P+ source short area, the source of two NMOS tubes
The extremely short cathode connect as device of the present invention.
The low conducting power consumption silicon-on-insulator lateral insulated gate bipolar transistor of one kind proposed by the present invention, as shown in figure 3,
Its working principles are as follows:
On-state linear zone principle: being applied more than the voltage of threshold voltage on device grids, electronics by device cathode successively
The N-channel in the first area NOMS He the tradition structural area LIGBT is flowed through, finally flows into the drift region of the tradition structural area LIGBT (outside N-type
Prolong layer 3).When the anode voltage of device is smaller, hole is injected into the drift region (N-type of traditional structural area LIGBT from the anode of device
Epitaxial layer 3), most of injected holes accumulates (the second p-well region 5) in the p-well region of traditional structural area LIGBT, so that traditional
The p-well region potential of the structural area LIGBT is elevated, but is also not up to the 2nd NMOS cut-in voltage, therefore the second NMOS tube is not yet
Open, when the potential between the 3rd N+ source region 15 of the second p-well region 5/ be greater than its PN junction Built-in potential when, by the 3rd N+ source region 15,
The NPN parasitic triode triggering that second p-well region 5, N-type epitaxy layer 3 are constituted, a large amount of electronics are injected into N-type extension by p-well region
Layer, so that the carrier density of device drift layer significantly improves, current capacity is substantially lifted, and realizes low conducting resistance.
On-state saturation region principle: when anode voltage further increases under on-state, the potential of the second p-well region 5 continues to rise,
Since the second p-well region 5 is connected with the grid of the 2nd NMOS and drain electrode, when the potential of the second p-well region is greater than the threshold of the 2nd NMOS
After threshold voltage, the 2nd NMOS conducting, hole can flow to device cathodes, and the 2nd P from the second p-well region 5 by the 2nd NMOS
The 2nd NMOS after the potential of well region 5 is switched on is clamped, and the potential of the 3rd N+ source region 15 is due to the conducting resistance of the first NMOS
Reason continue to be lifted with anode voltage.When the potential between the 3rd N+ source region 15 of the second p-well region 5/ is built-in less than its PN junction
When potential, the NPN parasitic triode shutdown being made of the 3rd N+ source region 15, the second p-well region 5, N-type epitaxy layer 3, device electronic electricity
Stream is flowed away by the MOS channel of LIGBT, and hole current flows to device cathodes by the 2nd NMOS by third p-well region, device into
Enter saturation state.
The advantages of in order to verify structure of the invention, present invention employs semiconductor devices simulation software Medici to device
Structure has carried out contrast simulation, and (if unspecified, emulation default parameters is VG=10V, Tox=50nm, L1=0.3 μm, L2=
0.3μm,L3=3 μm), as a result as shown in Fig. 4~Figure 19, Fig. 4 is structure of the invention in lower anode voltage, tradition
The structural area LIGBT enters current flow diagrams when latch mode.It can be seen from the figure that latch-up has occurred in device at this time,
And the 2nd NMOS is not opened at this time.Fig. 5 is the present invention when continuing that device enters saturation state after increasing with anode voltage
Current flow diagrams, due to the unlatching of the 2nd NMOS, device exits latch mode, progresses into saturation workspace.Fig. 6 is tradition
Current flow diagrams under the equivalent simplified circuit figure of LIGBT structure and its forward conduction state, Fig. 7 and Fig. 8 are respectively the present invention
Current flow diagrams of the device work under linear zone and saturation zone state.Comparison diagram 6, Fig. 7, Fig. 8 can be seen that device of the present invention
Inconsistent in linear zone and the current direction under saturation region operation state, Fig. 7 shows that device of the present invention works in linear work area
When, latch-up is occurred by the parasitic thyristor that PNP pipe and parasitic NPN pipe form, to form strong electricity in drift region
Modulation is led so that device on-resistance reduces.Fig. 8 shows device of the present invention current direction and tradition when being saturated workspace and working
Current direction is consistent when structure devices work.Fig. 9 be device of the present invention and tradition LIGBT structure under different anode voltages along
Illustrate the potential profile in the direction AA ', it can be seen that it in anode voltage is 1V, electricity between the 3rd N+ source region 15 of the second p-well region 5/
Potential difference is more than 0.7V, therefore latch effect occurs for device, and with the increase of anode voltage, the potential of the second p-well region 5 is by the 2nd NMOS
It clamps and keeps almost unchanged, and the potential of the 3rd N+ source region 15 continues to increase due to the conducting resistance of the first NMOS,
The potential difference between the 3rd N+ source region 15 of the second p-well region 5/ is finally made to be less than 0.7V, device latch stops, and device enters saturation
State.
Since the switching of device latch mode to saturation state and the conducting of the first NMOS and the 2nd NMOS have substantial connection,
Therefore relevant parameter needs carefully design.Figure 10 is distance L between different first p-wells 4 and the second p-well 53In the case of, electricity
The understanding and considerate condition of conductance, works as L3When being negative that i.e. two p-wells are overlapped, device will appear snapback phenomenon, this is because hole is not
It easily accumulates, works when being easy to flow to cathode from the first p-well region, therefore device being caused just to start in IGBT mode in the second p-well region,
And as anode voltage increases, the second p-well region potential, which is gradually increased, opens the 3rd N+ source region 15 this PN junction of the second p-well region 5/
It opens, works in latch mode, anode voltage continues to increase, and the 2nd NMOS is opened, and device progresses into saturation.It is answered when therefore designing
It should be so that L3Greater than 0.Figure 11 is under different gate oxide thickness, and device forward conduction Character Comparison, too small gate oxide makes
It is excessive to obtain device saturation current, and excessive gate oxide is increased slightly forward conduction voltage drop, but tradition LIGBT relatively
For structure, the gate oxide thickness conduction voltage drop of different-thickness is all drastically reduced.Figure 12 is under the first NMOS grid width L1 of difference
Forward conduction characteristic curve, it can be seen that if L1<L2, device not can enter saturation state.Figure 13 is different first NMOS grid
Forward conduction characteristic curve under wide L1, it can be seen that if L2>L1, device not can enter saturation state.It should when therefore designing
Guarantee L1More than or equal to L2。
Figure 14 is the forward conduction Character Comparison of device and traditional structure of the present invention under different grid voltages, it can be seen that
Even if device of the present invention is in 100A/cm when grid voltage is lower2Conduction voltage drop be significantly lower than traditional structure, therefore be conducive to
Reduce gate driving power consumption.Figure 15 be device of the present invention and tradition LIGBT structure pressure-resistant comparison diagram, can as seen from the figure,
The voltage endurance capability of structure of the invention and traditional structure does not have significant difference, and leakage current slightly increased.Figure 16 show this hair
It is bright with traditional structure in the comparison diagram that hole concentration is distributed under identical forward conduction electric current, device drift region of the present invention current-carrying
Son is more evenly distributed, and advantageously reduces device on-resistance and shutdown power consumption.Figure 17 is that device of the present invention and traditional structure exist
Cut-off current is 100A/cm2, shutdown voltage be Vcc=300V, gate resistance RG=5 Ω, grid voltage VGFrom 10V to 0V, bear
Carry inductance LCThe shutdown curve of=1mH, parasitic inductance LS=10nH make device by adjusting device anode doping concentration of the present invention
Part conduction voltage drop is identical as traditional structure, and faster, turn-off power loss is lower for device turn-off speed of the present invention as seen from the figure.Figure 18 is
Figure 17 corresponding time point device inside Carrier Profile variation when turning off.Figure 19 is the folding of device turn-off power loss and conduction voltage drop
Middle relationship, it can be seen that tradeoff of the invention is obviously improved.
Claims (1)
1. a kind of low-power consumption landscape insulation bar double-pole-type transistor, structure cell includes P type substrate (1), in P type substrate (1)
On bury oxygen (2) and burying the N-type epitaxy layer (3) on oxygen (2), which is characterized in that be equipped in N-type epitaxy layer (3) top side
Two disjunct P type trap zones are respectively defined as the first P type trap zone (4) and the second P type trap zone (5) along device transverse direction, the
Two P type trap zones (5) are located at close to device anode side；
The first p type buried layer (6) are equipped with inside the first P type trap zone (4), set that there are two N above first p type buried layer (6)
Type metal-oxide-semiconductor, two N-type metal-oxide-semiconductors share a first P+ source short area (11), the first area N-type MOS and the second NMOS area difference
At left and right sides of the first P+ source short area (11), i.e., the first P+ source short area (11) is located at the first P type trap zone (4) upper layer
Middle part；First area N-type MOS includes the first drain region N+ (9), the first N+ source region (10), the first gate oxide (110), wherein the first N
+ source region (10) is contacted with the first P+ source short area (11), and the first drain region N+ (9) is located at the first P type trap zone (4) upper layer side；
One end of first gate oxide (110) extends to the first drain region N+ (9) upper surface, and the other end extends to the first N+ source region
(10) upper surface, the first gate oxide (110) upper surface are equipped with the first polysilicon gate (120)；On first drain region N+ (9)
Side is equipped with the first cathodic metal (130)；Second is equipped with above the first N+ source region (10) and the first P+ source short area (11)
Cathodic metal (131)；Second area N-type MOS includes the 2nd N+ source region (12), the 2nd drain region N+ (13) and the second gate oxide
(111), wherein the 2nd N+ source region (12) is contacted with the first P+ source short area (11), the 2nd drain region N+ (13) is located at the first p-type
Well region (4) upper layer other side；The second cathodic metal (131) are equipped with above the 2nd N+ source region (12), second gate oxidation
One end of layer (111) extends to the 2nd drain region N+ (13) upper surface, and the other end extends to the 2nd N+ source region (12) upper surface, and second
Gate oxide (111) upper surface is equipped with the second polysilicon gate (121)；2nd N+ drain electrode top is equipped with third cathodic metal
(132)；
The second p type buried layer (7) are equipped with inside the second P type trap zone (5), are equipped with the 2nd P+ on the second p type buried layer (7) top
Source short area (14) and the 3rd N+ source region (15), and the 2nd P+ source short area (14) is contacted with the 3rd N+ source region (15)；?
It is equipped with the 4th cathodic metal (133) above 2nd P+ source short area (14), is set above the 3rd N+ source region (15)
There is the 5th cathodic metal (135)；Third gate oxide (112) are equipped with above the third P type trap zone (5), third gate oxidation
One boundary of layer (112) extends to above the 3rd N+ source region (15), another boundary extends to above N-type epitaxy layer (3)；?
The third gate oxide (112) is equipped with third polysilicon gate (122)；
Side far from the first P type trap zone (4) and the second P type trap zone (5) above epitaxial layer (3) is equipped with N-type buffer layer (8),
It is equipped with P+ drain electrode (16) on N-type buffer layer (8) upper layer, first anode metal is equipped with above P+ drain electrode (16)
(135)；
Second cathodic metal (131) is device cathodes；First polysilicon gate (120) and third polysilicon gate
(122) by metal interconnection as device grids；First cathodic metal (130) passes through metal interconnection and the 5th cathodic metal
(134) it is connected and is used as floating Ohmic electrode；Second polysilicon gate (121) passes through metal interconnection and third cathodic metal
(132) and the 4th cathodic metal (133) is connected as floating Ohmic electrode；The first anode metal (135) is device anode.
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| CN113066862A (en) * | 2021-03-25 | 2021-07-02 | 电子科技大学 | Integrated MOS self-adaptive control SOI LIGBT |
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| JP2002270844A (en) * | 2001-03-07 | 2002-09-20 | Toshiba Corp | Semiconductor device and manufacturing method of the same |
| US20120307407A1 (en) * | 2011-06-03 | 2012-12-06 | Renesas Electronics Corporation | Semiconductor device |
| CN105826367A (en) * | 2016-03-18 | 2016-08-03 | 东南大学 | Large-current silicon on insulator lateral insulated gate bipolar transistor device |
| CN106505101A (en) * | 2016-10-19 | 2017-03-15 | 东南大学 | A kind of high current silicon-on-insulator lateral insulated-gate bipolar transistor device |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113066862A (en) * | 2021-03-25 | 2021-07-02 | 电子科技大学 | Integrated MOS self-adaptive control SOI LIGBT |
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