CN214588866U

CN214588866U - Low-capacitance IGBT device

Info

Publication number: CN214588866U
Application number: CN202120578205.3U
Authority: CN
Inventors: 朱辉; 潘恒
Original assignee: Anhui Ruidi Microelectronics Co ltd
Current assignee: Anhui Ruidi Microelectronics Co ltd
Priority date: 2021-03-22
Filing date: 2021-03-22
Publication date: 2021-11-02
Anticipated expiration: 2031-03-22

Abstract

The utility model discloses a low electric capacity IGBT device, including N type drift region, two ditch groove bars, set up in the active area between two ditch groove bars, set up in the superficial empty P district of N type drift region upper surface and set up in the ditch groove bars with the auxiliary tank between the superficial empty P district. The utility model discloses a low electric capacity IGBT device, the leading-in of auxiliary tank is very big has reduced the miller electric capacity of device, can bring better performance promotion for the device to can not reduce any parameter index.

Description

Low-capacitance IGBT device

Technical Field

The utility model belongs to the technical field of the semiconductor product, specifically speaking, the utility model relates to a low electric capacity IGBT device.

Background

An Insulated Gate Bipolar Transistor (IGBT) combines the advantages of a BJT (Bipolar junction Transistor) of low on-state voltage drop and a MOSFET (Insulated Gate field effect Transistor) of high input impedance, and has the characteristics of full control, voltage driving, low on-state voltage drop, low switching loss, and the like. The application of the semiconductor is more and more extensive, and the semiconductor is widely applied to various fields of high-voltage power grids, rail transit, electric automobiles, industry, war industry, household appliances and the like at present, and is an important power semiconductor device.

With the development of the IGBT technology, the chip area is smaller and smaller, the current density is larger and larger, and the tradeoff relationship between the conduction voltage drop and the switching loss is particularly important. The emitter surface carrier enhancement technology improves the compromise relationship between the IGBT conduction voltage drop and the switching loss, and a common carrier enhancement technology is a floating P-type IGBT, and the structure of the carrier enhancement technology is shown in FIG. 1. Due to the introduction of the floating P region, the surface carrier concentration of the device in a conducting state is improved, and the conducting voltage drop of the device is reduced; the floating P region is introduced, so that channels exist on only one side of the grid electrode of the groove, the number of the channels can be effectively controlled, and the short-circuit capability of the device is ensured; in addition, the floating P-type IGBT structure is basically consistent with the conventional Trench IGBT, the structure is simpler, the process is consistent with the conventional Trench IGBT process, and any process difficulty and process cost cannot be increased.

The main parasitic capacitance distribution of the floating P-type IGBT is as shown in fig. 2, the capacitance of the floating P-type IGBT mainly has three parts, a collector-emitter capacitance (CCE) is formed by a junction capacitance in a hydrazine region, a gate-collector Capacitance (CGE) is formed by a polysilicon trench gate, the hydrazine region, an N + region and a surface metal, and a gate-collector capacitance (CGC) is formed by the polysilicon trench gate, a drift region and a floating P region. The largest part of the parasitic capacitance is the gate-collector capacitance (CGC) formed by the gate polysilicon and the collector, which is also called the miller capacitance. The overlarge Miller capacitor needs longer discharge time when the device is turned off, the switching speed is slower, and the switching loss is large; when the device is switched on, the gate of the device has a large displacement current, the gate becomes uncontrollable, and large dv/dt occurs in the switching process of the device, so that the EMC problem occurs at an application end, and large peak current is introduced, so that the device and the matched FRD fail; under the condition of short circuit, the device is uncontrollable due to the overlarge Miller capacitance, the instantaneous power is higher, the short circuit failure of the device is easily caused, and the short circuit capacity of the device is reduced.

SUMMERY OF THE UTILITY MODEL

The utility model discloses aim at solving one of the technical problem that exists among the prior art at least. Therefore, the utility model provides a low electric capacity IGBT device, the purpose reduces the miller electric capacity.

In order to realize the purpose, the utility model discloses the technical scheme who takes does: the low-capacitance IGBT device comprises an N-type drift region, two trench gates, an active region arranged between the two trench gates, a floating P region arranged on the upper surface of the N-type drift region, and an auxiliary groove arranged between the trench gates and the floating P region.

The floating P area is two, the auxiliary grooves are two, and the two groove gates are located between the two auxiliary grooves.

The active region includes a hydrazine region, a P + contact region, and an N + emitter.

And an insulating isolation dielectric layer and front emitter metal are arranged above the trench gate.

The auxiliary groove comprises an insulating oxide layer and polysilicon dummy.

The utility model discloses a low electric capacity IGBT device, the leading-in of auxiliary tank is very big has reduced the miller electric capacity of device, can bring better performance promotion for the device to can not reduce any parameter index.

Drawings

The description includes the following figures, the contents shown are respectively:

FIG. 1 is a schematic diagram of a prior art floating P-type IGBT structure;

FIG. 2 is a prior art floating P-type IGBT parasitic capacitance distribution plot;

FIG. 3 is a schematic structural diagram of the low capacitance IGBT of the present invention;

fig. 4a to 4i are schematic diagrams of a manufacturing process of a low capacitance IGBT;

fig. 5 is a schematic structural diagram of the low-capacitance IGBT according to the first embodiment;

fig. 6 is a schematic structural view of a low-capacitance IGBT according to a second embodiment.

Detailed Description

The following detailed description of the embodiments of the present invention will be given with reference to the accompanying drawings, for the purpose of helping those skilled in the art to understand more completely, accurately and deeply the conception and technical solution of the present invention, and to facilitate its implementation.

As shown in fig. 3, the utility model provides a low electric capacity IGBT device, include N type drift region, two ditch groove bars, set up in the active area between two ditch groove bars, set up in the superficial empty P district of N type drift region upper surface and set up in the ditch groove bars with the supplementary groove between the superficial empty P district.

Specifically speaking, as shown in fig. 3, the utility model provides a low electric capacity IGBT structural feature as follows: the active region is clamped between the two trench gates, an auxiliary trench is arranged on the other side of the trench, a floating P region is arranged on the other side of the auxiliary trench, and the rest structure is consistent with the existing field stop type IGBT structure.

The utility model provides a supplementary groove has been introduced to low electric capacity IGBT device, the leading-in of supplementary groove is very big has reduced the miller electric capacity of device, can bring better performance promotion for the device to can not reduce any parameter index. Under the blocking state, the introduction of the auxiliary groove can reduce the electric field intensity at the bottom of the groove, improve the voltage resistance of the device and reduce the leakage current of the device; the blocking effect of the auxiliary groove and the floating P region in the conducting state can improve the surface carrier storage concentration of the device and reduce the conducting voltage drop of the device, so that the device can obtain the conducting voltage drop as low as that of the existing floating P-type IGBT; in the process of turning on the device, the lower Miller capacitance of the device enables the turning on process of the device to be controllable, and a proper turning on resistance can be selected according to application requirements, so that the device obtains lower turning on loss, lower dv/dt and smaller turning on current overshoot in the turning on process, the failure rate of the device and matched FRD application is reduced, and the EMC problem in the application of the device is prevented; in the turn-off process of the device, the turn-off loss of the device is reduced by the lower Miller capacitance, and the compromise relation between the conduction voltage drop and the switching loss of the device is optimized. Under the condition of short circuit, the overshoot voltage of the grid electrode of the device with the small Miller capacitance is small, the instantaneous power of the short circuit of the device is controllable, and the good short circuit capability can be obtained under the appropriate channel density setting.

For the low-capacitance IGBT device with the structure, the specific manufacturing process is as follows:

1. TEOS is deposited on the local melting silicon single crystal 401 and annealed to form a hard mask layer 402, as shown in FIG. 4 a;

2. opening the groove area of the hard mask layer by photoetching, and etching the groove after removing the photoresist, as shown in FIG. 4 b;

3. removing the hard mask, growing the gate oxide 403, depositing polysilicon 404, as shown in FIG. 4 c;

4. etching back the polysilicon 404 to remove the polysilicon and the gate oxide layer on the surface, as shown in fig. 4 d;

5. growing Pad oxide 405, injecting, and thermally pushing the junction to form a Pwell region 406, a floating P region 407, and an N +408, as shown in FIG. 4 e;

6. depositing a dielectric layer and annealing to form a hard mask layer 409, opening the auxiliary groove area of the hard mask layer 409 by photoetching, and etching the auxiliary groove, as shown in FIG. 4 f;

7. growing a gate oxide layer, depositing a dielectric layer to form the auxiliary trench 410 and the ILD 411, as shown in FIG. 4 g;

8. photoetching and etching to open a contact area, etching silicon to enable a contact hole to contact a Pwell area, injecting Pwell to contact the P + layer 412 and activating, and sputtering front metal 413, as shown in FIG. 4 h;

9. back side implanting N-type impurities and activating to form field stop layer 414, implanting P-type impurities and activating to form P + collector 415, forming back side metal 416, as shown in fig. 4 i.

The first embodiment is as follows:

as shown in fig. 5, in the low-capacitance IGBT device of this embodiment, the active region (including the hydrazine region 506, the P + contact region 512, and the N + emitter 508) is sandwiched between two trench gates 504, an auxiliary trench 510 is formed on the other side of the trench, the auxiliary gate 510 is filled with a dielectric layer, and a floating P region 507 is formed on the other side of the auxiliary trench; above the trench is an insulating isolation dielectric layer 511 and a front emitter metal 513; below the trench are in turn an N-drift region 501, a field stop layer 514, a P + collector region 515, a back collector metal 516.

In the embodiment, the auxiliary groove is filled with the dielectric layer, the thickness of the dielectric layer on the floating P region side of the trench gate is increased, the Miller capacitance of the device is reduced, the device can be provided with better performance improvement, and any parameter index can not be reduced. Under the blocking state, the introduction of the auxiliary groove can reduce the power plant strength at the bottom of the groove, improve the voltage resistance of the device and reduce the leakage current of the device; the blocking effect of the auxiliary groove and the floating P region in the conducting state can improve the surface carrier storage concentration of the device and reduce the conducting voltage drop of the device, so that the device can obtain the conducting voltage drop as low as that of the existing floating P-type IGBT; in the process of turning on the device, the lower Miller capacitance of the device enables the turning on process of the device to be controllable, and a proper turning on resistance can be selected according to application requirements, so that the device obtains lower turning on loss, lower dv/dt and smaller turning on current overshoot in the turning on process, the failure rate of the device and matched FRD application is reduced, and the EMC problem in the application of the device is prevented; in the turn-off process of the device, the turn-off loss of the device is reduced by the lower Miller capacitance, and the compromise relation between the conduction voltage drop and the switching loss of the device is optimized. Under the condition of short circuit, the overshoot voltage of the grid electrode of the device with the small Miller capacitance is small, the instantaneous power of the short circuit of the device is controllable, and the good short circuit capability can be obtained under the appropriate channel density setting.

Example two:

as shown in fig. 6, in the low capacitance IGBT device of this embodiment, the active region (including the hydrazine region 606, the P + contact region 612, and the N + emitter 608) is sandwiched between two Trench gates 604, an auxiliary Trench 610 is formed on the other side of the Trench, the auxiliary Trench is composed of dummy trenches connected to the emitter, and includes an insulating oxide layer 6101 and polysilicon dummy 6102, and a floating P region 607 is formed on the other side of the auxiliary Trench; above the trench is an insulating isolation dielectric layer 611 and front emitter metal 613; below the trench are in turn an N-drift region 601, a field stop layer 614, a P + collector region 615, a back collector metal 616.

In this embodiment, the auxiliary tank is composed of dummy trenches connected to the emitter, and the original gate-collector capacitance is changed into a gate-emitter capacitance, so that the miller capacitance of the device is reduced, and the device has better performance improvement. Under the blocking state, the introduction of the auxiliary groove can reduce the power plant strength at the bottom of the groove, improve the voltage resistance of the device and reduce the leakage current of the device; the blocking effect of the auxiliary groove and the floating P region in the conducting state can improve the surface carrier storage concentration of the device and reduce the conducting voltage drop of the device, so that the device can obtain the conducting voltage drop as low as that of the existing floating P-type IGBT; in the process of turning on the device, the lower Miller capacitance of the device enables the turning on process of the device to be controllable, and a proper turning on resistance can be selected according to application requirements, so that the device obtains lower turning on loss, lower dv/dt and smaller turning on current overshoot in the turning on process, the failure rate of the device and matched FRD application is reduced, and the EMC problem in the application of the device is prevented; in the turn-off process of the device, the turn-off loss of the device is reduced by the lower Miller capacitance, and the compromise relation between the conduction voltage drop and the switching loss of the device is optimized. Under the condition of short circuit, the overshoot voltage of the grid electrode of the device with the small Miller capacitance is small, the instantaneous power of the short circuit of the device is controllable, and the good short circuit capability can be obtained under the appropriate channel density setting.

The invention has been described above by way of example with reference to the accompanying drawings. Obviously, the specific implementation of the present invention is not limited by the above-described manner. Various insubstantial improvements are made by adopting the method conception and the technical proposal of the utility model; or without improvement, the above conception and technical solution of the present invention can be directly applied to other occasions, all within the protection scope of the present invention.

Claims

1. Low electric capacity IGBT device, including N type drift region, two ditch groove bars, set up the active area between two ditch groove bars and set up in the superficial empty P district of N type drift region upper surface, its characterized in that: the floating gate structure further comprises an auxiliary groove arranged between the groove gate and the floating P region.

2. The low capacitance IGBT device of claim 1, wherein: the floating P area is two, the auxiliary grooves are two, and the two groove gates are located between the two auxiliary grooves.

3. A low capacitance IGBT device according to claim 1 or 2, characterized in that: the active region includes a hydrazine region, a P + contact region, and an N + emitter.

4. A low capacitance IGBT device according to claim 1 or 2, characterized in that: and an insulating isolation dielectric layer and front emitter metal are arranged above the trench gate.

5. The low capacitance IGBT device of claim 4, wherein: the auxiliary groove comprises an insulating oxide layer and polysilicon dummy.