CN107799582B - Trench gate charge storage type insulated gate bipolar transistor and manufacturing method thereof - Google Patents

Trench gate charge storage type insulated gate bipolar transistor and manufacturing method thereof Download PDF

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CN107799582B
CN107799582B CN201710986479.4A CN201710986479A CN107799582B CN 107799582 B CN107799582 B CN 107799582B CN 201710986479 A CN201710986479 A CN 201710986479A CN 107799582 B CN107799582 B CN 107799582B
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gate
emitter
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CN107799582A (en
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张金平
赵倩
刘竞秀
李泽宏
任敏
张波
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University of Electronic Science and Technology of China
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    • H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
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Abstract

A trench gate charge storage type insulated gate bipolar transistor and a manufacturing method thereof belong to the field of semiconductor power devices. The invention overcomes the adverse effect of an N-type charge storage layer in the traditional structure, obtains more excellent voltage resistance, and solves the problems of compromised characteristics of switching performance, conduction voltage drop and switching loss and reliability of the device caused by deepening the depth of a trench gate and reducing the width of a cell compared with the traditional mode. According to the invention, the series diode structure is introduced into the P-type body region, so that the channel voltage of the MOSFET is clamped at a very small value, the saturation current density of the device is reduced, and the short-circuit safe working region of the device is improved; by introducing the split electrode and the split electrode dielectric layer into the trench gate structure, the switching performance of the device is improved while the threshold voltage and the switching speed of the device are ensured; the floating P-type body region improves the compromise characteristic of forward conduction voltage drop and switching loss of the device. In addition, the invention provides that the manufacturing process of the CSTBT device is compatible with the traditional manufacturing process.

Description

Trench gate charge storage type insulated gate bipolar transistor and manufacturing method thereof
Technical Field
The invention belongs to the technical field of semiconductor power devices, particularly relates to an Insulated Gate Bipolar Transistor (IGBT), and particularly relates to a trench gate charge storage type insulated gate bipolar transistor (CSTBT).
Background
Insulated Gate Bipolar Transistors (IGBTs) are widely used in various fields such as traffic, communication, household appliances, aerospace, and the like as one of the core electronic components in modern power electronic circuits. An Insulated Gate Bipolar Transistor (IGBT) is a novel power electronic device formed by compounding an insulated field effect transistor (MOSFET) and a Bipolar Junction Transistor (BJT), and can be equivalent to the MOSFET driven by the bipolar junction transistor. The IGBT mixes the working mechanism of the MOSFET structure and the bipolar junction transistor, has the advantages of easy driving of the MOSFET, low input impedance and high switching speed, and also has the advantages of high on-state current density, low on-state voltage reduction, low loss and good stability of the BJT, so that the application of the IGBT improves the performance of a power electronic system. Since the invention of the IGBT, people are always working on improving the performance of the IGBT, and through twenty years of development, seven generations of IGBT device structures are proposed successively to continuously improve the performance of the device. A seventh generation IGBT structure, namely a trench gate charge storage type insulated gate bipolar transistor (CSTBT), is characterized in that a hole potential barrier is introduced below a P type base region by introducing an N type charge storage layer with higher doping concentration and certain thickness below the P type base region, so that the hole concentration of a device close to an emitter terminal is greatly improved, the electron concentration of the device is greatly increased according to the electric neutral requirement, the carrier concentration distribution of the whole N-drift region is improved, the conductivity modulation effect of the N-drift region is enhanced, and the IGBT obtains lower forward conduction voltage drop and better compromise relationship between the forward conduction voltage drop and turn-off loss. The higher the doping concentration of the N-type charge storage layer is, the greater the CSTBT conductivity modulation effect is improved, and the better the forward conduction characteristic of the device is. However, with the increasing doping concentration of the N-type charge storage layer, the breakdown voltage of the CSTBT device is remarkably reduced. In the conventional csbt device structure shown in fig. 1, in order to effectively shield the adverse effect of the N-type charge storage layer and obtain a higher device withstand voltage, the following two methods are mainly adopted:
(1) a deep trench gate depth, typically such that the trench gate depth is greater than the junction depth of the N-type charge storage layer;
(2) the width of the unit cell is small, namely the channel density of the MOS structure is improved to ensure that the distance between the groove gates is as small as possible;
while the method (1) is implemented, the gate-emitter capacitance and the gate-collector capacitance are increased, and the switching process of the IGBT is essentially a process of charging/discharging the gate capacitance, so that the increase of the gate capacitance increases the charging/discharging time, and further, the switching speed is reduced. Therefore, the deep trench gate depth can reduce the switching speed of the device, increase the switching loss of the device and influence the compromise characteristic of the conduction voltage drop and the switching loss of the device; the implementation of the mode (2) will increase the gate capacitance of the device, resulting in the reduction of the switching speed and the increase of the switching loss of the device, and affecting the compromise characteristic of the conduction voltage drop and the switching loss of the device, and on the other hand, the large channel density will also increase the saturation current density of the device, and make the short-circuit safe working area of the device worse. In addition, a gate oxide layer in a trench gate structure is formed in a trench through one-time thermal oxidation, in order to guarantee a certain threshold voltage, the thickness of the whole gate oxide layer is required to be smaller, however, the size of an MOS capacitor is inversely proportional to the thickness of the oxide layer, so that the thickness of the thin gate oxide layer in the traditional CSTBT device can obviously increase the gate capacitance of the device, and meanwhile, the electric field concentration effect at the bottom of the trench can reduce the breakdown voltage of the device, so that the reliability of the device is poor.
Disclosure of Invention
The technical problem to be solved by the invention is as follows: the trench gate charge storage type insulated gate bipolar transistor with excellent comprehensive performance and the manufacturing method thereof are provided, the saturation current density of the device is reduced by reasonably optimizing the structure of the device, and the short-circuit safe working area of the device is improved; the electric field concentration effect at the bottom of the groove is improved, and the breakdown voltage of the device is improved; the grid capacitance of the device is reduced, the switching speed of the device is improved, and the switching loss is reduced; the problems of current, voltage oscillation and EMI in the dynamic starting process are avoided, and the reliability of the device is improved; the carrier enhancement effect of the emitter terminal of the device is further improved, and the carrier concentration distribution of the whole N-drift region and the compromise between the forward conduction voltage drop and the switching loss are improved. And the manufacturing method is compatible with the manufacturing process of the existing CSTBT device.
In order to solve the technical problems, the technical scheme provided by the invention is as follows:
the first technical scheme is as follows:
in one aspect, the present invention provides a trench gate charge storage type igbt, wherein a cell structure of the igbt includes: the drift region comprises a P-type collector region 12, a collector metal 13 positioned on the back side of the P-type collector region 12, an N-type electric field stop layer 11 positioned on the front side of the P-type collector region 12 and an N-type drift region 10 positioned above the N-type electric field stop layer 11; the N-type drift region 10 is provided with an N + emitter region 3, a P + emitter region 4, a P-type base region 5, an N-type charge storage layer 6, a P-type body region 71 and a trench gate structure; the groove gate structure partially penetrates into the N-type drift region 10 along the vertical direction of the device; the P-type body region 71 is positioned on one side of the trench gate structure, the P-type base region 5 is positioned on the other side of the trench gate structure, and the junction depth of the P-type body region 71 is greater than that of the P-type base region 5; the top layer of P type base region 5 has N + emitter region 3 and P + emitter region 4 of mutual contact, and N + emitter region 3 and P + emitter region 4 set up side by side and link to each other with the first emitter metal 101 of top, and N type charge storage layer 6 is located between P type base region 5 and N type drift region 10, the trench gate structure includes: the transistor comprises a gate electrode 81, a first gate dielectric layer 83 and a second gate dielectric layer 84, wherein the gate electrode 81 is isolated from an N + emitter region 3, a P-type base region 5 and an N-type charge storage layer 6 through the second gate dielectric layer 84, and the gate electrode 81 is isolated from an upper first emitter metal 101 through a second dielectric layer 1402, and the transistor is characterized in that: the depth of the gate electrode 81 is greater than the P-type base region 5 and less than the junction depth of the N-type charge storage layer 6; the trench gate structure further includes: a split electrode 82, a first split electrode dielectric layer 85, and a second split electrode dielectric layer 86; the split electrode 82 is connected with the upper first emitter metal 101, the split electrode 82 is L-shaped and is arranged to be arranged to surround the gate electrode 81 in a half mode, the split electrode 82 is separated from the gate electrode 81 through the first gate dielectric layer 83, and the depth of the split electrode 82 is larger than that of the gate electrode 81; the split electrode 82 is isolated from the N-type drift region 10 through a first split electrode dielectric layer 85, and the depth of the split electrode 82 is greater than the junction depth of the N-type charge storage layer 6; the split electrode 82 is isolated from the P-type body region 71 by a second split electrode dielectric layer 86;
the P-type body region 71 is also provided with a series diode structure 2 connected with the first emitter metal 101, and part of the series diode structure 2 is isolated from the P-type body region 71 through a first medium layer 1401.
Further, the junction depth of the P-type body region 71 is larger than that of the N-type charge storage layer 6, and the bottom of the P-type body region 71 extends laterally to surround the bottom of the trench gate structure to form a P-type layer.
Furthermore, the series diode structure adopts a PN junction diode, a Schottky diode or a Zener diode structure. When the PN junction diode and the Schottky diode are adopted, the anode/cathode connection modes of the diodes are the same, and the specific details are shown in the embodiment, and the number of the serially connected diode structures can be 1, 2 or more; when the zener diode structure is adopted, the anode/cathode connection of the diode is opposite to the connection of the two diode structures of the PN junction diode and the schottky diode, and it is generally sufficient to adopt one zener diode structure.
According to an embodiment of the present invention, the series diode structure of the present invention includes a first P-type doped region 21, a first N-type doped region 22, a second N-type doped region 23, and a second P-type doped region 24; wherein: the first P-type doped region 21 is in contact with the P-type body region 71, and the first N-type doped region 22, the second N-type doped region 23 and the second P-type doped region 24 are isolated from the P-type body region 71 through a first dielectric layer 1401; the first P-type doped region 21 is adjacent to the first N-type doped region 22 and contacts with the first N-type doped region to form a first PN junction diode, the second N-type doped region 23 is adjacent to the second P-type doped region 24 and contacts with the second P-type doped region to form a second PN junction diode, and the first PN junction diode and the second PN junction diode are connected through the floating metal layer 15.
Furthermore, the thicknesses of the first gate dielectric layer 83, the second gate dielectric layer 84, the first split electrode dielectric layer 85 and the second split electrode dielectric layer 86 may be the same or different.
Furthermore, the depth of the trench gate structure is less than or equal to the junction depth of the P-type body region.
Furthermore, the depth of the trench emitter structure (9) is less than or equal to the junction depth of the P-type body region.
Further, the drift region structure in the invention is an NPT structure or an FS structure.
Furthermore, the semiconductor material of the IGBT device adopts Si, SiC, GaAs or GaN, the groove filling material adopts polycrystalline Si, SiC, GaAs or GaN, and each part can adopt the same material or different materials.
The second technical scheme is as follows:
a trench gate charge storage type Insulated Gate Bipolar Transistor (IGBT) comprises a cell structure comprising:
the drift region comprises a P-type collector region 12, a collector metal 13 positioned on the back side of the P-type collector region 12, an N-type electric field stop layer 11 positioned on the front side of the P-type collector region 12 and an N-type drift region 10 positioned above the N-type electric field stop layer 11; the N-type drift region 10 is provided with an N + emitter region 3, a P + emitter region 4, a P-type base region 5, an N-type charge storage layer 6, a P-type body region 71 and a trench gate structure; the groove gate structure partially penetrates into the N-type drift region 10 along the vertical direction; the P-type body region 71 is positioned on one side of the trench gate structure, the P-type base region 5 is positioned on the other side of the trench gate structure, and the junction depth of the P-type body region 71 is greater than that of the P-type base region 5; the top layer of P type base region 5 has N + emitter region 3 and P + emitter region 4 of mutual contact, and N + emitter region 3 and P + emitter region 4 set up side by side and link to each other with the first emitter metal 101 of top, and N type charge storage layer 6 is located between P type base region 5 and N type drift region 10, the trench gate structure includes: the transistor comprises a gate electrode 81, a first gate dielectric layer 83 and a second gate dielectric layer 84, wherein the gate electrode 81 is isolated from an N + emitter region 3, a P-type base region 5 and an N-type charge storage layer 6 through the second gate dielectric layer 84, and the gate electrode 81 is isolated from an upper first emitter metal 101 through a second dielectric layer 1402, and the transistor is characterized in that: the depth of the gate electrode 81 is greater than the P-type base region 5 and less than the junction depth of the N-type charge storage layer 6; the trench gate structure further includes: a split electrode 82, a first split electrode dielectric layer 85, and a second split electrode dielectric layer 86; the split electrode 82 is connected with the upper first emitter metal 101, the split electrode 82 is separated from the gate electrode 81 through the first gate dielectric layer 83, and the depth of the split electrode 82 is larger than that of the gate electrode 81; the split electrode 82 is L-shaped and is arranged to semi-surround the gate electrode 81, the split electrode 82 is separated from the gate electrode 81 through a first gate dielectric layer 83, and the depth of the split electrode 82 is greater than that of the gate electrode 81; the split electrode 82 is isolated from the N-type drift region 10 through a first split electrode dielectric layer 85, and the depth of the split electrode 82 is greater than the junction depth of the N-type charge storage layer 6; the split electrode 82 is isolated from the P-type body region 71 by a second split electrode dielectric layer 86;
the top layer of the N-type drift region 10 is also provided with a floating P-type body region 72 which is isolated from the P-type body region 71 through the trench emitter structure 9, and the junction depth of the floating P-type body region 72 is greater than that of the N-type charge storage layer 6; a series diode structure 2 connected with a first emitter metal 101 is arranged above a P-type body region 71 between the trench emitter structure 9 and the trench gate structure, and part of the series diode structure 2 is isolated from the P-type body region 71 through a first dielectric layer 1401; a trench emitter structure 9 penetrates into the P-type body region 71 in a vertical direction, said trench emitter structure 9 comprising: the trench emitter comprises a trench emitter dielectric layer 91 and a trench emitter 92, wherein the side surface and the bottom surface of the trench emitter 92 are both surrounded by the trench emitter dielectric layer 91; the trench emitter 92 has a second metal emitter 102 connected thereto, the floating P-type body region 72 has a third dielectric layer 1403 connected thereto, the third dielectric layer 1403 is connected to the second metal emitter 102, and the second metal emitter 102 is isolated from the series diode structure 2 by a fourth dielectric layer 1404.
Further, the junction depth of the P-type body region 71 is larger than that of the N-type charge storage layer 6, and the bottom of the P-type body region 71 extends laterally to surround the bottom of the trench gate structure to form a P-type layer.
Furthermore, the series diode structure adopts a PN junction diode, a Schottky diode or a Zener diode structure. When the PN junction diode and the Schottky diode are adopted, the anode/cathode connection modes of the diodes are the same, and the specific details are shown in the embodiment, and the number of the serially connected diode structures can be 1, 2 or more; when the zener diode structure is adopted, the anode/cathode connection of the diode is opposite to the connection of the two diode structures of the PN junction diode and the schottky diode, and it is generally sufficient to adopt one zener diode structure.
According to an embodiment of the present invention, the series diode structure of the present invention includes a first P-type doped region 21, a first N-type doped region 22, a second N-type doped region 23, and a second P-type doped region 24; wherein: the first P-type doped region 21 is in contact with the P-type body region 71, and the first N-type doped region 22, the second N-type doped region 23 and the second P-type doped region 24 are isolated from the P-type body region 71 through a first dielectric layer 1401; the first P-type doped region 21 is adjacent to the first N-type doped region 22 and contacts with the first N-type doped region to form a first PN junction diode, the second N-type doped region 23 is adjacent to the second P-type doped region 24 and contacts with the second P-type doped region to form a second PN junction diode, and the first PN junction diode and the second PN junction diode are connected through the floating metal layer 15.
Furthermore, the thicknesses of the first gate dielectric layer 83, the second gate dielectric layer 84, the first split electrode dielectric layer 85 and the second split electrode dielectric layer 86 may be the same or different.
Furthermore, the depth of the trench gate structure is less than or equal to the junction depth of the P-type body region.
Furthermore, the depth of the trench emitter structure (9) is less than or equal to the junction depth of the P-type body region.
Further, in the present invention, the trench emitter structure 9 penetrates through the entire floating P-type body region 72 in the vertical direction or penetrates through a part of the floating P-type body region 72 in the vertical direction.
Further, the drift region structure in the invention is an NPT structure or an FS structure.
Furthermore, the semiconductor material of the IGBT device adopts Si, SiC, GaAs or GaN, the groove filling material adopts polycrystalline Si, SiC, GaAs or GaN, and each part can adopt the same material or different materials.
On the other hand, the invention provides a manufacturing method of a trench gate charge storage type insulated gate bipolar transistor, which is characterized by comprising the following steps:
step 1: an N-type lightly doped monocrystalline silicon wafer is used as an N-type drift region 10 of a device, a field oxide layer grows on the surface of the silicon wafer, an active region is obtained through photoetching, then a pre-oxide layer grows, and N-type impurities are injected into one side of the top layer of the silicon wafer through ion injection to obtain an N-type charge storage layer 6; continuing to inject P-type impurities above the N-type charge storage layer 6, at the central position of the top layer of the silicon wafer and at the other side of the top layer of the silicon wafer respectively through ion injection, and respectively preparing a P-type base region 5, a P-type body region 71 and a floating P-type body region 72 through annealing treatment; the junction depth of the P-type body region 71 and the junction depth of the floating P-type body region 71 are both greater than the junction depth of the N-type charge storage layer 6;
step 2: depositing a protective layer on the surface of a silicon wafer, photoetching a window to perform groove silicon etching, further etching and forming a first groove and a second groove which are mutually independent on the N-type drift region 10, wherein the depth of the first groove is less than or equal to the junction depth of the P-type body region 71, the depth of the second groove is less than or equal to the junction depth of the floating P-type body region 72, and removing the protective layer after the groove etching is finished;
and step 3: respectively forming dielectric layers on the inner walls of the first groove and the second groove, then respectively depositing polycrystalline silicon in the first groove and the second groove, wherein the dielectric layer on the inner wall of the second groove and the polycrystalline silicon in the dielectric layer jointly form a groove emitter structure 9;
and 4, step 4: etching a part of the dielectric layer and a part of the polycrystalline silicon on the inner wall of the first groove by adopting a photoetching process to form a third groove, wherein the depth of the third groove is less than the junction depth of the P-type base region 5 and greater than the junction depth of the N-type charge storage layer 6, and the width of the third groove is less than the width of the bottom of the first groove; the etched residual polysilicon in the first groove is used as a split electrode 82, and the etched residual oxide layer in the first groove is used as a split electrode dielectric layer;
and 5: growing a gate dielectric layer on the inner wall of the third groove, and then depositing polycrystalline silicon in the third groove to form a gate electrode 81, wherein the depth of the lower surface of the gate electrode 81 is smaller than the junction depth of the P-type base region 5 and larger than the junction depth of the N-type charge storage layer 6; the split electrode dielectric layer, the split electrode 82, the gate dielectric layer on the inner wall of the third trench and the gate electrode 81 form a trench gate structure together;
step 6: respectively injecting P-type impurities and N-type impurities into the top layer of the P-type base region 5 to obtain an N + emitter region 3 and a P + emitter region 4 which are mutually contacted and arranged side by side through photoetching and ion injection processes; the N-type emitting region 3 is connected with a gate electrode 81 through a gate dielectric layer;
and 7: depositing a dielectric layer on the surface of the device, and forming a third dielectric layer 1403 positioned on the upper surface of the floating P-type body region 72, a fourth dielectric layer 1404 positioned on the upper surface of a dielectric layer on the inner wall of a second groove arranged close to the inner side of the device, a first dielectric layer 1401 positioned on the upper surface of the P-type body region 71 and a second dielectric layer 1402 positioned on the upper surfaces of the gate electrode 81 and the gate dielectric layer by photoetching and etching;
and 8: growing N-type epitaxial layers on the surfaces of a P-type body region 71 and a first medium layer 1401, and preparing a first P-type doped region 21, a first N-type doped region 22, a second P-type doped region 23 and a second N-type doped region 24 which are all located on the upper surface of the first medium layer 1401 through photoetching and ion implantation processes; one side of the first P-type doped region 21 is in contact with the fourth dielectric layer 1404, the other side thereof is in contact with the first N-type doped region 22 and the first dielectric layer 1401, and the second N-type doped region 23 is in contact with the second P-type doped region 24;
and step 9: etching to remove the redundant N-type epitaxial layer, depositing metal on the surface of the device, forming a second emitter metal 102 connected with the upper surface of the trench emitter structure 9 between the third dielectric layer 1403 and the fourth dielectric layer 1404 by adopting photoetching and etching processes, forming a floating metal layer 15 between the first N-type doped region 22 and the second P-type doped region 23, and forming a first emitter metal 101 on the upper surfaces of the split electrode 82, the N + emitter region 4 and the P + emitter region 5;
step 10: and turning over the silicon wafer, reducing the thickness of the silicon wafer, injecting N-type impurities into the back of the silicon wafer, annealing to manufacture an N-type field stop layer 11 of the device, injecting P-type impurities into the back of the N-type field stop layer 11 to form a P-type collector region 12, and depositing metal on the back to form collector metal 13.
Furthermore, in step 1 of the present invention, the P-type base region 5, the P-type body region 71 and the floating P-type body region 72 can be formed by adding a photolithography step in three times.
Further, the preparation of the N-type field stop layer 11 in the step 10 of the present invention may be performed before the preparation of the front structure of the device; or a double-layer epitaxial material with the N-type field stop layer 11 and the N-type drift region 10 can be directly selected as a silicon wafer material for starting the process.
Furthermore, the materials of the dielectric layers 1401 to 1404 may be the same or different. According to the invention, by introducing and reasonably arranging the split electrode, the split electrode dielectric layer, the groove emitter structure, the series diode, the floating P-type body region and the P-type layer, the comprehensive performance of the device is obviously improved under the condition of not influencing the threshold voltage and the turn-on performance of the device, and the invention principle of the invention is explained in detail as follows:
firstly, the split electrode with the same potential as the emitter is introduced into the trench gate structure, and the relationship between the split electrode and the rest structures is reasonably set, so that the depth of the gate electrode is greater than the junction depth of the P-type base region and less than the junction depth of the N-type charge storage layer. The technical means reduces the whole grid capacitance under the condition of not influencing the turn-on of the IGBT device, meanwhile, the coupling of the bottom of the grid electrode and the collector electrode is shielded by the split electrode, the grid-collector electrode capacitance is converted into the grid-emitter electrode capacitance, the grid-collector electrode capacitance is further reduced, the switching speed of the device is improved, and the switching loss and the driving loss are reduced.
According to the invention, the split electrode and the emitter are equipotential, so that on one hand, the N-type semiconductor surface in contact with the split electrode dielectric layer can not form electron accumulation in the dynamic starting process of the device, and the P-type semiconductor surface in contact with the split electrode dielectric layer can not form an inversion layer, so that the device can not generate a negative differential capacitance effect, the problems of current, voltage oscillation and EMI in the dynamic switching process are avoided, and the reliability of the device is further improved. On the other hand, due to the introduction of the split electrode with the same electric potential as the emitter, the concentration of carriers near the split electrode is reduced, the reduction of the concentration of the carriers near the split electrode can be compensated by the existence of the N-type charge storage layer, and the problem that the forward conduction voltage drop of the device is sharply increased due to the introduction of the split electrode, so that the characteristic of the device is poor is solved.
Fig. 1 shows a conventional CSTBT device structure, and the CSTBT device based on this structure has a forward conduction performance that can be improved with the continuous increase of the doping concentration of the N-type charge storage layer, but also has a breakdown voltage performance that is damaged, particularly in that the breakdown voltage is significantly reduced. In order to effectively shield the adverse effect of the N-type charge storage layer, a thicker dielectric layer is introduced below the split electrode, in the manufacturing process step of the trench gate structure, the dielectric layers at the periphery of the split electrode and the periphery of the gate electrode are formed step by step, the thick dielectric layer at the periphery of the split electrode can improve the electric field concentration effect at the bottom of the trench gate, the breakdown voltage of the device is favorably improved, the reliability of the device is further improved, meanwhile, the existence of the split electrode can avoid the contradiction relation between the conduction voltage and the breakdown voltage caused by the increase of the doping concentration of the N-type charge storage layer, namely, the invention can not reduce the breakdown voltage while increasing the doping concentration of the N-type charge storage layer to reduce the conduction voltage. On the other hand, the junction depth of the P-type body region exceeds the junction depth of the N-type charge storage layer 6 and laterally diffuses to form a P-type layer, the N-type drift region 10 below the N-type charge storage layer 6 is completely consumed due to the lateral extension of the P-type layer, and therefore almost all reverse voltage is borne by a junction region formed by the P-type layer and the N-type charge storage layer 6, the breakdown voltage of the device is prevented from being affected no longer due to the fact that the doping concentration of the charge storage layer 6 is increased, and the problem that the forward conduction performance and the voltage resistance performance of the device are contradictory due to the fact that the doping concentration of the.
Third, the series diode structure 2 is introduced above the P-type body area 71 of the device, forward conduction is achieved under the condition that threshold voltage and turn-on of an IGBT device are not affected, the potential of the P-type body area 71 is increased along with the increase of collector voltage, when the IGBT is in a normal conduction state, the potential of the P-type body area 71 is lower than conduction voltage drop VDC of the series diode structure due to the fact that the collector voltage is lower, no current flows through the diode series structure, and the device characteristic is the same as that of a traditional CSTBT structure; when the IGBT is in a short circuit state, the collector voltage is large, the potential of the P-type body region 71 rises to exceed the conduction voltage drop VDC of the series diode structure, and the series diode structure is turned on, so that the potential of the P-type body region 71 is clamped at VDC, and the device channel voltage is clamped at a small value, thereby reducing the saturation current density of the IGBT device; in addition, the split electrode portion below the gate electrode 81 is beneficial to reducing the channel density of the MOSFET, and further reducing the saturation current density of the device, thereby improving the short-circuit safe operating area characteristic of the device.
In the invention, the floating P-type body region 72 isolated from the P-type body region 71 is formed by further arranging the groove emitter structure, the existence of the floating P-type body region reduces the extraction area of a cavity, enhances the conductivity modulation effect, simultaneously improves the carrier enhancement effect of an emitter terminal, further improves the carrier concentration distribution of the whole N-type drift region, and thus optimizes the compromise relationship between forward conduction voltage drop and switching loss.
Compared with the prior art, the invention has the following beneficial effects:
the invention provides a novel CSTBT device and a manufacturing method thereof through improvement on the structure of the traditional CSTBT device. The device structure is reasonably designed to comprehensively improve the performance of the device, and the series diode structure is introduced above the P-type body region, so that when the potential of the P-type body region is higher than the conduction voltage drop of the series diode structure in the conduction state of the device, the channel voltage of the MOS structure is clamped at a small value by the series diode structure, the saturation current density of the device is reduced, the short-circuit safe working area is improved, and the conduction loss is reduced; by reducing the depth of the gate electrode, the depth of the gate electrode is smaller than the junction depth of the N-type charge storage layer, so that the gate-emitter capacitance and the gate-collector capacitance are reduced, the switching speed of the device is improved, and the switching loss is reduced; the existence of the split electrode reduces the density of an MOS channel and further reduces the saturation current density of the device, and the dielectric layer around the split electrode improves the electric field concentration effect at the bottom of the groove, improves the breakdown voltage of the device and improves the reliability of the device; because the split electrode and the emitter metal have the same potential, in the dynamic starting process of the device, the surface of an N-type semiconductor (an N-type charge storage layer and an N-drift region) in contact with the split electrode dielectric layer cannot form electron accumulation, and the surface of a P-type semiconductor (a P-type body region) in contact with the split electrode dielectric layer cannot form an inversion layer, so that the device cannot generate a negative differential capacitance effect, the problems of current, voltage oscillation and EMI in the dynamic starting process are avoided, and the reliability of the device is further improved; the floating P-type body region further improves the carrier enhancement effect of the emitter terminal of the device, improves the carrier concentration distribution of the whole N-drift region, and further improves the compromise between the forward conduction voltage drop and the switching loss. In addition, the structure provided by the invention can overcome the defects of compromised characteristics of switching performance, conduction voltage drop and switching loss and reliability of the device caused by deepening the depth of the trench gate and reducing the width of the cell in the prior art. And the manufacturing method of the invention is compatible with the manufacturing process of the existing traditional CSTBT device.
Drawings
FIG. 1 is a schematic diagram of a cell structure of a conventional CSTBT device; wherein: 1 is emitter metal, 3 is an N + emitter region, 4 is a P + emitter region, 5 is a P-type base region, 6 is an N-type charge storage layer, 71 is a P-type body region, 81 is a gate electrode, 10 is an N-type drift region, 11 is an N-type electric field stop layer, 12 is a P-type collector region, 13 is collector metal, and 14 is a dielectric layer.
Fig. 2 is a schematic diagram of a cell structure of a CSTBT device provided in embodiment 1;
FIG. 3 is a schematic diagram of a CSTBT device cell structure provided in embodiment 2;
FIG. 4 is a schematic diagram of a CSTBT device cell structure provided in embodiment 3;
FIG. 5 is a schematic diagram of a CSTBT device cell structure provided in embodiment 4;
in fig. 2 to 5: 101 is a first emitter metal, 102 is a second emitter metal, 2 is a series diode structure, 21 is a first P-type doped region, 22 is a first N-type doped region, 23 is a second N-type doped region, 24 is a second P-type doped region, 3 is an N + emitter region, 4 is a P + emitter region, 5 is a P-type base region, 6 is an N-type charge storage layer, 71 is a P-type body region, 72 is a floating P-type body region, 81 is a gate electrode, 82 is a split electrode, 83 is a first gate dielectric layer, 84 is a second gate dielectric layer, 85 is a first split electrode dielectric layer, 86 is a second split electrode dielectric layer, 9 is a trench emitter structure, 91 is a trench emitter dielectric layer, 92 is a trench emitter, 10 is an N-type drift region, 11 is an N-type electric field stop layer, 12 is a P-type collector region, 13 is a collector metal, 1401 is a first dielectric layer, 1402 is a second dielectric layer, 1403 is a third dielectric layer, reference numeral 1404 denotes a fourth dielectric layer, and 15 denotes a floating metal layer.
Fig. 6 is a schematic structural diagram after a dielectric layer is formed on the inner wall of the trench in the manufacturing method according to embodiment 2 of the present invention;
fig. 7 is a schematic structural diagram after polysilicon is deposited in the trench in the manufacturing method provided in embodiment 2 of the present invention;
fig. 8 is a schematic structural diagram of the manufacturing method according to embodiment 2 after etching a part of the oxide layer and a part of the polysilicon in the first trench;
fig. 9 is a schematic structural diagram after a gate dielectric layer is formed on the inner wall of the third trench in the manufacturing method according to embodiment 2 of the present invention;
fig. 10 is a schematic structural view after a gate electrode is formed in a third trench in the manufacturing method according to embodiment 2 of the present invention;
fig. 11 is a schematic structural diagram after forming the N + emitter region 4 and the P + emitter region 5 in the manufacturing method provided in embodiment 2 of the present invention;
fig. 12 is a schematic structural diagram after a dielectric layer is formed on the surface of a device in the manufacturing method provided in embodiment 2 of the present invention;
fig. 13 is a schematic structural diagram of a series diode structure formed on a device surface in the manufacturing method provided in embodiment 2 of the present invention;
fig. 14 is a schematic structural diagram after an emitter electrode and a floating electrode are formed on the surface of a device in the manufacturing method provided in embodiment 2 of the present invention;
fig. 15 is a schematic view of a device structure formed after completion of all steps in the manufacturing method provided in embodiment 2 of the present invention;
fig. 16 is a schematic structural diagram illustrating a gate dielectric layer formed on an inner wall of the third trench in the manufacturing method according to embodiment 3 of the present invention;
fig. 17 is a schematic structural diagram after etching the excess polysilicon and the oxide layer to form the first split electrode in the manufacturing method according to embodiment 4 of the present invention;
fig. 18 is a schematic structural view of a split electrode dielectric layer formed after a first split electrode is formed in the manufacturing method according to embodiment 4 of the present invention;
fig. 19 is a schematic structural diagram after polysilicon is deposited in the first split electrode and split electrode dielectric layer in the manufacturing method provided in embodiment 4 of the present invention;
fig. 20 is a schematic structural diagram of forming a second split electrode after etching a part of the oxide layer and a part of the polysilicon in the manufacturing method according to embodiment 4 of the present invention;
fig. 21 is a schematic structural diagram of a device after a gate dielectric layer is formed in the manufacturing method provided in embodiment 4 of the present invention;
fig. 22 is a schematic structural diagram of a device after a polysilicon gate electrode is formed in the manufacturing method provided in embodiment 4 of the present invention.
Detailed Description
The principles and features of the present invention are described in detail below with reference to the accompanying drawings and specific embodiments:
example 1:
in this embodiment, a trench gate charge storage type igbt is provided as shown in fig. 2, and the cell structure of the igbt includes: the drift region comprises a P-type collector region 12, a collector metal 13 positioned on the back side of the P-type collector region 12, an N-type electric field stop layer 11 positioned on the front side of the P-type collector region 12 and an N-type drift region 10 positioned above the N-type electric field stop layer 11; the N-type drift region 10 is provided with an N + emitter region 3, a P + emitter region 4, a P-type base region 5, an N-type charge storage layer 6, a P-type body region 71 and a trench gate structure; the groove gate structure partially penetrates into the N-type drift region 10 along the vertical direction of the device; the P-type body region 71 is positioned on one side of the trench gate structure, the P-type base region 5 is positioned on the other side of the trench gate structure, and the junction depth of the P-type body region 71 is greater than that of the P-type base region 5; the top layer of P type base region 5 has N + emitter region 3 and P + emitter region 4 of mutual contact, and N + emitter region 3 and P + emitter region 4 set up side by side and link to each other with the first emitter metal 101 of top, and N type charge storage layer 6 is located between P type base region 5 and N type drift region 10, the trench gate structure includes: the transistor comprises a gate electrode 81, a first gate dielectric layer 83 and a second gate dielectric layer 84, wherein the gate electrode 81 is isolated from an N + emitter region 3, a P-type base region 5 and an N-type charge storage layer 6 through the second gate dielectric layer 84, and the gate electrode 81 is isolated from an upper first emitter metal 101 through a second dielectric layer 1402, and the transistor is characterized in that: the depth of the gate electrode 81 is greater than the P-type base region 5 and less than the junction depth of the N-type charge storage layer 6; the trench gate structure further includes: a split electrode 82, a first split electrode dielectric layer 85, and a second split electrode dielectric layer 86; the split electrode 82 is connected with the first emitter metal 101 above and has the same potential as the emitter metal 1, the split electrode 82 is L-shaped and is arranged to be semi-surrounded by the gate electrode 81, the split electrode 82 is isolated from the gate electrode 81 through the first gate dielectric layer 83, and the depth of the split electrode 82 is greater than that of the gate electrode 81; the split electrode 82 is isolated from the N-type drift region 10 through a first split electrode dielectric layer 85, and the depth of the split electrode 82 is greater than the junction depth of the N-type charge storage layer 6; the width of the part of the split electrode 82 located below the gate electrode 81 is greater than the sum of the width of the upper part of the split electrode and the thickness of the first gate dielectric layer 83 and is less than the sum of the width of the upper part of the split electrode, the thickness of the first gate dielectric layer 83 and the width of the gate electrode 81, and the split electrode 82 is isolated from the P-type body region 71 through the second split electrode dielectric layer 86; the P-type body region 71 is also provided with a series diode structure 2 connected with the first emitter metal 101, and part of the series diode structure 2 is isolated from the P-type body region 71 through a first medium layer 1401.
Example 2:
the present embodiment proposes a trench gate charge storage type igbt as shown in fig. 3, which includes a P-type collector region 12, a collector metal 13 located on the back of the P-type collector region 12, an N-type electric field blocking layer 11 located on the front of the P-type collector region 12, and an N-type drift region 10 located above the N-type electric field blocking layer 11; the N-type drift region 10 is provided with an N + emitter region 3, a P + emitter region 4, a P-type base region 5, an N-type charge storage layer 6, a P-type body region 71 and a trench gate structure; the groove gate structure partially penetrates into the N-type drift region 10 along the vertical direction; the P-type body region 71 is positioned on one side of the trench gate structure, the P-type base region 5 is positioned on the other side of the trench gate structure, and the junction depth of the P-type body region 71 is greater than that of the P-type base region 5; the top layer of the P-type base region 5 is provided with an N + emitter region 3 and a P + emitter region 4 which are mutually contacted, the N + emitter region 3 and the P + emitter region 4 are arranged side by side and are connected with the first emitter metal 101 above, the N-type charge storage layer 6 is positioned between the P-type base region 5 and the N-type drift region 10, and the junction depth of the N-type charge storage layer 6 is smaller than that of the P-type body region 71; the trench gate structure includes: the transistor comprises a gate electrode 81, a first gate dielectric layer 83 and a second gate dielectric layer 84, wherein the gate electrode 81 is isolated from an N + emitter region 3, a P-type base region 5 and an N-type charge storage layer 6 through the second gate dielectric layer 84, and the gate electrode 81 is isolated from an upper first emitter metal 101 through a second dielectric layer 1402, and the transistor is characterized in that: the depth of the gate electrode 81 is greater than the P-type base region 5 and less than the junction depth of the N-type charge storage layer 6; the trench gate structure further includes: a split electrode 82, a first split electrode dielectric layer 85, and a second split electrode dielectric layer 86; the split electrode 82 is connected with the upper first emitter metal 101, the split electrode 82 is separated from the gate electrode 81 through the first gate dielectric layer 83, and the depth of the split electrode 82 is larger than that of the gate electrode 81; the width of the part of the split electrode 82 located below the gate electrode 81 is greater than the sum of the width of the upper part of the split electrode and the thickness of the first gate dielectric layer 83 and is less than the sum of the width of the upper part of the split electrode, the thickness of the first gate dielectric layer 83 and the width of the gate electrode 81, and the depth of the split electrode 82 is greater than the junction depth of the N-type charge storage layer 6; the split electrode 82 is isolated from the N-type drift region 10 by a first split electrode dielectric layer 85, and the split electrode 82 is isolated from the P-type body region 71 by a second split electrode dielectric layer 86;
the top layer of the N-type drift region 10 is also provided with a floating P-type body region 72 which is isolated from the P-type body region 71 through the trench emitter structure 9, and the junction depth of the floating P-type body region 72 is greater than that of the N-type charge storage layer 6; a series diode structure 2 connected with a first emitter metal 101 is arranged above a P-type body region 71 between the trench emitter structure 9 and the trench gate structure, and part of the series diode structure 2 is isolated from the P-type body region 71 through a first dielectric layer 1401; a trench emitter structure 9 penetrates into the P-type body region 71 in a vertical direction, said trench emitter structure 9 comprising: the trench emitter comprises a trench emitter dielectric layer 91 and a trench emitter 92, wherein the side surface and the bottom surface of the trench emitter 92 are both surrounded by the trench emitter dielectric layer 91; the trench emitter 92 has a second metal emitter 102 connected thereto, the floating P-type body region 72 has a third dielectric layer 1403 connected thereto, the third dielectric layer 1403 is connected to the second metal emitter 102, and the second metal emitter 102 is isolated from the series diode structure 2 by a fourth dielectric layer 1404.
Example 3:
this embodiment is similar to embodiment 2 except that the thicknesses of the split electrode dielectric layers (i.e., the first split electrode dielectric layer 85 and the second split electrode dielectric layer 86) are greater than the thicknesses of the gate dielectric layers (i.e., the first gate dielectric layer 83 and the second gate dielectric layer 84).
As shown in fig. 1, the structure of the conventional trench gate charge storage type insulated gate bipolar transistor is shown, a gate oxide layer is formed in a trench by one-time thermal oxidation, in order to ensure a certain threshold voltage, the thickness of the whole gate oxide layer is small, and the size of an MOS capacitor is inversely proportional to the thickness of the gate oxide layer, so that the gate capacitance of the device is greatly increased by the thickness of the thin gate oxide layer in the conventional CSTBT structure, and meanwhile, the breakdown voltage of the device is reduced by the electric field concentration effect at the bottom of the trench, so that the reliability of the device is poor. Therefore, compared with embodiment 2, this embodiment can further reduce the gate capacitance, and further improve the electric field concentration effect at the bottom of the trench, thereby increasing the breakdown voltage of the device and improving the reliability of the device.
Example 4:
this embodiment proposes a trench gate charge storage type igbt as shown in fig. 5, and the structure of this embodiment is the same as that of embodiment 2 except that the split-electrode and peripheral split-electrode dielectric layers are different from that of embodiment 2; in this embodiment, the split electrode includes a first split electrode and a second split electrode that are connected to each other, the first split electrode is located at the bottom of the trench and is prepared before the second split electrode, and since the width of the first split electrode is smaller than that of the second split electrode, the thickness of the dielectric layer connecting the first split electrode and the N-type charge storage layer 6 and the N-type drift region 10 is larger than the thickness of the dielectric layer connecting the second split electrode and the N-type charge storage layer and the N-type drift region 10.
Compared with embodiment 2, the embodiment can further reduce the gate capacitance, improve the electric field concentration effect at the bottom of the trench, improve the breakdown voltage of the device, and improve the reliability of the device.
Example 5:
the embodiment provides a manufacturing method of a trench gate charge storage type insulated gate bipolar transistor, which is characterized by comprising the following steps:
step 1: an N-type lightly doped monocrystalline silicon wafer is used as an N-type drift region 10 of the device, the thickness of the selected silicon wafer is 300-600 um, and the doping concentration is 1013～1014Per cm3；
Step 2: growing a field oxide layer on the surface of a silicon wafer, photoetching to obtain an active region, then growing a pre-oxide layer, and implanting N-type impurities into one side of the silicon wafer by ion implantation to obtain an N-type charge storage layer 6, wherein the energy of the ion implantation is 200-500 keV, and the implantation dosage is 1013～1014Per cm2(ii) a Continuing to implant P-type impurities above the N-type charge storage layer 6, at the central position of the silicon wafer and on the other side of the silicon wafer through ion implantation, and respectively preparing a P-type base region 5, a P-type body region 71 and a floating P-type body region 72 through annealing treatment, wherein the energy of the ion implantation is 60-120 keV, and the implantation dosage is 10 keV13～1014Per cm2Annealing at 1100-1150 deg.c for 10-30 min; the P-type base region 5 is positioned above the N-type charge storage layer 6, the P-type body region 71 is positioned in the center of the top layer of the N-type drift region 10, the floating P-type body region 72 is positioned on one side of the top layer of the N-type drift region 10, and the junction depth of the P-type body region 71 and the junction depth of the floating P-type body region 71 are both greater than that of the N-type charge storage layer 6;
and step 3: depositing a TEOS protective layer with the thickness of 700-1000 nm on the surface of a silicon wafer, performing groove silicon etching after a window is photoetched, and etching to form a first groove and a second groove which are independent from each other, wherein: the depth of the first groove is smaller than or equal to the junction depth of the P-type body area 71, the depth of the second groove is smaller than or equal to the junction depth of the floating P-type body area 72, and the TEOS protective layer is removed after the grooves are etched;
and 4, step 4: o at 1050-1150 deg.C2Oxide layers are respectively formed on the inner walls of the first groove and the second groove in the atmosphere to serve as a groove emitter dielectric 91, then polycrystalline silicon is deposited in the first groove and the second groove at 750-950 ℃ to serve as a groove emitter 92, and the oxide layer on the inner wall of the second groove and the polycrystalline silicon in the oxide layer jointly form a groove emitter structure 9;
and 5: etching part of the oxide layer on the inner wall of the first groove and part of the polycrystalline silicon in the oxide layer in the step 4 by adopting a photoetching process to form a third groove, wherein the depth of the third groove is less than the junction depth of the P-type base region 5 and greater than the junction depth of the N-type charge storage layer 6, and the width of the third groove is less than the width of the bottom of the first groove; forming a split electrode 82 by the polycrystalline silicon in the etched first groove, and taking an oxide layer in the etched first groove as a split electrode dielectric layer;
step 6: forming an oxide layer on the inner wall of the third groove by thermal oxidation, wherein the formed oxide layer is used as a gate dielectric layer, the thickness of the formed oxide layer is less than 120nm, then depositing polycrystalline silicon in the third groove at 750-950 ℃ to form a gate electrode 81, and the depth of the lower surface of the gate electrode 81 is less than the junction depth of the P-type base region 5 and greater than the junction depth of the N-type charge storage layer 6; the split electrode dielectric layer and the split electrode 82 therein, the gate dielectric layer on the inner wall of the third groove and the gate electrode 81 therein jointly form a groove gate structure;
and 7: injecting N-type impurities into one end of the top layer of the P-type base region 5 by adopting photoetching and ion injection processes to prepare an N + emitter region 3, wherein the energy of ion injection is 30-60 keV, and the injection dosage is 1015～1016Per cm2The N-type emitter region 3 is connected with a gate electrode 81 through a gate dielectric layer 34;
and 8: injecting P-type impurities into the other end of the top layer of the P-type base region 5 by adopting photoetching and ion injection processes to obtain a P + emitter region 4, and annealing, wherein the energy of ion injection is 60-80 keV, and the injection dosage is 1015～1016Per cm2Annealing at 900 ℃ for 20-30 minutes; the N + emission region 3 and the P + emission region 4 are arranged side by side;
and step 9: depositing a dielectric layer on the surface of the device, and forming a third dielectric layer 1403 positioned on the upper surface of the floating P-type body region 72, a fourth dielectric layer 1404 positioned on the upper surface of a dielectric layer on the inner wall of a second groove arranged close to the inner side of the device, a first dielectric layer 1401 positioned on the upper surface of the P-type body region 71 and a second dielectric layer 1402 positioned on the upper surfaces of the gate electrode 81 and the gate dielectric layer by photoetching and etching;
step 10: growing an N-type epitaxial layer on the surfaces of the P-type body region 71 and the first dielectric layer 1401 by photoetching and ion implantationPreparing a first P-type doped region 21 on the upper surface of the P-type body region 71, a first N-type doped region 22 on the upper surface of the first dielectric layer 1401, a second P-type doped region 23 and a second N-type doped region 24 by using a process and annealing treatment; the energy of ion implantation of N-type impurities is 30-60 keV, and the implantation dose is 1015～1016Per cm2The energy of ion implantation of P-type impurity is 60-80 keV, and the implantation dosage is 1015～1016Per cm2Annealing at 900 ℃ for 20-30 minutes; one side of the first P-type doped region 21 is in contact with the fourth dielectric layer 1404, the other side thereof is in contact with the first N-type doped region 22 and the first dielectric layer 1401, and the second N-type doped region 23 is in contact with the second P-type doped region 24;
step 11: etching to remove the redundant N-type epitaxial layer, depositing metal on the surface of the device, forming a second emitter metal 102 connected with the upper surface of the trench emitter structure 9 between the third dielectric layer 1403 and the fourth dielectric layer 1404 by adopting photoetching and etching processes, forming a floating metal layer 15 between the first N-type doped region 22 and the second P-type doped region 23, and forming a first emitter metal 101 on the upper surfaces of the split electrode 82, the N + emitter region 4 and the P + emitter region 5;
step 12: turning over the silicon wafer, reducing the thickness of the silicon wafer, injecting N-type impurities into the back of the silicon wafer, annealing and manufacturing an N-type field stop layer 11 of the device, wherein the energy of ion injection is 1500-2000 keV, and the injection dosage is 10 keV13～1014Per cm2The annealing temperature is 1200-1250 ℃, and the time is 300-600 minutes; implanting P-type impurities into the back of the N-type field stop layer 11 to form a P-type collector region 12 with an implantation energy of 40-60 keV and an implantation dose of 1012～1013Per cm2In H2And N2Carrying out back annealing in a mixed atmosphere at the temperature of 400-450 ℃ for 20-30 minutes; and depositing metal on the back to form a collector metal 13, thus finishing the preparation of the trench gate charge storage type IGBT.
Furthermore, in step 2 of the present invention, the P-type base region 5, the P-type body region 71 and the floating P-type body region 72 can be formed by adding a photolithography step in three times.
Further, in step 12 of the present invention, the N-type field stop layer 11 can be prepared before the front structure of the device is prepared; or a double-layer epitaxial material with the N-type field stop layer 11 and the N-type drift region 10 can be directly selected as a silicon wafer material for starting the process.
Further, the dielectric layers 1401 to 1404, the gate dielectric layer, the split electrode dielectric layer and the trench emitter dielectric 91 may be made of the same or different materials, and the gate dielectric layer or the split electrode dielectric layer may be made of different dielectric materials.
Further, the preparation of the first N-type field stop layer 11 in the process step may be omitted.
Example 6:
this embodiment is different from embodiment 4 in that: when the gate dielectric layer is formed by thermal oxidation, the growth time is controlled to be shorter than the growth time for forming the oxide layer at the bottom of the first trench by the thermal oxidation method, so that the thickness of the gate dielectric layer is smaller than the thickness of the oxide layer at the bottom of the first trench, and the device structure shown in fig. 4 can be obtained.
Example 7:
this embodiment is different from embodiment 4 in that: in step 4, a photolithography step is added to form the first split electrode 821, the second split electrode 822 and the stepped split electrode dielectric layer step by step, so as to obtain the device structure shown in fig. 5. The above operations are conventional operations in the art, and are not described herein again.

Claims (9)

1. A trench gate charge storage type Insulated Gate Bipolar Transistor (IGBT) comprises a cell structure comprising: the solar cell comprises a P-type collector region (12), collector metal (13) positioned on the back of the P-type collector region (12), an N-type electric field stop layer (11) positioned on the front of the P-type collector region (12) and an N-type drift region (10) positioned above the N-type electric field stop layer (11); the N-type drift region (10) is provided with an N + emitter region (3), a P + emitter region (4), a P-type base region (5), an N-type charge storage layer (6), a P-type body region (71) and a trench gate structure; the groove gate structure partially penetrates into the N-type drift region (10) along the vertical direction; the P-type body region (71) is positioned on one side of the trench gate structure, the P-type base region (5) is positioned on the other side of the trench gate structure, and the junction depth of the P-type body region (71) is greater than that of the P-type base region (5); the top layer of P type base region (5) has N + emitter region (3) and P + emitter region (4) of mutual contact, and N + emitter region (3) and P + emitter region (4) set up side by side and link to each other with first emitter metal (101) of top, and N type charge storage layer (6) are located between P type base region (5) and N type drift region (10), the ditch slot gate structure includes: the transistor comprises a gate electrode (81), a first gate dielectric layer (83) and a second gate dielectric layer (84), wherein the gate electrode (81) is isolated from an N + emitter region (3), a P-type base region (5) and an N-type charge storage layer (6) through the second gate dielectric layer (84), and the gate electrode (81) is isolated from an upper first emitter metal (101) through the second dielectric layer (1402), and the transistor is characterized in that: the depth of the gate electrode (81) is greater than the depth of the P-type base region (5) and less than the junction depth of the N-type charge storage layer (6); the trench gate structure further includes: a split electrode (82), a first split electrode dielectric layer (85), and a second split electrode dielectric layer (86); the split electrode (82) is connected with the upper first emitter metal (101), and the split electrode (82) is separated from the gate electrode (81) through a first gate dielectric layer (83) and has a depth larger than that of the gate electrode (81); the split electrode (82) is L-shaped and is arranged to be semi-surrounded with the gate electrode (81), the split electrode (82) is separated from the gate electrode (81) through a first gate dielectric layer (83), and the depth of the split electrode (82) is larger than that of the gate electrode (81); the split electrode (82) is isolated from the N-type drift region (10) through a first split electrode dielectric layer (85), and the depth of the split electrode (82) is larger than the junction depth of the N-type charge storage layer (6); the split electrode (82) is isolated from the P-type body region (71) through a second split electrode dielectric layer (86);
the top layer of the N-type drift region (10) is also provided with a floating P-type body region (72) which is isolated from the P-type body region (71) through a trench emitter structure (9), and the junction depth of the floating P-type body region (72) is greater than that of the N-type charge storage layer (6); a series diode structure (2) connected with first emitter metal (101) is arranged above a P-type body region (71) between the trench emitter structure (9) and the trench gate structure, and part of the series diode structure (2) is isolated from the P-type body region (71) through a first dielectric layer (1401); a trench emitter structure (9) penetrating into the P-type body region (71) in a vertical direction, the trench emitter structure (9) comprising: the trench emitter comprises a trench emitter dielectric layer (91) and a trench emitter (92), wherein the side surface and the bottom surface of the trench emitter (92) are surrounded by the trench emitter dielectric layer (91); a second metal emitter (102) connected with the trench emitter (92) is arranged above the trench emitter, a third dielectric layer (1403) connected with the floating P-type body region (72) is arranged above the floating P-type body region, the third dielectric layer (1403) is in contact with the second metal emitter (102), and the second metal emitter (102) is isolated from the series diode structure (2) through a fourth dielectric layer (1404);
the thicknesses of the first split electrode dielectric layer (85) and the second split electrode dielectric layer (86) are larger than the thicknesses of the first gate dielectric layer (83) and the second gate dielectric layer (84).
2. A trench gate charge storage type IGBT as claimed in claim 1, characterized in that the junction depth of the P-type body region (71) is greater than the junction depth of the N-type charge storage layer (6), and the bottom of the P-type body region (71) extends towards the N-type drift region (10) at the bottom of the trench gate structure to form a P-type layer.
3. The trench-gate charge storage insulated gate bipolar transistor of claim 1, wherein: the series diode structure comprises a first P-type doped region (21), a first N-type doped region (22), a second N-type doped region (23) and a second P-type doped region (24); wherein: the first P-type doped region (21) is in contact with the P-type body region (71), and the first N-type doped region (22), the second N-type doped region (23) and the second P-type doped region (24) are isolated from the P-type body region (71) through a first insulating medium layer (1401); the first P-type doped region (21) is adjacent to the first N-type doped region (22) and contacts with the first N-type doped region to form a first PN junction diode, the second N-type doped region (23) is adjacent to the second P-type doped region (24) and contacts with the second P-type doped region to form a second PN junction diode, and the first PN junction diode and the second PN junction diode are connected through a floating metal layer (15).
4. The trench-gate charge storage insulated gate bipolar transistor of claim 1, wherein: the depth of the trench gate structure is less than or equal to the junction depth of the P-type body region; the depth of the trench emitter structure (9) is less than or equal to the junction depth of the P-type body region.
5. The trench-gate charge storage insulated gate bipolar transistor of claim 1, wherein: the structure of the drift region (10) is an NPT structure or an FS structure.
6. The trench-gate charge storage insulated gate bipolar transistor of claim 1, wherein: the material of the trench gate charge storage type insulated gate bipolar transistor is Si, SiC, GaAs or GaN.
7. A manufacturing method of a trench gate charge storage type insulated gate bipolar transistor is characterized by comprising the following steps:
step 1: an N-type lightly doped monocrystalline silicon wafer is used as an N-type drift region (10) of a device, a field oxide layer grows on the surface of the silicon wafer, an active region is obtained through photoetching, then a pre-oxide layer grows, and N-type impurities are injected into one side of the top layer of the silicon wafer through ion injection to obtain an N-type charge storage layer (6); continuously injecting P-type impurities above the N-type charge storage layer (6), at the central position of the top layer of the silicon wafer and at the other side of the top layer of the silicon wafer respectively through ion injection, and respectively preparing a P-type base region (5), a P-type body region (71) and a floating P-type body region (72) through annealing treatment; the junction depth of the P-type body region (71) and the junction depth of the floating P-type body region (72) are both larger than the junction depth of the N-type charge storage layer (6);
step 2: depositing a protective layer on the surface of a silicon wafer, photoetching a window to perform groove silicon etching, further etching and forming a first groove and a second groove which are mutually independent on an N-type drift region (10), wherein the depth of the first groove is less than or equal to the junction depth of a P-type body region (71), the depth of the second groove is less than or equal to the junction depth of a floating P-type body region (72), and removing the protective layer after the groove etching is finished;
and step 3: respectively forming dielectric layers on the inner walls of the first groove and the second groove, then respectively depositing polycrystalline silicon in the first groove and the second groove, wherein the dielectric layer on the inner wall of the second groove and the polycrystalline silicon in the dielectric layer jointly form a groove emitter structure (9);
and 4, step 4: etching a part of the dielectric layer and a part of the polycrystalline silicon on the inner wall of the first groove by adopting a photoetching process to form a third groove, wherein the depth of the third groove is greater than the junction depth of the P-type base region (5) and less than the junction depth of the N-type charge storage layer (6), and the width of the third groove is less than the width of the bottom of the first groove; the etched residual first in-groove polycrystalline silicon is used as a split electrode (82), and the etched residual first in-groove oxide layer is used as a split electrode dielectric layer;
and 5: growing a gate dielectric layer on the inner wall of the third groove, and then depositing polycrystalline silicon in the third groove to form a gate electrode (81), wherein the depth of the lower surface of the gate electrode (81) is greater than the junction depth of the P-type base region (5) and less than the junction depth of the N-type charge storage layer (6); the split electrode dielectric layer, the split electrode (82), the gate dielectric layer on the inner wall of the third groove and the gate electrode (81) form a groove gate structure together; the thickness of the third groove inner wall dielectric layer is smaller than that of the first groove inner wall dielectric layer;
step 6: respectively injecting P-type impurities and N-type impurities into the top layer of the P-type base region (5) through photoetching and ion injection processes to obtain an N + emitter region (3) and a P + emitter region (4) which are mutually contacted and arranged side by side; the N + emitting region (3) is connected with a gate electrode (81) through a gate dielectric layer;
and 7: depositing a dielectric layer on the surface of the device, and forming a third dielectric layer (1403) positioned on the upper surface of the floating P-type body region (72), a fourth dielectric layer (1404) positioned on the upper surface of a dielectric layer on the inner wall of a second groove arranged close to the inner side of the device, a first dielectric layer (1401) positioned on the upper surface of the P-type body region (71) and a second dielectric layer (1402) positioned on the upper surfaces of a gate electrode (81) and a gate dielectric layer by adopting photoetching and etching;
and 8: growing an N-type epitaxial layer on the surfaces of the P-type body region (71) and the first dielectric layer (1401), and preparing a cathode and an anode doped region of the Zener diode on the upper surface of the P-type body region (71) through photoetching and ion implantation processes; the cathode doped region is in contact with the P-type body region (71), and the anode doped region is in contact with the first emitter metal (101);
and step 9: etching to remove the redundant N-type epitaxial layer, depositing metal on the surface of the device, forming second emitter metal (102) connected with the upper surface of the trench emitter structure (9) between the third dielectric layer (1403) and the fourth dielectric layer (1404) by adopting photoetching and etching processes, forming a floating metal layer (15) between the first N-type doped region (22) and the second P-type doped region (23), and forming first emitter metal (101) on the upper surfaces of the split electrode (82), the N + emitter region (4) and the P + emitter region (5);
step 10: and turning over the silicon wafer, reducing the thickness of the silicon wafer, injecting N-type impurities into the back of the silicon wafer, annealing to manufacture an N-type field stop layer (11) of the device, injecting P-type impurities into the back of the N-type field stop layer (11) to form a P-type collector region (12), and depositing metal on the back to form collector metal (13).
8. The method of claim 7, wherein the step of forming the trench-gate charge storage insulated-gate bipolar transistor comprises: in the step 1, a P-type base region (5), a P-type body region (71) and a floating P-type body region (72) are respectively formed in three times by adding a photoetching step.
9. The method of claim 7, wherein the step of forming the trench-gate charge storage insulated-gate bipolar transistor comprises: the preparation of the N-type field stop layer (11) in the step 10 is carried out before the preparation of the front structure of the device.
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