CN107768436A - A kind of trench gate electric charge memory type IGBT and its manufacture method - Google Patents
A kind of trench gate electric charge memory type IGBT and its manufacture method Download PDFInfo
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- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
- H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
- H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
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Abstract
A kind of trench gate electric charge memory type IGBT and its manufacture method, belong to semiconductor power device technology field, the present invention is by introducing the trench emitter structure being connected with PXing Ti areas in the N-type drift region of trench gate side in traditional C/S TBT devices, so as to which grid collector capacitance to be changed to the adverse effect for for gate emitter electric capacity, improving Miller capacitance；The thick dielectric layer of trench emitter structure avoids channel bottom electric field concentration effect, improves the breakdown voltage of device；The invention enables the junction depth that the depth of gate electrode is less than N-type charge storage layer, overall grid capacitance is reduced in the case where not influenceing IGBT and opening, the switching speed of device is improved, reduces the switching loss of device, improves the compromise characteristic between forward conduction voltage and turn-off power loss；The presence in ZhongPXing Ti areas of the present invention can reduce the extraction area in hole, improve the carrier concentration profile of whole N-type drift region；And present invention reduces influence of noise, avoids EMI effects.
Description
Technical field
The invention belongs to semiconductor power device technology field, more particularly to a kind of insulated gate bipolar transistor
(IGBT), and in particular to a kind of trench gate electric charge memory type IGBT and its manufacture method.
Background technology
Insulated gate bipolar transistor (IGBT) is as one of core electron component in modern power electronic circuit, quilt
It is widely used in the every field such as traffic, communication, household electrical appliance and Aero-Space.Insulated gate bipolar transistor (IGBT) is one
The novel power transistor that kind insulated type FET (MOSFET) and bipolar junction transistor (BJT) are combined, can be waited
Imitate the MOSFET for bipolar junction transistor driving.IGBT is mixed with the working machine of MOSFET structure and bipolar junction transistor
Reason, both with the advantages of MOSFET is easy to driving, input impedance is low, switching speed is fast, have again BJT on state currents density it is big,
The advantages of conduction voltage drop is low, loss is small, stability is good, thus, IGBT with the performance for improving power electronic system.From
Since IGBT inventions, people are directed to improving always IGBT performance, by the development of twenties years, propose for seven generations in succession
IGBT device structure constantly to be lifted the performance of device.7th generation IGBT structure --- trench gate charge storage type insulated gate bipolar
Transistor npn npn (CSTBT) is to be stored by being introduced below p-type base with higher-doped concentration and certain thickness N-type electric charge
Layer introduces hole barrier below p-type base so that and device greatly promotes close to the hole concentration of emitter terminal, and according to electricity
Neutral requirement will greatly increase electron concentration herein, improve the carrier concentration profile of whole N- drift regions, enhancing N- drifts with this
The conductivity modulation effect in area is moved, IGBT is obtained lower forward conduction voltage drop and more excellent forward conduction voltage drop and shut-off
The tradeoff of loss.As N-type charge storage layer doping concentration is higher, the improvement of CSTBT conductivity modulation effects is bigger, device
Forward conduction characteristic is also better.However, with the continuous improvement of N-type charge storage layer doping concentration, CSTBT devices can be caused
Breakdown voltage significantly reduces.In traditional C/S TBT device architectures as shown in Figure 1, in order to effectively shield N-type charge storage layer not
Profit influences, and the higher device of acquisition is pressure-resistant, mainly uses the following two kinds mode：
(1) trench gate depth deep, the depth of trench gate is generally made to be more than the junction depth of N-type charge storage layer；
(2) cellular width small, that is, improving MOS structure gully density makes trench gate spacing as small as possible；
Mode (1) can increase gate-emitter electric capacity and grid-collector capacitance while implementation, and IGBT switch
It is exactly the process that charge/discharge is carried out to grid capacitance on process nature, so, when the increase of grid capacitance can cause charge/discharge
Between increase, in turn result in switching speed reduction.Thus, deep trench gate depth will reduce devices switch speed, increase device
Switching loss, have influence on the compromise characteristic of break-over of device pressure drop and switching loss；And the implementation of mode (2) is on the one hand by enhancer
The grid capacitance of part, cause devices switch speed to reduce, switching loss increase, influence the folding of break-over of device pressure drop and switching loss
Middle characteristic, the big gully density of another aspect will also increase the saturation current density of device, and become shorted devices safety operation area
Difference.In addition, the gate oxide in trench gate structure is formed in the trench by a thermal oxide, in order to ensure certain threshold value
Voltage, therefore it is required that the thickness of whole gate oxide is smaller, but the thickness of mos capacitance size and oxide layer is inversely proportional, this
The grid capacitance of device can be dramatically increased by allowing for gate oxide thickness thin in traditional C/S TBT devices, while channel bottom
Electric field concentration effect will reduce the breakdown voltage of device, cause the reliability of device poor.
The content of the invention
The technical problems to be solved by the invention are：A kind of trench gate electric charge memory type of excellent combination property is provided
IGBT and its manufacture method, by reasonably optimizing device architecture, ensureing that certain device trench depth and trench MOS structure are close
On the premise of degree, solve in traditional C/S TBT devices and cause device forward conduction by improving N-type charge storage layer doping concentration
The problem of contradictory relation be present between performance and pressure-resistant performance；Grid-collector capacitance of device is reduced, improves Miller effect
The adverse effect brought；Device entirety grid capacitance is reduced, device switching speed is improved, reduces switching loss, simultaneously
Device is set to obtain the compromise characteristic between more preferable conduction voltage drop and switching loss；The carrier enhancement effect of emitter terminal is improved,
The carrier concentration profile of whole N- drift regions is improved, further improves the compromise between break-over of device pressure drop and switching loss
Characteristic；Electric current, voltage oscillation and the EMI problems in device unlatching dynamic process are avoided, improves the reliability of device；Improve
Channel bottom electric field concentration effect, improves device electric breakdown strength, further increases the reliability of device.And the present invention
Manufacture method is compatible with the manufacturing process of existing CSTBT devices.
To achieve the above object, the present invention provides following technical scheme：
On the one hand, the present invention proposes a kind of trench gate electric charge memory type IGBT, and its structure cell includes：P-type collecting zone 14,
Collector electrode metal 15 positioned at the back side of p-type collecting zone 14, positioned at the positive N-type electric field trapping layer 13 of p-type collecting zone 14 and positioned at N
The N-type drift region 12 of the top of type electric field trapping layer 13；It is characterized in that：There is P+ launch sites 4, N+ to launch in N-type drift region 12
Area 5, p-type base 6, N-type charge storage layer 7, trench gate structure, trench emitter structure and PXing Ti areas 10；
The groove emitting structural is located at the top central of N-type drift region 12, and is penetrated wherein along device vertical direction, described
Trench emitter structure is by trench emitter electrode 91 and the emitter stage medium located at the surrounding of trench emitter electrode 91 and bottom side
Layer 92 is formed；There is the PXing Ti areas 10 being attached thereto, the p-type in the N-type drift region 12 of the trench emitter structure side
Body area 10 and its upper surface of mutually close emitter stage dielectric layer 92 are provided with first medium floor 2；The trench emitter structure is another
There is the P+ launch sites 4 and N+ launch sites 5 for contacting with each other and being arranged side by side in the N-type drift region 12 of side；In the He of P+ launch sites 4
The lower section of N+ launch sites 5 has the p-type base 6 being attached thereto；Between p-type base 6 and N-type drift region 12 there is N-type electric charge to deposit
Reservoir 7；P+ launch sites 4, p-type base 6 and N-type charge storage layer 7 are connected with emitter stage dielectric layer 92；N-type charge storage layer 7
In also there is trench gate structure, the trench gate structure includes：Gate electrode 81 and gate dielectric layer, gate dielectric layer is along device Vertical Square
Groove is formed to extending into N-type charge storage layer 7, side gate dielectric layer 82 and N+ launch sites 5, p-type base 6 and N-type electricity
Lotus accumulation layer 7 is in contact, and bottom surface gate dielectric layer 83 is in contact with N-type charge storage layer 7, and the gate electrode 81 is located in groove,
The depth of gate electrode is more than the junction depth of p-type base 6 and less than the junction depth of N-type charge storage layer 7；The thickness of gate dielectric layer 82,83
No more than the thickness of trench emitter dielectric layer 92.In trench gate structure, P+ launch sites 4, N+ launch sites 5 and trench emitter electricity
Pole 91 and its top of mutually close emitter stage dielectric layer 92 have the emitter metal 1 being attached thereto, the trench gate structure
It is isolated between emitter metal 1 by second dielectric layer 3.
Further, also there is the first P-type layer 11 being attached thereto, the first P in the present invention below trench emitter structure
Type layer 11 is connected with trench emitter electrode 91 by the emitter stage dielectric layer 92 of bottom side, and first P-type layer 11 is horizontal to side
Into the N-type drift region 12 extended to below N-type charge storage layer 7.Further, also have below trench gate structure in the present invention
There is the second P-type layer 16 being attached thereto, the second P-type layer 16 is connected with gate electrode 81 by bottom surface gate dielectric layer 83, the 2nd P
Type layer 16 is extended laterally to side in the N-type drift region 12 of the lower section of N-type charge storage layer 7.
Further, the first P-type layer 11 or the second P-type layer 16 are extended laterally under N-type charge storage layer 7 in the present invention
Distance in the N-type drift region 12 of side is no more than P+ launch sites 4 and the width sum both N+ launch sites 5.
Further, when the first P-type layer 11 and the second P-type layer 16 simultaneously in the presence of, the two lateral extension portions does not connect.
Further, trench gate structure also includes Split Electrode 84 and Split Electrode dielectric layer 85, division electricity in the present invention
Pole 84 is located at the lower section of gate electrode 81 and the two is connected by bottom surface gate dielectric layer 83, Split Electrode 84 and N-type charge storage layer 7 and
It is connected between N-type drift region 12 by Split Electrode dielectric layer 85.
According to embodiments of the present invention, Split Electrode 84 and emitter metal equipotential.
Further, the thickness of Split Electrode dielectric layer 85 is more than the thickness of gate dielectric layer in the present invention.
Further, the trench emitter electrode 91 in trench emitter structure of the present invention is stepped knot wide at the top and narrow at the bottom
Structure so that the thickness of the emitter stage dielectric layer 92 of lower section is more than the thickness of the emitter stage dielectric layer 92 of top.
Further, the Split Electrode 84 in trench gate structure of the present invention is step structure wide at the top and narrow at the bottom so that under
The thickness of the Split Electrode dielectric layer 85 of side is more than the thickness of the Split Electrode dielectric layer 85 of top.
Further, the junction depth of N-type charge storage layer 7 is less than the depth of trench emitter electrode 91 in the present invention.
Further, the width of trench gate structure is less than the width of trench emitter structure in the present invention.
Further, the depth of trench emitter structure is less than or equal to the junction depth in PXing Ti areas in the present invention.
It is further that drift region structure is NPT structures or FS structures in the present invention.
It is further that the semi-conducting material of IGBT device uses Si, SiC, GaAs or GaN in the present invention, and groove is filled out
Filling material can use same material also to use not same material group using polycrystalline Si, SiC, GaAs or GaN, and each several part
Close.
On the other hand, the present invention proposes a kind of trench gate electric charge memory type IGBT manufacture method, it is characterised in that including
Following steps：
Step 1：N-type drift region 12 of the monocrystalline silicon piece as device is lightly doped using N-type, deposits and protects in silicon chip surface
Layer, make window by lithography and carry out groove silicon etching, and then etching forms separate first groove and the in N-type drift region 12
Two grooves, the depth of first groove are more than the depth of second groove；
Step 2：Silicon chip surface obtained by being handled through step 1 grows one layer of field oxide, is lithographically derived active area, then
One layer of regrowth pre-oxidation layer, by first groove and between the second groove of first groove side and second ditch
N-type charge storage layer 7 is made in trench bottom injection N-type impurity；It is another above N-type charge storage layer 7 and positioned at first groove again
The top layer implanting p-type impurity of side simultaneously makes annealing treatment obtained p-type base 6 and PXing Ti areas 10 respectively；
Step 3：Dielectric layer is formed in the first groove and second groove inwall, respectively in first groove and second groove
Interior depositing polysilicon, polysilicon and its dielectric layer of the week side of boss form trench emitter structure in first groove, more in second groove
Crystal silicon and its dielectric layer in outside form trench gate structure；
Step 4：Distinguished by the top layer of p-type base 6 of photoetching, ion implantation technology between first groove and second groove
The P+ launch sites 4 and N+ launch sites 5 for contacting with each other and being arranged side by side is made in implanting p-type impurity and N-type impurity；The P+ launch sites
4 are connected with the dielectric layer of first groove inwall, and the N+ launch sites 5 are connected with the dielectric layer of second groove inwall；
Step 5：Deposited in device surface, and formed using photoetching, etching technics and be located at the upper surface of PXing Ti areas 10 and its phase
The first medium layer 2 of the close upper surface of emitter stage dielectric layer 92 and the second dielectric layer 3 positioned at trench gate structure upper surface；
Step 6：Device surface deposit metal, and using photoetching, etching technics difference trench gate structure, P+ launch sites 4,
N+ launch sites 5 form emitter metal 1 with the upper surface of trench emitter electrode 91 and its mutually close emitter stage dielectric layer 92；
Step 7：Silicon chip is overturn, silicon wafer thickness is thinned, injects the N-type of N-type impurity and making devices of annealing in silicon chip back side
Field stop layer 13, p-type collecting zone 14 is formed in the back side implanting p-type impurity of N-type field stop layer 13, back side deposit metal forms current collection
Pole metal 15.
Further, p-type base 6 and PXing Ti areas 10 can be formed respectively at twice by increasing lithography step in the present invention.
Further, the material of the second dielectric layer 3 of first medium layer 2 can be the same or different in the present invention.
It is further the step of etching groove and to form p-type base 6, N-type electric charge storage layer 7, p-type body in the present invention
The step of area 10 and P-type layer 11, is sequentially interchangeable, i.e., can be also initially formed in N-type drift region after doped region and carry out groove quarter again
Erosion.
It is further that the preparation of N-type field stop layer 13 can be before the Facad structure of device be prepared in step 7 of the present invention
Prepared；Or directly the two-layer epitaxial material with N-type field stop layer 13 and N-type drift region 12 can be selected to be risen as technique
The silicon sheet material of beginning.
Fig. 1 is traditional C/S TBT device architectures, and the CSTBT devices based on this structure are present to be adulterated with N-type charge storage layer
The continuous improvement of concentration, forward conduction performance can be lifted but also can be especially embodied in and hit so that hit pressure-resistant performance impairment simultaneously
Wearing voltage significantly reduces.The present invention introduces the trench emitter structure being connected with PXing Ti areas in traditional C/S TBT device architectures,
So as to avoid it is existing using deepening trench gate depth and reducing present in cellular width these means the defects of, and effectively shielding
Also reach while covering this adverse effect of N-type charge storage layer and significantly carried in the case of not influenceing device threshold voltage and opening
The combination property of device is risen, the operation principle of optimised devices, technological improvement of the invention and relevant art effect have following institute
State：
First, the present invention introduces the trench emitter structure being connected with PXing Ti areas in traditional C/S TBT device architectures, not
In the case that influence IGBT device threshold voltage and IGBT device are opened, traditional C/S TBT gate electrode-collector capacitance is changed
For gate-emitter electric capacity, Miller capacitance is greatly reduced, improves the adverse effect that Miller effect is brought；Groove is launched
Thick emitter stage dielectric layer can avoid channel bottom electric field concentration effect in the structure of pole, improve the breakdown voltage of device.
2nd, it is more than the junction depth of p-type base and less than the knot of N-type charge storage layer the invention enables the depth of trench gate structure
It is deep, whole grid capacitance is reduced, improves the switching speed of device, reduces switching loss and drive loss, is caused simultaneously
Device obtains the compromise characteristic between more preferable conduction voltage drop and switching loss.
3rd, the presence in PXing Ti areas can reduce the extraction area in hole, improve the carrier enhancing effect of emitter terminal
Answer, further improve the carrier concentration profile of whole N-type drift region, so as to optimize the folding of forward conduction voltage drop and switching loss
Middle relation.
4th, the present invention sets by introducing and the equipotential trench emitter electrode of emitter stage and rationally itself and remaining structure
Between relation, ensure that the semiconductor surface that is in contact with emission electrode dielectric layer is not in device opens dynamic process with this
Electron accumulation or inversion layer can be formed, therefore device is not in negative differential capacity effect, is avoided in switch dynamic process
Electric current, voltage oscillation and EMI problems, and then lifted device reliability.
5th, by setting P-type layer below trench gate structure or/and trench emitter structure, P-type layer extends to the present invention
N below N-type charge storage layer-Drift region, and P-type layer and N-The PN junction that drift region is formed is reverse-biased, because P-type layer laterally expands
The electron screening effect that exhibition provides, the N-type drift region fully- depleted below N-type charge storage layer make it that before device breakdown, and then
So that thus almost all backward voltage is born, so as to not influence device while charge storage layer doping concentration is improved
Breakdown voltage, which overcome traditional C/S TBT structure forward conduction characteristics and it is pressure-resistant between contradiction.
In summary, the beneficial effect of the present invention compared with prior art is：
The present invention is launched by the groove that the introducing of trench gate structure side is connected with PXing Ti areas in traditional C/S TBT devices
Pole structure, trench emitter structure by the conversion of traditional C/S TBT grid-collector capacitance for gate-emitter electric capacity, significantly
Miller capacitance is reduced, improves the adverse effect that Miller effect is brought, meanwhile, in device opens dynamic process, with groove
The semiconductor surface of emitter stage dielectric layer contact will not form accumulation layer or inversion layer, therefore device is not in negative differential electric capacity
Effect, electric current, voltage oscillation and the EMI problems opened in dynamic process are avoided, device reliability is improved, in addition, groove
Thick emitter stage dielectric layer can avoid channel bottom electric field concentration effect in emitter structure, improve the breakdown potential of device
Pressure；Present invention decreases the depth of trench gate so that the depth of trench gate is less than the junction depth of N-type charge storage layer, is reduced with this
Gate-emitter electric capacity and grid-collector capacitance, the switching speed of device is improved, switching loss of device by it,
Device is caused to obtain the compromise characteristic between more preferable conduction voltage drop and switching loss simultaneously；The presence energy in ZhongPXing Ti areas of the present invention
The extraction area in hole is enough reduced, improves the carrier enhancement effect of emitter terminal, improves the current-carrying of whole N-type drift region
Sub- concentration distribution, further improve the compromise characteristic between forward conduction voltage drop and turn-off power loss.The it is proposed of structure of the present invention
Can overcome existing causes the switch performance, conduction voltage drop and switch of device by deepening trench gate depth and reducing cellular width
The deficiency that loss compromise characteristic and reliability are damaged, and manufacture method of the present invention and the manufacture of existing traditional C/S TBT devices
Technique is mutually compatible.
Brief description of the drawings
Fig. 1 is the structure cell schematic diagram of traditional CSTBT devices；
Fig. 2 is the structure cell schematic diagram for the trench gate charge storage type IGBT device that the embodiment of the present invention 1 provides；
Fig. 3 is the structure cell schematic diagram for the trench gate charge storage type IGBT device that the embodiment of the present invention 2 provides；
Fig. 4 is the structure cell schematic diagram for the trench gate charge storage type IGBT device that the embodiment of the present invention 3 provides；
Fig. 5 is the structure cell schematic diagram for the trench gate charge storage type IGBT device that the embodiment of the present invention 4 provides；
Fig. 6 is the structure cell schematic diagram for the trench gate charge storage type IGBT device that the embodiment of the present invention 5 provides；
Fig. 7 is the structure cell schematic diagram for the trench gate charge storage type IGBT device that the embodiment of the present invention 6 provides；
Fig. 8 is the structure cell schematic diagram for the trench gate charge storage type IGBT device that the embodiment of the present invention 7 provides；
Fig. 1 is into Fig. 8：
1 is emitter metal, and 2 be first medium layer, and 3 be second dielectric layer, and 4 be N+ launch sites, and 5 be P+ launch sites, and 6 are
P-type base, 7 be N-type charge storage layer, and 81 be gate electrode, and 82 be side gate dielectric layer, and 83 be bottom surface gate dielectric layer, and 84 be point
Split electrode, 85 be Split Electrode dielectric layer, and 91 be trench emitter electrode, and 92 be emitter stage dielectric layer, and 10 be PXing Ti areas, 11
It is N-type drift region for P-type layer, 12,13 be N-type electric field trapping layer, and 14 be p-type collecting zone, and 15 be collector electrode metal.
Fig. 9 is that the device architecture schematic diagram formed after groove is etched in the manufacture method that the embodiment of the present invention 1 provides；
Figure 10 is the device architecture schematic diagram formed in the manufacture method that the embodiment of the present invention 1 provides after trench dielectric layer；
Figure 11 is the device architecture signal formed in the manufacture method that the embodiment of the present invention 1 provides after trench polysilicon silicon electrode
Figure；
Figure 12 is the device architecture formed in the manufacture method that the embodiment of the present invention 1 provides behind N+ launch sites and P+ launch sites
Schematic diagram；
Figure 13 is the device architecture schematic diagram formed in the manufacture method that the embodiment of the present invention 1 provides after surface media；
Figure 14 is the device architecture signal formed in the manufacture method that the embodiment of the present invention 1 provides after the electrode of surface emitting pole
Figure；
Figure 15 is the device architecture signal formed in the manufacture method that the embodiment of the present invention 1 provides after the completion of whole processes
Figure；
Figure 16 is the device architecture schematic diagram formed in the manufacture method that the embodiment of the present invention 2 provides after groove；
Figure 17 is the device architecture schematic diagram formed in the manufacture method that the embodiment of the present invention 3 provides after groove；
Figure 18 is that trench emitter dielectric layer and Split Electrode medium are formed in the manufacture method that the embodiment of the present invention 4 provides
Device architecture schematic diagram after layer；
Figure 19 is the device architecture schematic diagram after depositing polysilicon in the manufacture method that the embodiment of the present invention 4 provides；
Figure 20 is the device formed in the manufacture method that the embodiment of the present invention 4 provides after trench emitter electrode and Split Electrode
Part structural representation；
Figure 21 is the device architecture schematic diagram formed in the manufacture method that the embodiment of the present invention 4 provides after gate dielectric layer；
Figure 22 is the device architecture schematic diagram formed in the manufacture method that the embodiment of the present invention 4 provides after trench gate electrode；
Embodiment
The principle and characteristic of the present invention are described in detail with reference to Figure of description and specific embodiment：
Embodiment 1：
The present embodiment provides a kind of trench gate electric charge memory type IGBT as shown in Figure 2, and its structure cell includes：P-type collection
Electric area 14, the collector electrode metal 15 positioned at the back side of p-type collecting zone 14, positioned at the positive N-type electric field trapping layer 13 of p-type collecting zone 14
With the N-type drift region 12 above N-type electric field trapping layer 13；It is characterized in that：In N-type drift region 12 have P+ launch sites 4,
N+ launch sites 5, p-type base 6, N-type charge storage layer 7, trench gate structure, trench emitter structure, PXing Ti areas 10 and P-type layer
11；
The groove emitting structural is located at the top central of N-type drift region 12, and is penetrated wherein along device vertical direction, described
Trench emitter structure is by trench emitter electrode 91 and the emitter stage medium located at the surrounding of trench emitter electrode 91 and bottom side
Layer 92 is formed；There is the PXing Ti areas 10 being attached thereto, the p-type in the N-type drift region 12 of the trench emitter structure side
Body area 10 and its upper surface of mutually close emitter stage dielectric layer 92 are provided with first medium floor 2；The trench emitter structure is another
There is the P+ launch sites 4 and N+ launch sites 5 for contacting with each other and being arranged side by side in the N-type drift region 12 of side；In the He of P+ launch sites 4
The lower section of N+ launch sites 5 has the p-type base 6 being attached thereto；Between p-type base 6 and N-type drift region 12 there is N-type electric charge to deposit
Reservoir 7；P+ launch sites 4, p-type base 6 and N-type charge storage layer 7 are connected with emitter stage dielectric layer 92；N-type charge storage layer 7
In also there is trench gate structure, the trench gate structure includes：Gate electrode 81 and gate dielectric layer, gate dielectric layer is along device Vertical Square
Groove is formed to extending into N-type charge storage layer 7, side gate dielectric layer 82 and N+ launch sites 5, p-type base 6 and N-type electricity
Lotus accumulation layer 7 is in contact, and bottom surface gate dielectric layer 83 is in contact with N-type charge storage layer 7, and the gate electrode 81 is located in groove,
The depth of gate electrode is more than the junction depth of p-type base 6 and less than the junction depth of N-type charge storage layer 7；The thickness of gate dielectric layer 82,83
No more than the thickness of trench emitter dielectric layer 92；In trench gate structure, P+ launch sites 4, N+ launch sites 5 and trench emitter electricity
Pole 91 and its top of mutually close emitter stage dielectric layer 92 have the emitter metal 1 being attached thereto, the trench gate structure
It is isolated between emitter metal 1 by second dielectric layer 3.
Embodiment 2：
The present embodiment provides a kind of trench gate electric charge memory type IGBT as shown in Figure 3, and the present invention in groove except launching
It is provided with below the structure of pole beyond the first P-type layer 11 being attached thereto, remaining structure is same as Example 1.
The present embodiment is by introducing the first P being connected with trench emitter electrode 91 by the emitter stage dielectric layer 92 of bottom side
Type layer 11, the first P-type layer 11 are extended laterally in the N-type drift region 12 of the lower section of N-type charge storage layer 7 to side, improved with this
Device electric breakdown strength, while improve the lance caused by charge storage layer concentration between breakdown voltage and forward conduction voltage drop
Shield.
Embodiment 3：
The present embodiment provides a kind of trench gate electric charge memory type IGBT, its structure cell as shown in figure 4, the present embodiment except
It is provided with below trench gate structure beyond the second P-type layer 16 being attached thereto, remaining structure is same as Example 2.
The present embodiment introduces the second P-type layer 16 being connected with gate electrode 81 by bottom side gate dielectric layer 83, the second P-type layer 16
Extended laterally to side in the N-type drift region 12 of the lower section of N-type charge storage layer 7, negative electrical charge in the storage of N-type electric charge is shielded with this
Influence, reduce gate capacitance, improve the concentration of trench gate bottom electric field, improve device electric breakdown strength and reliability.
Embodiment 4：
The present embodiment provides a kind of trench gate electric charge memory type IGBT, its structure cell as shown in figure 5, the present embodiment except
Introduced in trench gate structure below gate electrode 81 and beyond Split Electrode equipotential with gate electrode 84, remaining structure is equal
It is same as Example 1.
Preferably, the thickness of Split Electrode dielectric layer 85 is more than the thickness of gate dielectric layer in the present embodiment.
Embodiment 1 is compared in this implementation, and the breakdown voltage of device is also improved while grid capacitance is reduced.
Embodiment 5：
A kind of trench gate electric charge memory type IGBT is present embodiments provided, its structure cell is as shown in fig. 6, the present embodiment removes
Introduced in trench gate structure below gate electrode 81 and beyond Split Electrode equipotential with gate electrode 84, remaining structure
It is same as Example 2.
Preferably, the thickness of Split Electrode dielectric layer 85 is more than the thickness of gate dielectric layer in the present embodiment.
Embodiment 6：
A kind of trench gate electric charge memory type IGBT is present embodiments provided, its structure cell is as shown in fig. 7, the present embodiment removes
Introduced in trench gate structure below gate electrode 81 and beyond Split Electrode equipotential with gate electrode 84, remaining structure
It is same as Example 3.
Preferably, the thickness of Split Electrode dielectric layer 85 is more than the thickness of gate dielectric layer in the present embodiment.
Embodiment 7：
A kind of trench gate electric charge memory type IGBT is present embodiments provided, its structure cell is as shown in figure 8, the present embodiment removes
Trench emitter electrode 91 is designed as the thickness that step structure wide at the top and narrow at the bottom causes the emitter stage dielectric layer 92 of lower section
More than the thickness of the emitter stage dielectric layer 92 of top；Split Electrode 84 is designed as step structure wide at the top and narrow at the bottom and causes lower section
Split Electrode dielectric layer 85 thickness be more than top Split Electrode dielectric layer 85 thickness, remaining structure with embodiment 6
It is identical.
The present embodiment can increase the thickness of channel bottom sharp corner dielectric layer, further improve the breakdown voltage of device.
Embodiment 8：
The present embodiment is said by taking the trench gate charge storage type insulated gate bipolar transistor of 1200V voltage class as an example
It is bright, the device of different performance parameter can be prepared according to the actual requirements according to common sense in the field.
Step 1：N-type drift region 12 of the monocrystalline silicon piece as device is lightly doped using N-type, the thickness of selected silicon chip is 300
~600um, doping concentration 1013~1014Individual/cm3；Protected in the TEOS that silicon chip surface deposition thickness is 700~1000 nanometers
Layer, make window by lithography and carry out groove silicon etching, and then etching forms separate first groove and the in N-type drift region 12
Two grooves, the depth of first groove are more than the depth of second groove；
Step 2：Silicon chip surface obtained by being handled through step 1 grows one layer of field oxide, is lithographically derived active area, then
One layer of regrowth pre-oxidation layer, by first groove and between the second groove of first groove side and second ditch
Trench bottom injection N-type impurity is made N-type charge storage layer 7, and the energy of ion implanting is 200~500keV, implantation dosage 1013
~1014Individual/cm2；The top layer implanting p-type impurity above N-type charge storage layer 7 and positioned at first groove opposite side and anneal again
Processing is made p-type base 6 and PXing Ti areas 10 respectively, and the energy of ion implanting is 60~120keV, implantation dosage 1013~
1014Individual/cm2, annealing temperature is 1100~1150 DEG C, and annealing time is 10~30 minutes；
Step 3：In 1050 DEG C~1150 DEG C of O2Formed respectively in the first groove and second groove inwall under atmosphere
Dielectric layer, and after more in the depositing polysilicon in first groove and second groove respectively at 750 DEG C~950 DEG C, first groove
Crystal silicon and its dielectric layer of the week side of boss form trench emitter structure, and polysilicon and its dielectric layer in outside form ditch in second groove
Slot grid structure；
Step 4：Distinguished by the top layer of p-type base 6 of photoetching, ion implantation technology between first groove and second groove
Implanting p-type impurity and N-type impurity, the energy of ion implanting N-type impurity are 30~60keV, implantation dosage 1015~1016Individual/
cm2, the energy of ion implanting p type impurity is 60~80keV, implantation dosage 1015~1016Individual/cm2, annealing temperature 900
DEG C, the time is 20~30 minutes, and the P+ launch sites 4 and N+ launch sites 5 for contacting with each other and being arranged side by side is made；The P+ launch sites
4 are connected with first groove inwall dielectric layer, and the N+ launch sites 5 are connected with second groove inwall dielectric layer；
Step 5：Deposited in device surface, and formed using photoetching, etching technics and be located at the upper surface of PXing Ti areas 10 and its phase
The first medium layer 2 of the close upper surface of emitter stage dielectric layer 92 and the second dielectric layer 3 positioned at trench gate structure upper surface；
Step 6：Device surface deposit metal, and using photoetching, etching technics difference trench gate structure, P+ launch sites 4,
N+ launch sites 5 form emitter metal 1 with the upper surface of trench emitter electrode 91 and its mutually close emitter stage dielectric layer 92；
Step 7：Silicon chip is overturn, silicon wafer thickness is thinned, injects the N-type of N-type impurity and making devices of annealing in silicon chip back side
Field stop layer 13, the thickness of N-type field stop layer 13 is 15~30 microns, and the energy of ion implanting is 1500~2000keV, injection
Dosage is 1013~1014Individual/cm2, annealing temperature is 1200~1250 DEG C, and the time is 300~600 minutes；In N-type field stop layer
13 back side implanting p-type impurity form p-type collecting zones 14, and Implantation Energy is 40~60keV, implantation dosage 1012~1013Individual/
cm2, in H2With N2Back side annealing is carried out under the atmosphere of mixing, temperature is 400~450 DEG C, and the time is 20~30 minutes；Form sediment at the back side
Product metal forms collector electrode metal 15, so far completes trench gate charge storage type IGBT preparation.
Further, p-type base 6 and PXing Ti areas 10 can be formed respectively at twice by increasing lithography step in the present invention.
Further, the preparation of N-type field stop layer 13 can be in the advance for the Facad structure for preparing device in step 7 of the present invention
It is prepared by row；Or directly the two-layer epitaxial material with N-type field stop layer 13 and N-type drift region 12 can be selected to be originated as technique
Silicon sheet material.
Further, the material of first medium layer 2, second dielectric layer 3, gate dielectric layer or emitter stage medium 92 can be adopted
Combination of materials not of the same race can also be used with same material, first medium layer 2, second dielectric layer 3, gate dielectric layer and emitter stage are situated between
The material of matter 92 can be the same or different.
Further, can be by increasing etching, oxidation and polysilicon after polycrystalline silicon deposit in step 3 completion groove of the present invention
Depositing technics forms splitting bar structure, you can device architecture as shown in Figure 5 is made.
Further, can be formed in step 2 of the present invention before N-type charge storage layer 6 is formed by increasing lithography step
P-type layer positioned at first groove or/and second groove bottom；Complete polycrystalline silicon deposit in groove in step 3 again on this basis
After can pass through and increase etching, oxidation and polycrystalline silicon deposition process and form splitting bar structure, you can be made as is seen in fig. 6 or fig. 7
Device architecture.
Further, the present invention can directly select the two-layer epitaxial material with N-type field stop layer 13 and N- drift regions 12
Silicon sheet material as technique starting；
Further, the preparation of N-type field stop layer 13 can omit in present invention process step 7.
Claims (9)
1. a kind of trench gate electric charge memory type IGBT, including：P-type collecting zone (14), the current collection positioned at p-type collecting zone (14) back side
Pole metal (15), positioned at the positive N-type electric field trapping layer (13) of p-type collecting zone (14) and on N-type electric field trapping layer (13)
The N-type drift region (12) of side；It is characterized in that：There is P+ launch sites (4), N+ launch sites (5), p-type base in N-type drift region (12)
Area (6), N-type charge storage layer (7), trench gate structure, trench emitter structure and PXing Ti areas (10)；
The groove emitting structural is located at N-type drift region (12) top central, and is penetrated wherein along device vertical direction, the ditch
Groove emitter structure is by groove emission electrode (91) and the emitter stage dielectric layer located at groove emission electrode (91) surrounding and bottom side
(92) form；There is the PXing Ti areas (10) being attached thereto, institute in the N-type drift region (12) of the trench emitter structure side
ShuPXing Ti areas (10) and its upper surface of mutually close emitter stage dielectric layer (92) are provided with second dielectric layer (2)；The groove hair
There is the P+ launch sites (4) and N+ launch sites for contacting with each other and being arranged side by side in the N-type drift region (12) of emitter structure opposite side
(5)；There is the p-type base (6) being attached thereto in the lower section of P+ launch sites (4) and N+ launch sites (5)；P-type base (6) and N-type
There is N-type charge storage layer (7) between drift region (12)；P+ launch sites (4), p-type base (6) and N-type charge storage layer (7) are equal
It is connected with emitter stage dielectric layer (92)；Also there is trench gate structure, the trench gate structure includes in N-type charge storage layer (7)：
Gate electrode (81) and gate dielectric layer, gate dielectric layer form ditch in extending into N-type charge storage layer (7) along device vertical direction
Groove, side gate dielectric layer (82) are in contact with N+ launch sites (5), p-type base (6) and N-type charge storage layer (7), and bottom surface grid are situated between
Matter layer (83) is in contact with N-type charge storage layer (7), and the gate electrode (81) is located in groove, and the depth of gate electrode (81) is big
Junction depth in p-type base (6) and the junction depth less than N-type charge storage layer (7), the thickness of gate dielectric layer (82,83) are not more than ditch
The thickness of groove emitter stage dielectric layer (92)；In trench gate structure, P+ launch sites (4), N+ launch sites (5) and groove emission electrode
(91) and its top of mutually close emitter stage dielectric layer (92) has the emitter metal (1) that is attached thereto, the trench gate
It is isolated between structure and emitter metal (1) by first medium layer (3).
A kind of 2. trench gate electric charge memory type IGBT according to claim 1, it is characterised in that：The trench emitter knot
Also there is the first P-type layer (11) being attached thereto, the first P-type layer (11) passes through bottom side with trench emitter electrode (91) below structure
Emitter stage dielectric layer (92) be connected, first P-type layer (11) is extended laterally to below N-type charge storage layer (7) to side
N-type drift region (12) in.
A kind of 3. trench gate electric charge memory type IGBT according to claim 1, it is characterised in that：Under the trench gate structure
Side also has the second P-type layer (16) being attached thereto, and the second P-type layer (16) passes through bottom surface gate dielectric layer (83) with gate electrode (81)
It is connected, second P-type layer (16) is extended laterally in the N-type drift region (12) below N-type charge storage layer (7) to side.
A kind of 4. trench gate electric charge memory type IGBT according to claim 1, it is characterised in that：The trench gate structure is also
Including Split Electrode (84) and Split Electrode dielectric layer (85), Split Electrode (84) is located at below gate electrode (81) and the two passes through
Bottom surface gate dielectric layer (83) is connected, by dividing between Split Electrode (84) and N-type charge storage layer (7) and N-type drift region (12)
Electrode dielectric (85) is split to be connected.
A kind of 5. trench gate electric charge memory type IGBT according to claim 1, it is characterised in that：N-type electric charge in the present invention
The junction depth of accumulation layer (7) is less than the depth of trench emitter electrode (91).
A kind of 6. trench gate electric charge memory type IGBT according to claim 1, it is characterised in that：In the trench gate structure
Split Electrode (84) be step structure wide at the top and narrow at the bottom so that the thickness of the Split Electrode dielectric layer (85) of lower section be more than it is upper
The thickness of the Split Electrode dielectric layer (85) of side.
A kind of 7. trench gate electric charge memory type IGBT according to claim 1, it is characterised in that：The trench emitter knot
Trench emitter electrode (91) in structure is step structure wide at the top and narrow at the bottom so that the thickness of the emitter stage dielectric layer (92) of lower section
Thickness of the degree more than the emitter stage dielectric layer (92) of top.
8. a kind of trench gate electric charge memory type IGBT manufacture method, it is characterised in that comprise the following steps：
Step 1：N-type drift region (12) of the monocrystalline silicon piece as device is lightly doped using N-type, protective layer is deposited in silicon chip surface,
Make window by lithography and carry out groove silicon etching, and then etching forms separate first groove and the in N-type drift region (12)
Two grooves, the depth of first groove are more than the depth of second groove；
Step 2：Silicon chip surface obtained by being handled through step 1 grows one layer of field oxide, is lithographically derived active area, then regenerates
Long one layer of pre-oxidation layer, by first groove and between the second groove of first groove side and the second groove bottom
N-type charge storage layer (7) is made in portion's injection N-type impurity；It is again above N-type charge storage layer (7) and another positioned at first groove
The top layer implanting p-type impurity of side simultaneously makes annealing treatment obtained p-type base (6) and PXing Ti areas (10) respectively；
Step 3：Dielectric layer is formed in the first groove and second groove inwall, is formed sediment respectively in first groove and second groove
Product polysilicon, polysilicon and its dielectric layer of the week side of boss form trench emitter structure in first groove, polysilicon in second groove
And its dielectric layer in outside forms trench gate structure；
Step 4：Noted respectively by p-type base (6) top layer of photoetching, ion implantation technology between first groove and second groove
Enter p type impurity and the P+ launch sites (4) and N+ launch sites (5) for contacting with each other and being arranged side by side is made in N-type impurity；The P+ transmittings
Area (4) is connected with the dielectric layer of first groove inwall, and the N+ launch sites (5) are connected with the dielectric layer of second groove inwall；
Step 5：Deposited in device surface, and formed positioned at PXing Ti areas (10) upper surface using photoetching, etching technics and its mutually leaned on
The first medium layer (2) of near emitter stage dielectric layer (92) upper surface and the second dielectric layer positioned at trench gate structure upper surface
(3)；
Step 6：Metal is deposited in device surface, and using photoetching, etching technics difference trench gate structure, P+ launch sites (4), N+
Launch site (5) forms emitter stage gold with the upper surface of trench emitter electrode (91) and its mutually close emitter stage dielectric layer (92)
Belong to (1)；
Step 7：Silicon chip is overturn, silicon wafer thickness is thinned, injects the N-type field resistance of N-type impurity and making devices of annealing in silicon chip back side
Only layer (13), at N-type field stop layer (13) back side, implanting p-type impurity forms p-type collecting zone (14), and back side deposit metal forms collection
Electrode metal (15).
9. a kind of trench gate electric charge memory type IGBT according to claim 1, it is characterised in that pass through in the step 2
Increase lithography step and form p-type base (6) and PXing Ti areas (10) respectively at twice.
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