CN115985942A - Trench gate IGBT device and manufacturing method - Google Patents
Trench gate IGBT device and manufacturing method Download PDFInfo
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Abstract
The invention provides a trench gate IGBT device and a manufacturing method thereof. The device comprises a substrate, a collector region, a drift region, a carrier storage layer, a body region, an emitter region, a gate region and two emitter groove structures. Each emitter trench structure includes an emitter dielectric and an emitter conductive material filled in an emitter trench, two emitter trenches extending vertically downward from the top surface of the device into the drift region, the two emitter trenches being laterally separated by the body region. The structure of the two emitter grooves can effectively improve the circulation path of hole current, so that the hole current can vertically flow into emitter metal upwards from the bottom and the side wall of the emitter groove and through a current carrier storage layer and a body region between the two emitter grooves, the hole current of the region below the emitter region is reduced, the opening of a PN junction formed between the body region and the emitter region is inhibited, and the short-circuit resistance, the latch-up resistance and the large-current turn-off capability of a device are obviously improved.
Description
Technical Field
The invention relates to the technical field of power semiconductors, in particular to a trench type insulated gate bipolar transistor device.
Background
An Insulated Gate Bipolar Transistor (IGBT) combines the advantages of an MOSFET that driving control is easy, input impedance is high, GTR current density is large, and saturation voltage drop is low, and is widely applied to the fields of rail transit, new energy vehicles, high voltage direct current transmission, and the like. Since the birth of the IGBT, the performance of the IGBT is continuously improved, and the IGBT also develops towards higher voltage, larger current, higher working temperature, lower loss and the like.
The gate structure of the high-voltage IGBT may be classified into a planar gate structure and a trench gate structure. The IGBT with the trench gate structure has higher channel density due to smaller cell pitch, and is more widely applied to scenes of high voltage and large current. However, the IGBT channel density of the trench gate structure is increased, which leads to an increase in short-circuit current and a decrease in short-circuit resistance, and due to the introduction of the trench, a high electric field is introduced at the bottom of the trench gate, which limits the increase in IGBT blocking capability of the trench gate structure.
In practical application, the short-circuit resistance, the latch-up resistance and the large-current turn-off resistance of the IGBT with the trench gate structure need to be optimized and improved, so that the stability and the reliability of the device are improved.
Disclosure of Invention
The invention aims to solve the problems in the prior art and provides a trench gate IGBT device and a manufacturing method thereof. The trench gate IGBT device comprises two emitter trench structures, and the circulation path of hole current can be effectively improved, so that the hole current can vertically and upwards flow into emitter metal from the bottom and the side wall of the emitter trench of a reference ground potential and through a current carrier storage layer and a body region between the two emitter trenches, the hole current in the region below the emitter region is reduced, the opening of a PN junction formed between the body region and the emitter region is inhibited, and the short-circuit resistance, the latching resistance and the large-current turn-off capability of the device are obviously improved.
According to an aspect of the present invention, there is provided a trench gate IGBT device, comprising: a semiconductor substrate having a first conductivity type; the collector region is of a second conduction type and is formed at the bottom of the semiconductor substrate; a drift region of the first conductivity type overlying the collector region; a carrier storage layer having a first conductivity type formed on the drift region; a body region having a second conductivity type formed over the carrier storage layer; an emitter region of a first conductivity type formed over the body region on top of the semiconductor substrate; the gate region is formed in a gate region groove, and the gate region groove vertically extends downwards from the top surface of the device to a first depth and enters the drift region; and first and second emitter trench structures formed within the first and second emitter trenches, respectively, each emitter trench structure including an emitter dielectric and an emitter conductive material filled in the emitter trench, each emitter trench extending vertically downward from the device top surface to a second depth into the drift region, the emitter dielectric separating the emitter conductive material from the body regions, the carrier storage layer, and the drift region, wherein the first and second emitter trench structures are laterally separated by the body regions.
According to another aspect of the invention, a method for manufacturing a trench gate IGBT device is provided, which comprises the following steps: forming a carrier storage layer on top of a semiconductor substrate; forming a gate region groove from the top surface of the semiconductor substrate to penetrate through the carrier storage layer downwards; filling the groove of the gate region with a conductive material to form a gate region; forming a first emitter trench and a second emitter trench from the top surface of the semiconductor substrate down through the carrier storage layer; forming a dielectric layer on inner walls of the first emitter trench and the second emitter trench; filling the first emitter trench and the second emitter trench with a conductive material to form a first emitter trench structure and a second emitter trench structure; and forming a first body region between the first emitter trench and the second emitter trench.
Drawings
Fig. 1 shows a cross-sectional view of a trench gate IGBT device 100 according to an embodiment of the invention;
fig. 2 shows a cross-sectional view of a trench gate IGBT device 200 according to yet another embodiment of the invention;
fig. 3 shows a cross-sectional view of a trench gate IGBT device 300 according to yet another embodiment of the invention;
fig. 4 shows a cross-sectional view of a trench gate IGBT device 400 according to yet another embodiment of the invention;
fig. 5 shows a cross-sectional view of a trench gate IGBT device 500 according to yet another embodiment of the invention;
fig. 6 shows a cross-sectional view of a trench gate IGBT device 600 according to yet another embodiment of the invention;
fig. 7A-7I are schematic process flow diagrams of a process for fabricating a trench gate IGBT device 600 according to an embodiment of the invention.
As shown in the drawings, like reference numerals refer to like parts throughout the different views. The drawings presented herein are for purposes of illustrating the embodiments, principles, concepts, etc., and are not necessarily drawn to scale.
In the above figures, the reference numerals have the following meanings: 100-600 are trench gate IGBT devices; 1 is an emitter metal; 2 is an interlayer dielectric layer; 3 is an N-type emitter region; 4 is a P-type emitting region; 5 is a P-type body region; 51 is a first P-type body region; 52 is a second P-type body region; 53 is a floating P-type region; 6 is an N-type carrier storage layer; 7 is a grid groove; 71 is a gate dielectric; 72 is a gate region; 8 is an N-type lightly doped drift region; 9 is an N-type field stop layer; 10 is a P-type collector region; 11 is a collector metal; 12 is an emitter groove; 121 is an emitter trench dielectric; 122 is an emitter trench conductive material; 13 is a floating P-type buried layer; 31, a grid region groove mask plate; 32 emitter trench mask.
Detailed Description
Specific embodiments of the present invention will now be described without limitation in conjunction with the accompanying drawings. This invention may be embodied in many different forms and this description is provided for the purpose of describing particular embodiments more fully and fully, and should not be construed as limited to these particular embodiments. The drawings are idealized schematic representations of specific structures and/or intermediate structures of specific embodiments. It is to be understood that variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments of the invention should not be construed as limited to the particular forms of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to limit the scope of the present invention. It will be further appreciated that the drawings are not to scale and that the size of layers and regions may be exaggerated for clarity. In this specification, "+" and "-" are used to describe the relative concentrations of the doped regions, but this does not limit the concentration range of the doped regions, nor does it limit the doped regions otherwise. For example, a doped region described below as being N + or N-may also be referred to as an N-type doped region. Further, the term "coupled" as used herein means directly connected or indirectly connected through another conductor, such as a metal.
Reference throughout this specification to "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention. Thus, the appearances of the phrases "in one embodiment" or "in an embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment. The verbs "comprising" and "having" are used herein as open-ended limitations that neither exclude nor require the presence of unrecited features. The features recited in the dependent claims may be freely combined with each other, unless explicitly stated otherwise. Furthermore, the described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.
Certain other embodiments may differ in construction, composition, or process flow from embodiments disclosed in the present technology, but it will be understood by those skilled in the art that embodiments of the present technology may be practiced without the embodiments or other details, methods, materials, etc. shown in the drawings.
Fig. 1 shows a cross-sectional view of a trench gate IGBT device 100 according to an embodiment of the invention. The trench gate IGBT device 100 includes a semiconductor substrate having a first conductivity type (e.g., N-type) with a collector region 10 of a second conductivity type (e.g., P-type) opposite to the first conductivity type at the bottom of the semiconductor substrate. An N-type field stop layer 9 is formed above the P-type collector region 10. An N-type lightly doped (N-) drift region 8 is located above the N-type field stop layer 9. An N-type carrier storage layer 6 and a P-type body region 5 are located within the N-drift region 8. An N-type heavily doped (N +) emitter region 3 and a P-type heavily doped (P +) body contact region 4 are located within the P-type body region 5 and are formed adjacent to the surface of the P-type body region 5.
Gate trenches extend from the top surface of the device down through the N + emitter region 3, the P-type body region 5 and the N-type carrier storage layer 6 into the N-drift region 8. A gate 72 is formed in the gate trench, the gate 72 comprising a conductive material (e.g., doped polysilicon). A gate dielectric 71 is formed in the gate trench and comprises an insulating material (e.g., silicon dioxide). A gate dielectric 71 separates the gate 72 from the N-type emitter region 3, the P-type body region 5, the N-type carrier storage layer 6 and the N-drift region 8. The gate region 72 will be electrically connected to the outside through a gate metal (not shown). In one embodiment, the gate trench extends to a depth of 3-6 um and the thickness of the gate dielectric 71 within the gate trench is 50-150 nm.
Each IGBT cell of the IGBT device 100 further includes two identical emitter trench structures, which are formed in the two emitter trenches, respectively. An emitter trench extends from the top surface of the device down through the P + body contact region 4, the P-type body region 5 and the N-type carrier storage layer 6 and into the N-drift region 8. The emitter trench structure includes an emitter trench conductive material 122 (such as doped polysilicon) and an emitter trench dielectric 121. An emitter trench dielectric 121 separates emitter trench conductive material 122 from P + body contact region 4, P-type body region 5, N-type carrier storage layer 6, and N-drift region 8. The two emitter trenches are laterally separated by a P-type body region 5 and an N-type carrier storage layer 6. In this embodiment, the portion of the P-type body region 5 located between two emitter trenches is illustrated as a first P-type body region 51.
In one embodiment, the emitter trench extension depth is greater than the gate trench extension depth. For example, in one embodiment, the emitter trench extends to a depth of 4 μm to 8 μm, and the width of the emitter trench is set to 0.5 μm to 2 μm. In one embodiment, the emitter trench extends to a depth of less than twenty percent of the device thickness. Emitter trench dielectric 121 comprises one or more dielectric materials, such as thermally grown and/or deposited silicon dioxide. In one embodiment, the dielectric constant of emitter trench dielectric 121 is greater than the dielectric constant of gate dielectric 71. The thickness of emitter trench dielectric 121 may be adjusted according to design requirements.
In some embodiments, the doping concentration of the P-type body region 5 is 3 × 10 16 cm -3 ～3×1017 cm -3 The depth of the knot is 1-4 μm. The doping concentration of the P + body contact region 4 is 5 x 10 18 cm -3 ～1×10 20 cm -3 The knot depth is 0.2-1 μm. The doping concentration of the N + emitter region 3 is 5X 10 18 cm -3 ～1×10 20 cm -3 The depth of the junction is 0.2 um-0.8 μm. The doping concentration of the N-type carrier storage layer 6 is 5 x 10 14 cm -3 ～5×10 16 cm -3 The depth of the knot is 3-7 μm. The doping concentration of the N-drift region 8 is 2 x 10 13 cm -3 ～8×10 14 cm -3 The thickness is 40 um-200 μm. The doping concentration of the N-type field stop layer 9 is 1 x 10 15 cm -3 ～5×10 17 cm -3 The depth of the knot is 0.5-40 μm. The doping concentration of the P-type collector region 10 is 8 multiplied by 10 16 cm -3 ～1×10 18 cm -3 The depth of the knot is 0.3-5 μm. The width of the unit cell of a single repeating unit is 1 um-12 μm.
The structure of the two emitter grooves can effectively improve the circulation path of hole current, so that the hole current can vertically flow upwards into the emitter metal 1 from the bottom and the side wall of the emitter groove with reference to the ground potential, and through the N-type carrier storage layer 6 and the first P-type body area 51 between the two emitter grooves, thereby reducing the hole current in the area below the N + emission area 3, inhibiting the opening of a PN junction formed between the P-type body area 5 and the N + emission area 3, and remarkably improving the short-circuit resistance, the latch-up resistance and the large-current turn-off capability of the device.
The emitter trench is deeper than the gate trench, which is beneficial to further reducing short-circuit current of the device and improving a circulation path of hole current, so that the hole current can vertically flow into the emitter metal upwards from the bottom and the side wall of the emitter trench with deeper reference ground potential, thereby further reducing the hole current in the area below the N + emitter region 3 and further inhibiting the opening of a PN junction formed by the P-type body region and the N + emitter region 3. In addition, due to the deeper emitter trenches, which increases the capacitive coupling between the gate trenches and the emitter trenches, the emitter trenches and the P-type collector region 10, the miller capacitance Cgc is reduced. In the turn-off process of the IGBT device, the deeper emitter groove is more beneficial to accelerating the extraction of the excess carriers, and both the deeper emitter groove and the deeper emitter groove reduce the turn-off loss of the device. When the IGBT is conducted, the carrier concentration on one side of the front N + emitting region 3 can be improved through the deeper emitter groove, the conductance modulation effect of the device is enhanced, the forward conduction voltage drop of the IGBT is reduced, and the compromise relation between the forward conduction voltage drop and the turn-off loss is optimized.
It will be appreciated that the conductivity and doping of the above materials or regions may be varied and the conductivity of the materials or regions may be suitably varied depending on the application. For example, when the collector region 10 of the IGBT device is N-type, the N-type field stop layer 9 changes to the P-type field stop layer 9, and the conductivity type of the material of the other regions changes accordingly.
Fig. 2 shows a cross-sectional view of a trench gate IGBT device 200 according to yet another embodiment of the invention. Compared with the IGBT device 100, the IGBT device 200 further includes two P-type floating buried layers 13. Each floating P-type buried layer 13 is located at the bottom of a corresponding emitter trench. In this embodiment, when the power IGBT device 200 is forward voltage-resistant, the floating P-type buried layer at the bottom of the emitter trench can effectively reduce the high electric field peak at the bottom of the emitter trench, thereby further improving the breakdown voltage of the device and enhancing the reliability of the device.
Fig. 3 shows a cross-sectional view of a trench-gate IGBT device 300, according to yet another embodiment of the invention. In IGBT device 300, first P-type body region 51 between the two emitter trenches has a deeper junction depth than IGBT device 100, which is equal to or greater than the junction depth of P-type body region 5, but equal to or less than the depth of the two emitter trenches. In one embodiment, the junction depth of the first P type body region 51 is greater than the junction depth of the N type carrier storage layer 6.
In the above embodiment, when the device is forward voltage-resistant, the deep first P-type body region 51 can effectively shield the high electric field of the dielectric layer in the emitter trench, and reduce the electric field strength, thereby improving the breakdown voltage of the device and enhancing the reliability of the device.
In one embodiment, the width of first P-type body region 51 between two emitter trenches in IGBT device 300, i.e., the distance between the two emitter trenches, is adjustable. The width of the first P-type body region 51 may be further reduced or further increased. Changing the width of the first P-type body region 51 can effectively adjust the magnitude of the forward conduction voltage drop and the short-circuit current, thereby optimizing and improving the compromise relationship between the short-circuit safe working region and the forward conduction voltage drop.
Fig. 4 shows a cross-sectional view of a trench-gate IGBT device 400 according to yet another embodiment of the invention. Compared with the IGBT device 300, the IGBT device 400 further includes two P-type floating buried layers 13 therein. Each floating P-type buried layer 13 is located at the bottom of a corresponding emitter trench. In this embodiment, when the IGBT device 400 is forward voltage-resistant, the floating P-type buried layer at the bottom of the emitter trench may effectively reduce the peak value of the high electric field at the bottom of the emitter trench, thereby further improving the breakdown voltage of the device and enhancing the reliability of the device.
Fig. 5 shows a cross-sectional view of a trench-gate IGBT device 500, according to yet another embodiment of the invention. The IGBT device 500 is a particular embodiment of the IGBT device 400, and when the width of the first P-type body region 51 is narrowed and the depth is deeper, the first P-type body region 51 and the two floating P-type buried layers 13 contact each other and form an integral second P-type body region 52.
According to still other embodiments of the present invention, in the power IGBT device shown in fig. 1 to 5, the first P-type body region 51 (and/or the second P-type body region 52) and the emitter metal 1 may be separated by the interlayer dielectric layer 2, so that the first P-type body region 51 (and/or the second P-type body region 52) becomes a floating body region. For example, fig. 6 illustrates a cross-sectional view of a trench gate IGBT device 600 according to yet another embodiment of the invention. In contrast to IGBT device 400, in IGBT device 600, first P-type body region 51 and emitter metal 1 are separated by interlayer dielectric layer 2, so that first P-type body region 51 becomes a floating P-type region 53. In the example shown in fig. 6, part of the interlayer dielectric layer 2 also covers part of the emitter trench, which is caused by the reasons of process implementation and the like in the manufacturing process, so as to completely separate the floating P-type region 53 from the emitter metal 1, and this should not be construed as a limitation to this application. The floating body region can further improve the concentration of hole carriers on one side of the emitter, so that the conductivity modulation effect is enhanced, and the forward conduction voltage drop VCE of the device is reduced. Meanwhile, the compromise relationship between the short-circuit safe working area and the forward conduction voltage drop can be optimized and improved. For the sake of brevity, cross-sectional views of device embodiments of the remaining other power IGBT devices of fig. 1-5 after the first P-type body region 51 (and/or the second P-type body region 52) is changed into a floating body region will not be shown here, but these embodiments are within the scope of the present invention.
Fig. 7A-7I illustrate process steps for fabricating the trench gate IGBT device 600 of fig. 6, according to one embodiment of the invention.
FIG. 7A: an N-type semiconductor substrate is selected as an N-drift region 8, and an N-type carrier storage layer 6 is formed on the top of the N-drift region 8 in an ion injection mode. In one embodiment, the N-type carrier storage layer 6 may be formed by implanting phosphorus or arsenic. The thickness and doping profile of the N-drift region 8 are chosen depending on the desired off-state characteristics of the drift region (such as the breakdown voltage). In a further embodiment, the N-drift region 8 may also be grown on the silicon substrate by means of vapor phase epitaxy.
FIG. 7B: an optional gate trench mask 31 is formed on the top surface of the N-type drift region 8 followed by an etching process to form the gate trench 7. In one embodiment, the gate trench mask 31 is formed by spin coating a photoresist on the oxide layer and exposing and developing. In one embodiment, the gate trench 7 may be formed by a reactive ion etching process through an optional gate trench mask into the N-type drift region 8. In one embodiment, the depth of the gate trench 7 is 3 to 6 μm.
FIG. 7C: the gate trench mask 31 is removed and a gate dielectric 71 is formed in the gate trench 7. In a preferred embodiment, gate dielectric 71 comprises thermal oxide grown on the surface of gate trench 7, and the thickness of gate dielectric 71 is dependent on the desired gate-source operating voltage that it can support.
After forming the gate dielectric 71, the gate trench 7 will be filled with a conductive material to form a gate 72. In one embodiment, a deposition process step may be used to fill the conductive material. In one embodiment, the conductive material may comprise any suitable conductive material, such as doped polysilicon, silicide, or metal, among others. In a preferred embodiment, N-doped polysilicon is selected as the conductive material.
FIG. 7D: an optional emitter trench mask 32 is formed on top of the structure formed in fig. 7C, followed by an etching process to form two identical emitter trenches 12. Likewise, in one embodiment, emitter trench mask 32 is formed by spin coating a photoresist on the oxide layer and developing by exposure. In one embodiment, emitter trench 12 can be formed by a reactive ion etching process through optional emitter trench mask 32 into N-type drift region 8. In one embodiment, the depth of emitter trench 12 is 4-8 μm. In one embodiment, the emitter trench mask comprises silicon nitride. In another embodiment, the emitter trench mask comprises silicon dioxide.
FIG. 7E: and removing the emitter trench mask 32, and forming a floating P-type buried layer 13 at the bottoms of the two emitter trenches 12 by means of ion implantation, and simultaneously forming a P-type body region 5 on the top surface of the N-type carrier storage layer 6. Wherein, the depth of the P-type ion implantation between the two emitter trenches exceeds the junction depth of the N-type carrier storage layer 6, and a floating P-type region 53 is formed.
FIG. 7F: an emitter trench dielectric 121 is formed in two identical emitter trenches 12 and filled with an emitter trench conductive material 122. The quality of the surface of emitter trench 12 can be improved by sacrificial oxidation and oxide etch processes prior to forming emitter trench dielectric 121. Emitter trench dielectric 121 comprises one or more suitable dielectric materials. In some embodiments, thermally grown oxide, deposited oxide (such as LPCVD TEOS), or a combination of these layers may be used to form emitter trench dielectric 121. In a preferred embodiment, emitter trench dielectric 121 comprises thermal oxide grown on the surface of emitter trench 12. In some embodiments, the thickness of the dielectric layer at the bottom of both emitter trenches 12 is greater than the thickness of the sidewalls of emitter trenches 12.
After formation of emitter trench dielectric 121, both emitter trenches 12 will be filled with emitter trench conductive material 122. In one embodiment, a deposition process step may be employed to fill emitter trench conductive material 122. In one embodiment, the conductive material 122 may comprise any suitable conductive material, such as doped polysilicon, silicide, or metal, among others. In a preferred embodiment, optionally N-doped polysilicon is used as the conductive material 122.
FIG. 7G: and forming a P type body region 5, an N + emission region 3 and a P + body contact region 4 on the top surface of the N-drift region 8 by means of photoetching and ion implantation. In one embodiment, the P-type body region 5 is formed by implanting boron or boron difluoride plasma. In one embodiment, the N + emitter region 3 is formed by means of photolithography, implantation of phosphorus or arsenic. In one embodiment, the P + body contact regions 4 are formed by implanting boron or boron difluoride plasma.
FIG. 7H: and growing an interlayer dielectric layer 2 on the top surface of the device formed in fig. 7G, selectively etching off part of the interlayer dielectric layer 2 in a photoetching and etching mode, and finally depositing an emitter metal 1 on the top surface of the formed structure. In one embodiment, the emitter metal 1 will be formed by means of evaporation or sputtering.
FIG. 7I: and turning over the silicon wafer, thinning the drift region 8, and forming an N-type field stop layer 9 and a P-type collector region 10 on the back of the drift region 8 in an ion implantation mode. In one embodiment, the N-type field stop layer 9 is formed by implanting phosphorus, arsenic or hydrogen plasma. In one embodiment, P-type collector region 10 is formed by implanting a boron or boron difluoride plasma.
Finally, a collector metal 11 will be redeposited on top of the P-type collector region 10. In one embodiment, the collector metal 11 will be formed by means of evaporation or sputtering. The wafer is flipped again to form IBGT device 600.
While the present invention has been described with reference to several exemplary embodiments, it is understood by those of ordinary skill in the relevant art that the terms used in the embodiments of the present invention disclosed are intended to be illustrative and exemplary, but not limiting, of the invention, and are intended to describe specific embodiments without limiting the invention. Furthermore, various modifications in form and detail of the disclosed embodiments of the invention may occur to those skilled in the art without departing from the spirit and concept of the invention and, therefore, such modifications are intended to be included within the scope of the present invention as defined in the appended claims and their equivalents.
Claims (10)
1. A trench-gate IGBT device, comprising:
a semiconductor substrate having a first conductivity type;
the collector region is of a second conduction type and is formed at the bottom of the semiconductor substrate;
a drift region of the first conductivity type overlying the collector region;
a carrier storage layer having a first conductivity type formed on the drift region;
a body region having a second conductivity type formed over the carrier storage layer;
an emitter region of a first conductivity type formed over the body region on top of the semiconductor substrate;
the gate region is formed in a gate region groove, and the gate region groove vertically extends downwards from the top surface of the device to a first depth and enters the drift region; and
first and second emitter trench structures formed within the first and second emitter trenches, respectively, each emitter trench structure including an emitter dielectric and an emitter conductive material filled in the emitter trench, each emitter trench extending vertically downward from the top surface of the device a second depth into the drift region, the emitter dielectric separating the emitter conductive material from the body regions, the carrier storage layer, and the drift region, wherein the first and second emitter trench structures are laterally separated by the body regions.
2. The trench gate IGBT device of claim 1, wherein the second depth is greater than the first depth.
3. The trench-gate IGBT device of claim 1, further comprising two floating layers of the second conductivity type at the bottom of the first emitter trench and at the bottom of the second emitter trench, respectively.
4. The trench-gate IGBT device of claim 1, wherein a depth of the body region between the first emitter trench and the second emitter trench is greater than a depth of the body region adjacent the gate trench and less than the second depth.
5. The trench gate IGBT device of claim 1, wherein a width of the body region between the first emitter trench structure and the second emitter trench structure is adjustable.
6. The trench gate IGBT device of claim 3, wherein a body region between the first emitter trench and the second emitter trench contacts the floating layer.
7. The trench gate IGBT device of claim 1, wherein a body region between the first emitter trench and the second emitter trench is separated from the emitter region by an interlayer dielectric layer.
8. The trench gate IGBT device of claim 1, further comprising emitter metal, the emitter conductive material being coupled through emitter metal to an emitter region and a body region between the first emitter trench structure and the second emitter trench structure.
9. A manufacturing method of a trench gate IGBT device comprises the following steps:
forming a carrier storage layer on the top of the semiconductor substrate;
forming a gate region groove from the top surface of the semiconductor substrate to penetrate through the carrier storage layer downwards;
filling the grid region groove with a conductive material to form a grid region;
forming a first emitter trench and a second emitter trench from the top surface of the semiconductor substrate down through the carrier storage layer;
forming a dielectric layer on inner walls of the first emitter trench and the second emitter trench;
filling the first emitter trench and the second emitter trench with a conductive material to form a first emitter trench structure and a second emitter trench structure; and
a first body region is formed between the first emitter trench and the second emitter trench.
10. The method of fabricating a trench gate IGBT device according to claim 9, further comprising: and forming a floating buried layer at the bottom of the first emitter trench and the bottom of the second emitter trench.
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