CN116936611B - Low-loss bidirectional conduction IGBT structure and preparation method - Google Patents
Low-loss bidirectional conduction IGBT structure and preparation method Download PDFInfo
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- 230000002457 bidirectional effect Effects 0.000 title claims abstract description 18
- 238000002360 preparation method Methods 0.000 title claims abstract description 10
- 230000004888 barrier function Effects 0.000 claims abstract description 51
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims abstract description 28
- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 28
- 239000001301 oxygen Substances 0.000 claims abstract description 28
- 238000005468 ion implantation Methods 0.000 claims abstract description 13
- 239000010410 layer Substances 0.000 claims description 77
- 229910052751 metal Inorganic materials 0.000 claims description 59
- 239000002184 metal Substances 0.000 claims description 59
- 230000000903 blocking effect Effects 0.000 claims description 51
- 238000000034 method Methods 0.000 claims description 42
- 230000008569 process Effects 0.000 claims description 41
- 230000006698 induction Effects 0.000 claims description 30
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 26
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 19
- 238000005229 chemical vapour deposition Methods 0.000 claims description 17
- 238000011049 filling Methods 0.000 claims description 17
- 229920005591 polysilicon Polymers 0.000 claims description 16
- 238000010438 heat treatment Methods 0.000 claims description 14
- 235000012239 silicon dioxide Nutrition 0.000 claims description 13
- 239000000377 silicon dioxide Substances 0.000 claims description 13
- 238000011161 development Methods 0.000 claims description 12
- 238000009792 diffusion process Methods 0.000 claims description 12
- 238000001312 dry etching Methods 0.000 claims description 12
- 238000002955 isolation Methods 0.000 claims description 12
- 238000004528 spin coating Methods 0.000 claims description 12
- 238000000137 annealing Methods 0.000 claims description 11
- 239000000758 substrate Substances 0.000 claims description 11
- 238000000151 deposition Methods 0.000 claims description 10
- 238000007667 floating Methods 0.000 claims description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 6
- 238000005240 physical vapour deposition Methods 0.000 claims description 6
- 229910052710 silicon Inorganic materials 0.000 claims description 6
- 239000010703 silicon Substances 0.000 claims description 6
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 4
- 230000008021 deposition Effects 0.000 claims description 4
- 238000005516 engineering process Methods 0.000 claims description 4
- 239000011229 interlayer Substances 0.000 claims description 4
- 238000004518 low pressure chemical vapour deposition Methods 0.000 claims description 3
- 238000001883 metal evaporation Methods 0.000 claims description 3
- 230000003647 oxidation Effects 0.000 claims description 3
- 238000007254 oxidation reaction Methods 0.000 claims description 3
- 238000007789 sealing Methods 0.000 claims description 3
- 238000000407 epitaxy Methods 0.000 claims description 2
- 238000000427 thin-film deposition Methods 0.000 claims description 2
- 238000004519 manufacturing process Methods 0.000 claims 1
- 230000005764 inhibitory process Effects 0.000 abstract description 3
- 239000004065 semiconductor Substances 0.000 abstract description 3
- 230000010354 integration Effects 0.000 abstract description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 abstract 1
- 229910052796 boron Inorganic materials 0.000 abstract 1
- 230000000694 effects Effects 0.000 description 8
- 230000001939 inductive effect Effects 0.000 description 5
- 238000000605 extraction Methods 0.000 description 4
- 238000002347 injection Methods 0.000 description 4
- 239000007924 injection Substances 0.000 description 4
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 3
- 238000013461 design Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 229910052698 phosphorus Inorganic materials 0.000 description 3
- 239000011574 phosphorus Substances 0.000 description 3
- 238000005530 etching Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000006798 recombination Effects 0.000 description 2
- 238000005215 recombination Methods 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- 230000001629 suppression Effects 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- -1 drift region Substances 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 239000010408 film Substances 0.000 description 1
- 238000011065 in-situ storage Methods 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 230000037361 pathway Effects 0.000 description 1
- 230000000750 progressive effect Effects 0.000 description 1
- 230000001105 regulatory effect Effects 0.000 description 1
- 230000035945 sensitivity Effects 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
- 230000007306 turnover Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
- H01L29/66333—Vertical insulated gate bipolar transistors
- H01L29/66348—Vertical insulated gate bipolar transistors with a recessed gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
- H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
- H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
Abstract
The application provides a low-loss bidirectional conduction IGBT structure and a preparation method thereof, and belongs to the field of semiconductor power devices. The structure is based on the traditional field cut-off IGBT structure, the boron doping concentration of a part of collector P-type region is reduced, a low-doped P-type barrier region is formed, then a collector N+ region is formed at the back of the P-type barrier region by ion implantation, a wrapping structure is formed, the center of the wrapping structure is etched and filled to form a short-circuit collector split trench, and an N-type buffer layer, a collector N-type region, the P-type barrier region and the short-circuit collector split trench form a bidirectional conduction NMOS structure. The two-way conduction NMOS structure and the collector P-type region are isolated by the deep oxygen trench, so that the two-way conduction NMOS structure has independent electrical characteristics. According to the application, a bidirectional conduction NMOS structure is integrated on the premise of no need of additionally introducing a control electrode, the turn-off speed is obviously improved, the turn-on loss of the device is further reduced, the lateral voltage turn-back inhibition size of the device is greatly reduced, and the chip integration level is improved.
Description
Technical Field
The application belongs to the technical field of semiconductor power devices, and particularly relates to a low-loss bidirectional conduction IGBT structure and a preparation method thereof.
Background
The insulated gate bipolar transistor (Insulated Gate Bipolar Transistor, IGBT) is a commonly used power semiconductor device, is mainly used in high-power applications such as switching power supplies and motor driving, and is easy to generate higher energy loss due to the fact that the insulated gate bipolar transistor is often operated in high-voltage and high-current environments, so that the heating of the device is increased, and the reliability and the service life of the device are affected.
The IGBT device may exhibit a tail current during turn-off, also referred to as a tail current (tai 1 current). The tail current is caused by electrons in the drift region, when the Gate electrode (Gate) applies negative voltage in the turn-off process of the IGBT so that the IGBT starts to turn off, the boundary potential of the P-type base region gradually propagates to the N-type drift region to block the electrons in the drift region in situ, so that the electrons can only disappear through recombination with residual positive charges in the drift region, and leakage current generated in the recombination process is the tail current, so that the turn-off time of the device is greatly increased, and higher turn-off loss is caused. Therefore, adding an electron extraction path on the collector side becomes an advantageous attempt to accelerate device turn-off and reduce loss.
However, this structure often suffers from a common problem: the electron path is the collector N+ region, the P-type base region, the N-type drift region and the electron path (N-type doped region), the device is conducted in a MOS mode, at the moment, the voltage drop on a PN junction formed by the collector P region and the N-type buffer layer is insufficient to enable the PN junction to be opened, holes cannot be injected into the drift region by the collector P region, the device works in a unipolar mode, the drift region has no conductivity modulation effect, and the on-resistance is large. When the current density rises, a PN junction formed by the collector electrode P region and the N type buffer layer is opened, holes are injected into the N type drift region in a large quantity by the collector electrode P region, the device is converted into a bipolar conduction mode, the drift region generates a conductivity modulation effect, the on resistance is obviously reduced, a negative resistance region is generated, different current magnitudes appear under the same voltage, and the parallel connection of the device is extremely unfavorable.
Disclosure of Invention
In order to solve the problems in the background technology, the application provides a novel IGBT structure and a preparation method thereof, wherein a low-doped floating P-type isolation region is designed at the back, an N+ region is prepared, a split groove is formed by etching, filling and preparing a short-circuit collector metal gate and an induction gate, a bidirectional conduction NMOS structure is formed to accelerate the turn-off speed and enhance the reverse conduction, and a deep oxygen groove is designed to isolate the collector P region and modulate an electron path to inhibit the voltage reverse phenomenon.
The application provides a low-loss bidirectional conduction IGBT structure, which comprises an N-type drift region, wherein a polysilicon gate, a P-type base region, an emitter N+ region, an emitter P+ region and emitter metal are arranged above the N-type drift region from bottom to top, and the polysilicon gate is of a groove structure; the N-type drift region comprises an N-type buffer layer, a collector electrode P region and a collector electrode metal which are stacked up and down, and is characterized in that: a bidirectional conduction NMOS structure and a deep oxygen trench are further arranged below the N-type drift region, wherein the bidirectional conduction NMOS structure comprises a short-circuit collector metal gate, an induction gate, a left collector N+ region, a right collector N+ region, a left P-type blocking region and a right P-type blocking region; the short-circuit collector metal gate is connected with the collector metal and is wrapped by an oxide layer together with the induction gate to form a short-circuit collector split groove; the left P-type blocking area and the right P-type blocking area are distributed symmetrically about the short-circuit collector splitting groove, and floating is not directly electrically connected; the left collector N+ region and the right collector N+ region are symmetrically distributed relative to the short collector splitting groove, are respectively wrapped by the left P-type blocking region and the right P-type blocking region, and are connected with collector metal; the deep oxygen trench is positioned between the left P-type barrier region and the collector electrode P region; the N-type buffer layer is positioned on the right side of the deep oxygen trench, the left side P-type blocking area and the upper side of the right side P-type blocking area.
Preferably, the shorted collector metal gate and the induction gate are wrapped by an oxide layer to form a shorted collector split trench gate, wherein the shorted collector metal gate, the right collector n+ region, the right P-type blocking region and the N-type buffer layer form a forward conduction NMOS structure; the induction gate, the left collector N+ region, the left P-type blocking region and the N-type buffer layer form a reverse conduction NMOS structure.
Preferably, the inductive gate is not directly electrically connected to a floating gate, the filling material can be polysilicon or metal, the top of the inductive gate is leveled with the top of the left P-type barrier region, and the bottom of the inductive gate is leveled with the top of the left collector N+ region.
Preferably, the doping concentration of the left side P type barrier region and the right side P type barrier region is lower than that of the collector electrode P region, and the doping concentration is 1e 14-1 e 16; the N+ region of the collector electrode has a doping concentration of 1e 16-1 e 18.
Preferably, the thickness range of the left collector N+ region and the right collector N+ region is 0.2-0.5 times of the thickness of the left P-type barrier region and the right P-type barrier region; the width range of the left collector N+ region and the right collector N+ region is 0.4-0.6 times of the width of the left P-type barrier region and the right P-type barrier region.
Preferably, the depth of the deep oxygen trench is not lower than the thickness of the collector P region, so as to isolate the electrical characteristics of the left P-type barrier region and the collector P region.
Preferably, the depth of the deep oxygen trench is higher than the sum of the thickness of the collector P region and the thickness of the N-type buffer layer, so that the electron flow path is modulated, and the voltage folding phenomenon is restrained.
Preferably, the tops of the short-circuit collector metal gate and the induction gate are thick oxide layers with the thickness of 0.5-1.0 micrometers; the thickness of the oxide layer on the right side of the short-circuit collector metal gate is 0.1-0.15 microns; and the thickness of the oxide layer on the left side of the induction gate is 0.05 microns.
The application provides a preparation method of a low-loss bidirectional conduction IGBT structure, which comprises the following steps:
s1, providing an assembly formed by sequentially stacking substrate substrates and drift layers from bottom to top;
s2, forming a P-type base region on the drift layer through a diffusion process and heat treatment;
s3, forming an emitter P+ region on the P-type base region through a diffusion process and heat treatment;
s4, forming an emitter N+ region on the emitter P+ region through an ion implantation process and heat treatment;
s5, preparing a groove structure in the center of the emitter N+ region through spin coating, exposure, development and dry etching processes;
s6, growing a gate oxide layer on the side wall of the groove sequentially through a furnace tube thermal oxidation process, and filling polycrystal by using low-pressure chemical vapor deposition equipment to form a polysilicon gate;
s7, generating interlayer dielectric silicon dioxide and front metal by adopting a thin film deposition technology;
s8, turning over the silicon wafer, thinning the substrate by adopting a thinning process, and forming an N-type buffer layer through ion implantation and annealing treatment;
s9, adopting a back epitaxy process, and carrying out epitaxial growth, diffusion and annealing on the back of the substrate to form a collector electrode P region and a P type isolation region;
s10, forming a collector N+ region in the P-type barrier region through ion implantation and heat treatment;
s11, preparing a groove structure in the center of the collector electrode N+ region through spin coating, exposure, development and dry etching processes; at this time, the collector N+ region and the P-type barrier region are divided into a left collector N+ region, a right collector N+ region, a left P-type barrier region and a right P-type barrier region;
s12, filling a groove oxide layer in the groove structure by adopting a chemical vapor deposition CVD process;
s13, forming a split groove structure on the filled groove by adopting the steps of spin coating, exposure, development and dry etching;
s14, filling polycrystalline silicon into the split grooves by adopting a chemical vapor deposition CVD process to form induction gates, and filling aluminum metal into the split grooves by adopting a physical vapor deposition PVD process to form short-circuit collector metal gates;
s15, depositing silicon dioxide by adopting a chemical vapor deposition CVD process, and sealing the induction gate to float;
s16, forming a groove structure at the junction of the left P-type isolation region and the collector electrode P region through the steps of spin coating, exposure, development and dry etching;
s17, depositing silicon dioxide in the groove through a chemical vapor deposition CVD process to form a deep oxygen groove;
s18, forming collector metal by adopting a metal evaporation process.
Preferably, the thickness of the right oxide layer in the split trench in the S13 is 0.1~0.2/>The thickness of the left oxide layer is 0.05 +.>The thickness of the top oxide layer is 0.5 +.>~1.0/>；
The filling size of the polysilicon in the S14 is that the top is leveled with the top of the P-type barrier region, and the bottom is leveled with the top of the collector N+ region;
the thickness of the silicon dioxide deposition in the S15 is consistent with the thickness of the collector N+ region.
Compared with the prior art, the application has the following advantages and beneficial effects:
the application integrates a bidirectional conduction NMOS structure on the premise of no extra control electrode, wherein a short-circuit collector metal gate, a right collector N+ region, a right P-type blocking region and an N-type buffer layer form a forward conduction NMOS structure; the induction gate, the left collector N+ region, the left P-type blocking region and the N-type buffer layer form a reverse conduction NMOS structure, which respectively provides an electronic path for the device when the device is turned off and reversely conducted, and improves the turn-off speed and the forward and reverse bidirectional conduction capability of the device. The application can improve the turn-off speed of the device on the premise of no voltage reverse phenomenon by adjusting the concentration of the P-type isolation region and the depth of the deep oxygen trench, thereby reducing the turn-on loss of the device; the reverse conduction capacity of the device is adjusted by adjusting the concentration of the N+ region of the collector, and the turn-off speed of the device is hardly influenced; compared with the traditional RC-IGBT device, the turn-off speed of the application is obviously improved, the lateral voltage turn-back inhibition size of the device is greatly reduced, and the chip integration level is improved.
Drawings
In order to more clearly illustrate the application or the technical solutions of the prior art, the following description will be given simply with reference to the accompanying drawings, which are used in the description of the embodiments or the prior art, it being evident that the following description is only one embodiment of the application, and that other drawings can be obtained from these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic structural view of the present application.
FIG. 2 is a graph showing the effect of P-type spacer concentration on voltage foldback inhibition in accordance with the present application.
FIG. 3 is a diagram showing the mechanism of voltage folding phenomenon generated when the concentration level of the P-type isolation region is low in the application.
FIG. 4 is a graph showing the effect of deep oxygen trench modulation electron flow path in the present application.
Fig. 5 is an equivalent schematic diagram of a deep oxygen trench modulated electron flow path in the present application.
FIG. 6 is a graph showing the effect of deep oxygen trench depth on voltage turn-around suppression in the present application.
Fig. 7 is a diagram of an electron extraction pathway when the structural device of the present application is turned off.
Fig. 8 is a comparison of the turn-off curve of the present application with a conventional RC-IGBT at the same turn-on voltage drop.
Fig. 9 is a graph of the enhancement effect of the sense gate on device reverse conduction when a reverse voltage is applied to the collector of the present application.
Fig. 10 shows reverse conduction curves of the collector n+ region of the present application at different doping concentrations.
FIG. 11 is a front side process flow of the preparation process of the present application.
FIG. 12 is a backside process flow during the preparation of the present application.
1. A metal gate; 2. an inductive grating; 3. a left collector n+ region; 4. a right collector n+ region; 5. a left P-type barrier region; 6. a right side P-type blocking region; 7. deep oxygen trenches; an N-type buffer layer; an n-type drift region; a p-type base region; 11. an emitter n+ region; 12. an emitter metal; 13. a polysilicon gate; 14. an emitter p+ region; 15. and an N-type buffer layer; 16. a collector P region; 17. collector metal.
Detailed Description
The technical solutions in the specific embodiments of the present application are clearly and completely described below with reference to the accompanying drawings in the present application.
Referring to fig. 1, the application provides a low-loss bidirectional conducting IGBT structure, which comprises a short collector metal gate 1, an inductive gate 2, a left collector n+ region 3, a right collector n+ region 4, a left P-type blocking region 5, a right P-type blocking region 6, a deep oxygen trench 7, an N-type buffer layer 8, an N-type drift region 9, a P-type base region 10, an emitter n+ region 11, an emitter metal 12, a polysilicon gate 13, an emitter p+ region 14, an N-type buffer layer 15, a collector P region 16, and a collector metal 17. The short-circuit collector metal grid 1 is connected with the collector metal 17 and is wrapped by an oxide layer with the induction grid 2 to form a short-circuit collector split groove; the left P-type blocking area 5 and the right P-type blocking area 6 are distributed symmetrically about the short collector split trench, and floating is not directly electrically connected; the left collector N+ region 3 and the right collector N+ region 4 are distributed symmetrically about the short collector splitting trench, are respectively wrapped by the left P-type blocking region 5 and the right P-type blocking region 6, and are connected with the collector metal 17; the deep oxygen trench 7 is positioned between the left P-type barrier region 5 and the collector P region 16; the N-type buffer layer 8 is positioned on the right side of the deep oxygen trench 7 and on the upper sides of the P-type barrier regions 5 and 6. The rest structure is consistent with the traditional FS-IGBT, and the collector metal 17, the collector P region 16, the N type buffer layer 15, the N type drift region 9, the polysilicon trench gate 13, the P type base region 10, the emitter P+ region 14, the emitter N+ region 11 and the emitter metal 12 are sequentially arranged from bottom to top. The left side and right side terms are all divided by taking the short-circuit collector metal grid 1 as the center.
The short-circuit collector metal gate 1 and the induction gate 2 are wrapped by an oxide layer to form a short-circuit collector split trench gate (SCST), wherein the short-circuit collector metal gate 1, the right-side collector N+ region 4, the right-side P-type barrier region 6 and the N-type buffer layer 8 form a forward conduction NMOS structure; the induction gate 2, the left collector N+ region 3, the left P-type barrier region 5 and the N-type buffer layer 8 form a reverse conduction NMOS structure.
The short-circuit collector metal grid 1 is connected with the collector metal 17 and is made of aluminum; the induction grid 2 is not directly electrically connected and is a floating grid; the filling material of the sensing gate 2 can be polysilicon or metal, the top of which is level with the top of the left P-type barrier region 5, and the bottom of which is level with the top of the left collector n+ region 3.
Referring to FIG. 2, in this embodiment, to show the effect of different parts of the design of the present application on the electrical characteristics of the device, the doping concentrations of the left-side P-type barrier region 5 and the right-side P-type barrier region 6 are set to 1e15~1e16/>And (3) the room(s). According to a PN junction built-in potential formula: />
It can be seen that the larger the concentration difference between the left P-type blocking region 5 and the right P-type blocking region 6 and the collector P-region 16, the larger the on-state voltage difference between the P-type blocking region and the collector P-region and the P-type buffer layer, and the larger the hole injection efficiency difference, the more obvious the voltage kink phenomenon.
Referring to fig. 3, in the initial turn-on stage, since the collector voltage is small, electrons are accumulated at both sides of the PN junction formed by the collector P region 16 and the N-type buffer layer 15 and the PN junction formed by the left P-type blocking region 5, the right P-type blocking region 6 and the N-type buffer layer 8, but the voltage is insufficient to turn on the junction, so that the hole injection efficiency is not high, wherein the injection efficiency of the left P-type blocking region 5 and the right P-type blocking region 6 with lower doping concentration is significantly lower than that of the collector P region 16 with higher doping concentration. The built-in potential of the PN junction formed by the left side P type barrier region 5, the right side P type barrier region 6 and the N type buffer layer 8 is smaller, the PN junction is started in advance, and the hole injection efficiency is lower than that of the collector P region 16 because the doping concentration of the left side P type barrier region 5 and the right side P type barrier region 6 is lower, and when the current intensity is increased to the opening of the PN junction formed by the collector P region 16 and the N type buffer layer 15, the voltage reverse phenomenon occurs.
Referring to fig. 4 to 6, in order to show the influence of different parts of the design of the present application on the electrical characteristics of the device in this embodiment, deep oxygen trenches are set to a depth of 2.0 μm to 4.0 μm. Although the concentration differences between the left and right P-type barrier regions 5, 6 and the collector P-region 16 still result in voltage foldback, the extremely small built-in potential difference makes the voltage foldback sensitive to the electron flow path resistance and length and sensitivity. Based on this principle, the application further proposes regulating the electron flow path through the deep oxygen trench to make electrons flow through the buffer layer, drift region, buffer layer and flow to the collector, and reducing the junction voltage between the collector P region 16 and the N-type buffer layer 15 fromModulated as->And because drift region resistance is far greater than the buffer layer, and the existence of P separation region makes the device very sensitive to electron flow path resistance again, and under the cooperation of the two, the device can obtain obvious voltage under very small lateral dimension and turn over the suppression effect, even eliminates the phenomenon of turning over completely.
Referring to fig. 7 and 8, when the device is turned off, the collector voltage will rise to the blocking voltage, because the application uses the short-circuit collector metal gate 1 connected with the collector metal 17 as the control gate of the forward conduction NMOS structure, the traditional collector end structure will make the electric field distribution in the right P-type blocking region 6 more uniform, and it is difficult to form an inversion region, so that the forward conduction NMOS structure can not be turned on to form an electron extraction channel when turned off, and the application firstly uses the deep oxygen trench 7 to isolate the potential influence of the collector P region 16 on the left P-type blocking region 5 and the right P-type blocking region 6, and then connects the collector with the left collector n+ region 3 and the right collector n+ region 4, in this way, the left P-type blocking region 5 and the right P-type blocking region 6 float, and finally the right P-type blocking region 6 and the left collector n+ region 3 and the right collector n+ region 4 form an ideal hole depletion region by using the wrapping structure formed by the collector voltage when the device is turned off. Through the scheme, when the device is turned off, the forward conduction NMOS structure formed by the short-circuit collector metal gate 1, the N-type buffer layer 8, the right P-type blocking region 6 and the right collector N+ region 4 is turned on, an extraction passage is provided for electrons, the tail current of the device is greatly reduced, and the turn-off loss is further reduced.
Referring to fig. 9 and 10, in this embodiment, to show the effect of different parts of the design of the present application on the electrical characteristics of the device, the doping concentrations of the left collector n+ region 3 and the right collector n+ region 4 are set to be 1e15~1e18/>And (3) the room(s). When the induction grid 2 is in reverse conduction, as the floating grid is not directly electrically connected, positive charges are induced on the surface of the induction grid 2 when the collector metal 17 is connected with negative potential, the induced charges attract electrons in the left P-type blocking area 5 to form an inversion layer, an extra electron channel is provided for reverse conduction of the device, and the reverse conduction capacity of the device is enhanced. Meanwhile, as the concentration of the left collector N+ region 3 and the right collector N+ region 4 increases, the reverse conduction capability of the device is obviously enhanced.
Referring to fig. 11 and 12, the preparation method of the IGBT structure provided by the embodiment of the application is as follows:
s1, providing an assembly formed by sequentially stacking a substrate and a drift layer from bottom to top, wherein the assembly is shown in (a);
in the embodiment of the application, the doping concentration of the drift region is 8e13。
S2, forming a P-type base region on the drift layer through a diffusion process and heat treatment, wherein the P-type base region is shown in (b); specifically, the upper surface of the provided silicon wafer is subjected to thermal diffusion and annealing treatment at the temperature of 1000-1200 ℃ to form the silicon wafer with the thickness of 1.5~2.0/>Doping concentration 1e 17->~1.2e17/>P-type base region of (a).
S3, forming an emitter P+ region on the P-type base region through a diffusion process and heat treatment, wherein the emitter P+ region is shown in (c); specifically, the upper surface of the formed P-type base region is subjected to thermal diffusion and annealing treatment to form a thickness of 0.5~0.8/>Doping concentration 1e 19->~1.2e19/>Emitter p+ regions of (a).
S4, forming an emitter N+ region on the emitter P+ region (14) through an ion implantation process and heat treatment, wherein the emitter N+ region is shown as (d); specifically, the upper surface of the formed emitter P+ region is treated by phosphorus ion implantation and annealing to formThickness of 0.5~0.8/>Width 2.8%>~3.2/>Doping concentration 1e 19->~1.2e19/>Emitter n+ region of (a).
S5, preparing a groove structure at the center of the emitter N+ region through processes such as spin coating, exposure, development, dry etching and the like, wherein the groove structure is shown in (e); specifically, the trench width is 0.8~1.2/>Depth 1.8%>~2.0/>。
S6, growing a gate oxide layer on the side wall of the groove sequentially through a furnace tube thermal oxidation process, and filling polycrystal by using low-pressure chemical vapor deposition equipment to form a polysilicon gate, wherein the polysilicon gate is shown in (f); specifically, the oxide layer growth thickness is 0.05~0.10/>。
S7, generating interlayer dielectric silicon dioxide and front metal by adopting a film deposition technology, wherein the interlayer dielectric silicon dioxide and the front metal are shown as (g);
s8, turning over the silicon wafer, thinning the substrate by adopting a thinning process, and then forming an N-type buffer layer through ion implantation and heat treatment, wherein the N-type buffer layer is shown as (h); specifically, the back surface of the thinned silicon wafer is formed into a thickness of 1.5 according to the phosphorus ion implantation and annealing treatment~3.0/>Doping concentration 2e 16->~3e16/>N-type buffer layer of (a).
S9, performing epitaxial growth, diffusion and annealing on the back of the buffer layer by adopting a back epitaxial process to form a collector electrode P region and a P type barrier region, wherein the collector electrode P region and the P type barrier region are shown as (i); specifically, a layer with the thickness of 0.5 is firstly grown on the back surface of the buffer layer~1.0/>Doping concentration 1e 14->~1e16/>The back of the formed P-type isolation region is subjected to thermal diffusion and annealing treatment at 900-1200 ℃ to form the P-type isolation region with the same thickness and doping concentration of 1.0e17%>~1.5e17/>Is formed on the substrate. The collector P region and the P type isolation region are arranged in parallel, and the width ratio is 5:1 or 4:1.
s10, forming a collector N+ region in the P-type barrier region through ion implantation and heat treatment, wherein the collector N+ region is shown as (j); specifically, a mask is manufactured on the formed P-type barrier region, phosphorus ion implantation is carried out at the middle part of the mask, and then annealing treatment is carried out, so that a collector N+ region with the thickness of 0.2-0.5 times of the thickness of the P-type barrier region and the width of 0.4-0.6 times of the width of the P-type barrier region is formed.
S11, preparing a groove structure in the center of the collector electrode N+ region through processes such as spin coating, exposure, development, dry etching and the like, wherein the groove structure is shown as (k); specifically, the trench depth is 0.5 higher than the collector P region~1.0/>。
S12, filling a groove oxide layer in the groove structure by adopting a chemical vapor deposition CVD process, wherein the groove oxide layer is shown as (l);
s13, forming a split groove structure on the filled groove by adopting steps of spin coating, exposure, development, dry etching and the like, wherein the split groove structure is shown as (m); specifically, the thickness of the right oxide layer in the split trench is 0.1~0.2/>The thickness of the left oxide layer is 0.05 +.>The thickness of the top oxide layer is 0.5 +.>~1.0/>。
S14, filling polycrystalline silicon into the split grooves by adopting a chemical vapor deposition CVD process to form induction gates, and filling aluminum metal into the split grooves by adopting a physical vapor deposition PVD process to form short-circuit collector metal gates, wherein the short-circuit collector metal gates are shown in (n); specifically, the polysilicon fill size is: the top is leveled with the top of the P-type barrier region, and the bottom is leveled with the top of the collector N+ region.
S15, depositing silicon dioxide by adopting a chemical vapor deposition CVD process, and sealing the induction gate to float the induction gate, wherein the chemical vapor deposition CVD process is shown in (o); specifically, the silicon dioxide deposition thickness is consistent with the collector n+ region thickness.
S16, forming a groove structure at the junction of the left P-type isolation region and the collector electrode P region through steps of spin coating, exposure, development, dry etching and the like, wherein the groove structure is shown as (P); specifically, the etching width is 0.6The depth is determined by the doping concentration of the P-type barrier region, and in this embodiment, the depth is 2.0 +.>~4.0/>Between them.
S17, depositing silicon dioxide in the groove through a chemical vapor deposition CVD process to form a deep oxygen groove, wherein the deep oxygen groove is shown as (q);
s18, forming collector metal by adopting a metal evaporation process, wherein the collector metal is shown as (r).
The foregoing description, in conjunction with the accompanying drawings, fully illustrates the specific embodiments of the application so as to enable those skilled in the art to practice them. Portions and features of some embodiments may be included in, or substituted for, those of others. In the present application, the terms "first," "second," and the like are used merely to distinguish one element from another element, and do not require or imply any actual relationship or order between the elements. Indeed the first element could also be termed a second element and vice versa. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a structure, apparatus, or device that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such structure, apparatus, or device. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a structure, apparatus or device comprising the element. In the application, each embodiment is described in a progressive manner, and each embodiment is mainly used for illustrating the difference from other embodiments, and the same similar parts among the embodiments are mutually referred.
The terms "longitudinal," "transverse," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," and the like herein refer to an orientation or positional relationship based on that shown in the drawings, merely for convenience of description herein and to simplify the description, and do not denote or imply that the devices or elements referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus are not to be construed as limiting the application. In the description herein, unless otherwise specified and defined, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be, for example, mechanically or electrically connected, or may be in communication with each other in two elements, directly or indirectly connected via an intermediate medium, as will be apparent to those of ordinary skill in the art, and the specific meaning of the terms described above may be understood in view of the circumstances; the terms "P-type blocking region", "collector n+ region", and "left and right P-type blocking regions", "left and right collector n+ regions", respectively, are designated by default unless otherwise specified. In the present application, the term "plurality" means two or more, unless otherwise indicated.
The above description is only for the preferred embodiments of the present application and is not intended to limit the present application, and various modifications and variations may be made by those skilled in the art, and it should be apparent that various modifications, variations, equivalents, etc. may be made without inventive faculty for those skilled in the art, and are intended to be included within the scope of the present application.
Claims (7)
1. The low-loss bidirectional conduction IGBT structure comprises an N-type drift region, wherein a polysilicon gate, a P-type base region, an emitter N+ region, an emitter P+ region and emitter metal are arranged above the N-type drift region from bottom to top, and the polysilicon gate is of a groove structure; the N-type drift region comprises an N-type buffer layer, a collector electrode P region and a collector electrode metal which are stacked up and down, and is characterized in that: a bidirectional conduction NMOS structure and a deep oxygen trench (7) are further arranged below the N-type drift region, wherein the bidirectional conduction NMOS structure comprises a short-circuit collector metal gate (1), an induction gate (2), a left collector N+ region (3), a right collector N+ region (4), a left P-type blocking region (5) and a right P-type blocking region (6); the short-circuit collector metal grid (1) is connected with the collector metal and is wrapped by an oxide layer together with the induction grid (2) to form a short-circuit collector split groove; the left P-type blocking area (5) and the right P-type blocking area (6) are distributed symmetrically left and right about the short-circuit collector splitting groove, and floating is not directly electrically connected; the left collector N+ region (3) and the right collector N+ region (4) are distributed symmetrically left and right relative to the short collector splitting groove, are respectively wrapped by the left P-type blocking region (5) and the right P-type blocking region (6), and are connected with collector metal; the deep oxygen groove (7) is positioned between the left P-type barrier region (5) and the collector electrode P region; the N-type buffer layer is positioned on the right side of the deep oxygen groove (7) and the upper sides of the left P-type blocking area (5) and the right P-type blocking area (6);
the induction grid (2) is not directly and electrically connected to be a floating grid, the top of the induction grid is leveled with the top of the left P-type isolation region (5), and the bottom of the induction grid is leveled with the top of the left collector N+ region (3); the doping concentration of the left side P-type barrier region (5) and the right side P-type barrier region (6) is lower than that of the collector electrode P region, and the doping concentration is 1e 14-1 e 16; the doping concentration of the left collector N+ region (3) and the right collector N+ region (4) is 1e 16-1 e 18; the depth of the deep oxygen groove (7) is higher than the sum of the thickness of the collector P region and the thickness of the N-type buffer layer, so that the voltage folding phenomenon is restrained.
2. The low-loss bi-directional conduction IGBT structure of claim 1 wherein: the short-circuit collector metal gate (1) and the induction gate (2) are wrapped by an oxide layer to form a short-circuit collector split trench gate, wherein the short-circuit collector metal gate (1), the right collector N+ region (4), the right P-type blocking region (6) and the N-type buffer layer (8) form a forward conduction NMOS structure; the induction gate (2), the left collector N+ region (3), the left P-type blocking region (5) and the N-type buffer layer (8) form a reverse conduction NMOS structure.
3. The low-loss bi-directional conduction IGBT structure of claim 1 wherein: the thickness range of the left collector electrode N+ region (3) is 0.2-0.5 times of the thickness of the left P-type barrier region (5); the thickness range of the right collector electrode N+ region (4) is 0.2-0.5 times of the thickness of the right P-type barrier region (6);
the width range of the left collector electrode N+ region (3) is 0.4-0.6 times of the width of the left P-type barrier region (5); the width range of the right collector electrode N+ region (4) is 0.4-0.6 times of the width of the right P-type barrier region (6).
4. The low-loss bi-directional conduction IGBT structure of claim 1 wherein: the depth of the deep oxygen trench (7) is not lower than the thickness of the collector P region so as to isolate the electrical characteristics of the left P-type barrier region (5) and the collector P region.
5. The low-loss bi-directional conduction IGBT structure of claim 1 wherein: the tops of the short-circuit collector metal grid (1) and the induction grid (2) are thick oxide layers with the thickness of 0.5-1.0 micrometers; the thickness of the oxide layer on the right side of the short-circuit collector metal gate (1) is 0.1-0.15 microns; the thickness of the oxide layer on the left side of the induction grid (2) is 0.05 microns.
6. The preparation method of the low-loss bidirectional conduction IGBT structure is characterized by comprising the following steps of:
s1, providing an assembly formed by sequentially stacking substrate substrates and drift layers from bottom to top;
s2, forming a P-type base region on the drift layer through a diffusion process and heat treatment;
s3, forming an emitter P+ region on the P-type base region through a diffusion process and heat treatment;
s4, forming an emitter N+ region on the emitter P+ region through an ion implantation process and heat treatment;
s5, preparing a groove structure in the center of the emitter N+ region through spin coating, exposure, development and dry etching processes;
s6, growing a gate oxide layer on the side wall of the groove sequentially through a furnace tube thermal oxidation process, and filling polycrystal by using low-pressure chemical vapor deposition equipment to form a polysilicon gate;
s7, generating interlayer dielectric silicon dioxide and front metal by adopting a thin film deposition technology;
s8, turning over the silicon wafer, thinning the substrate by adopting a thinning process, and forming an N-type buffer layer through ion implantation and annealing treatment;
s9, adopting a back epitaxy process, and carrying out epitaxial growth, diffusion and annealing on the back of the substrate to form a collector electrode P region and a P type isolation region;
s10, forming a collector N+ region in the P-type barrier region through ion implantation and heat treatment;
s11, preparing a groove structure in the center of the collector electrode N+ region through spin coating, exposure, development and dry etching processes; at the moment, the collector N+ region and the P-type barrier region are divided into a left collector N+ region (3), a right collector N+ region (4), a left P-type barrier region (5) and a right P-type barrier region (6);
s12, filling a groove oxide layer in the groove structure in the S11 by adopting a chemical vapor deposition CVD process;
s13, forming a split groove structure on the filled groove by adopting the steps of spin coating, exposure, development and dry etching;
s14, filling polycrystalline silicon into the split grooves by adopting a Chemical Vapor Deposition (CVD) process to form induction gates (2), and filling aluminum metal into the split grooves by adopting a Physical Vapor Deposition (PVD) process to form short-circuit collector metal gates (1);
s15, depositing silicon dioxide by adopting a chemical vapor deposition CVD process, and sealing the induction grid (2) to float;
s16, forming a groove structure at the junction of the left P-type isolation region (5) and the collector P region through the steps of spin coating, exposure, development and dry etching;
s17, depositing silicon dioxide in the groove structure in S16 through a chemical vapor deposition CVD process to form a deep oxygen groove (7);
s18, forming collector metal by adopting a metal evaporation process;
the depth of the deep oxygen groove (7) is higher than the sum of the thickness of the collector electrode P region and the thickness of the N-type buffer layer, so that the voltage folding phenomenon is restrained; the left P-type blocking area (5) and the right P-type blocking area (6) are arranged in a floating mode, the doping concentration of the left P-type blocking area (5) and the right P-type blocking area (6) is lower than that of the collector P area, and the doping concentration is 1e 14-1 e 16; the left collector N+ region (3) and the right collector N+ region (4) are connected with collector metal, and the doping concentration is 1e 16-1 e 18; the metal grid (1) is connected with the collector metal.
7. The method for manufacturing the low-loss bi-directional conduction IGBT structure of claim 6, wherein: the thickness of the right oxide layer in the split trench in the S13 is 0.1~0.2/>The thickness of the left oxide layer is 0.05 +.>The thickness of the top oxide layer is 0.5 +.>~1.0/>；
The filling size of the polysilicon in the S14 is that the top is leveled with the top of the P-type barrier region, and the bottom is leveled with the top of the collector N+ region;
the thickness of the silicon dioxide deposition in the S15 is consistent with the thickness of the collector N+ region.
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