CN117766390A - RC-IGBT with self-bias structure and manufacturing method thereof - Google Patents
RC-IGBT with self-bias structure and manufacturing method thereof Download PDFInfo
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- CN117766390A CN117766390A CN202410195298.XA CN202410195298A CN117766390A CN 117766390 A CN117766390 A CN 117766390A CN 202410195298 A CN202410195298 A CN 202410195298A CN 117766390 A CN117766390 A CN 117766390A
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- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 11
- 239000011574 phosphorus Substances 0.000 claims description 11
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 7
- 229910052796 boron Inorganic materials 0.000 claims description 7
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- 238000005224 laser annealing Methods 0.000 claims description 6
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- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 5
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Abstract
The invention discloses an RC-IGBT with a self-bias structure and a manufacturing method thereof. The method comprises the steps of manufacturing a cellular structure and a terminal structure on the upper side of a substrate; thinning the device from the lower side of the substrate, and sequentially manufacturing an N-type doped region and a P-type doped region at the lower end of the substrate; etching the lower side of the substrate to form a plurality of first auxiliary grooves and second auxiliary grooves, and manufacturing a P-buried area around the upper end of the second auxiliary grooves; forming an isolation oxide layer in the first auxiliary groove and the second auxiliary groove, and then forming an auxiliary control gate arranged in the first auxiliary groove and a self-bias gate arranged in the second auxiliary groove; depositing a dielectric layer at the lower end of the auxiliary control gate; and manufacturing collector metal on the lower side of the substrate, wherein the collector metal is connected with the self-bias gate, and the auxiliary control gate is led out through a conductor inserted on the substrate. The invention can completely eliminate the rebound phenomenon of the RC-IGBT and reduce the conduction voltage drop during reverse conduction.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to an RC-IGBT with a self-bias structure and a manufacturing method thereof.
Background
reverse conducting IGBT (RC-IGBT) is a novel IGBT integrating a freewheeling diode (FWD) and the IGBT on a chip to achieve the purposes of reducing the volume of a module, reducing parasitic capacitance and inductance and improving the anti-electromagnetic interference capability of the module.
Because the injection of the P-type collector at the back of the RC-IGBT is not common injection, negative differential resistance phenomenon appears in the positive characteristic curve of the RC-IGBT, and the negative differential resistance phenomenon is visually represented as rebound (snapback) phenomenon in the characteristic curve.
the current methods for improving rebound phenomenon are as follows:
1. The back FWD part is isolated from the IGBT part, so that carriers flowing from the FWD part to the IGBT part during forward conduction of the device are reduced, and the rebound phenomenon is restrained. Such as the patent application publication CN 108649068A. This isolation only suppresses the rebound phenomenon and does not completely eliminate the rebound. And isolating the FWD from the IGBT can create current concentration phenomena, leading to thermal failure of the module.
2. a trench gate or a plane gate is manufactured on the back of the device to achieve the purpose of accurately controlling the on and off of the FWD part, so that the rebound phenomenon is eliminated. Such as the patent application publication CN 115832038A. The auxiliary control gate is manufactured on the back surface, so that the rebound phenomenon can be completely eliminated, but the device is a unipolar device when being reversely conducted, and the reverse conduction voltage drop is far higher than the forward conduction voltage drop.
Disclosure of Invention
The invention aims to provide an RC-IGBT with a self-bias structure and a manufacturing method thereof, aiming at the defects in the prior art.
in order to achieve the above object, in a first aspect, the present invention provides a method for manufacturing an RC-IGBT with a self-bias structure, including:
Providing an N-type substrate;
forming a cell structure and a terminal structure on the upper side of the substrate;
thinning the device from the lower side of the substrate, and sequentially manufacturing an N-type doped region and a P-type doped region arranged on the lower side of the N-type doped region at the lower end of the substrate;
Etching a plurality of first auxiliary grooves and second auxiliary grooves on the lower side of the substrate, wherein the depth of the first auxiliary grooves and the second auxiliary grooves is larger than that of the N-type doped region;
Forming a P-buried area around the upper end of the second auxiliary groove;
forming isolation oxide layers in the first auxiliary groove and the second auxiliary groove, and then depositing conductive substances in the first auxiliary groove and the second auxiliary groove to form an auxiliary control gate arranged in the first auxiliary groove and a self-bias gate arranged in the second auxiliary groove;
depositing a dielectric layer at the lower end of the auxiliary control gate so as to seal the auxiliary control gate in the first auxiliary groove;
and manufacturing collector metal on the lower side of the substrate, wherein the collector metal is connected with the self-bias gate, and the auxiliary control gate is led out through a conductor inserted on the substrate.
Further, when the device is thinned, the device is thinned to a preset thickness, and then the middle part of the substrate is thinned to 90-120um by using the Taiko process.
Further, the N-type doped region is formed by implanting phosphorus element with an implantation energy of 230-450kev and an implantation dose of 1E12-4E12 atoms/cm3。
Further, the P-type doped region is formed by implanting boron element with an implantation energy of 20-40kev and an implantation dose of 3E12-1E13 atoms/cm3。
Further, the P-buried region is formed by implanting P-type element into the substrate around the upper end of the second auxiliary groove and performing laser annealing, the implantation energy is 150-400kev, and the implantation dosage is 1E12-4E12 atoms/cm3。
Further, the conductive material is polysilicon doped with phosphorus element, and the doping concentration is 1E19-6E19 atoms/cm3。
In a second aspect, the invention provides an RC-IGBT with a self-bias structure, including an N-type substrate, where a cell structure and a termination structure are disposed on the upper side of the substrate, an N-type doped region and a P-type doped region disposed on the lower side of the N-type doped region are disposed on the lower side of the substrate, a plurality of first sub-trenches and second sub-trenches are disposed on the lower side of the substrate, the depths of the first sub-trenches and the second sub-trenches are greater than those of the N-type doped region, a P-buried region is disposed around the upper end of the second sub-trenches, an isolation oxide layer is disposed in the first sub-trenches and the second sub-trenches, conductive materials are deposited in the first sub-trenches and the second sub-trenches inside the isolation oxide layer to form a sub-control gate disposed in the first sub-trenches, a lower dielectric layer is disposed on the lower end of the sub-control gate, the sub-control gate is sealed in the first sub-trenches, a metal is disposed on the lower side of the substrate, and the metal is connected to the sub-control gate via the collector conductor.
Further, the N-type doped region is formed by implanting phosphorus element with an implantation energy of 230-450kev and an implantation dose of 1E12-4E12 atoms/cm3。
Further, the P-type doped region is formed by implanting boron element with an implantation energy of 20-40kev and an implantation dose of 3E12-1E13 atoms/cm3。
Further, the P-buried region is formed by implanting P-type element into the substrate around the upper end of the second auxiliary groove and performing laser annealing, the implantation energy is 150-400kev, and the implantation dosage is 1E12-4E12 atoms/cm3。
The beneficial effects are that: 1. the invention can completely eliminate the rebound phenomenon of RC-IGBT;
2. The invention reduces the conduction voltage drop during reverse conduction through the electric conduction modulation effect;
3. The invention can achieve the effects of eliminating stress and reducing wafer warpage by adjusting the directions of the first auxiliary groove and the second auxiliary groove to be vertical to the main groove.
Drawings
FIG. 1 is a schematic structural view of a substrate;
FIG. 2 is a schematic diagram of the structure after etching a main trench in a substrate;
FIG. 3 is a schematic diagram of the structure after a gate oxide layer is formed in the main trench;
FIG. 4 is a schematic diagram of the structure after the main control gate is fabricated in the main trench;
Fig. 5 is a schematic structural diagram after body and source regions are fabricated on the upper side of the substrate;
FIG. 6 is a schematic diagram of the structure after etching the connection holes;
FIG. 7 is a schematic diagram of the structure after fabrication of an emitter metal;
FIG. 8 is a schematic diagram of the structure of the substrate after the N-type doped region and the P-type doped region are formed on the underside of the substrate;
FIG. 9 is a schematic diagram of the structure after etching a first sub-trench and a second sub-trench in the underside of the substrate;
FIG. 10 is a schematic diagram of the structure after P-buried regions are fabricated on the substrate;
FIG. 11 is a schematic diagram of a structure after forming isolation oxide layers in the first and second sub-trenches;
Fig. 12 is a schematic structural view of the collector metal formed on the underside of the substrate;
Fig. 13 is an equivalent circuit diagram of an RC-IGBT with a self-biasing structure.
Detailed Description
The invention will be further illustrated by the following drawings and specific examples, which are carried out on the basis of the technical solutions of the invention, it being understood that these examples are only intended to illustrate the invention and are not intended to limit the scope of the invention.
The embodiment of the invention provides a manufacturing method of an RC-IGBT with a self-biasing structure, which comprises the following steps:
referring to fig. 1, an N-type substrate 1 (N-drift (Sub)) is provided. The substrate 1 is generally manufactured by FZ zone melting method, and proper resistivity is selected according to rated voltage of the designed device.
A cell structure and a terminal structure are formed on the upper side of the substrate 1. The manufacturing process of the cell structure and the terminal structure is specifically as follows:
Firstly, pre-growing a layer of oxide layer 300A-800A on a substrate 1 as a stop layer for terminal pressure-resistant ring injection, then opening a region to be injected for ion injection through a photoetching process, and finally pushing the pressure-resistant ring to the designed depth and width through a furnace tube. The ion implantation energy is 100-150KeV, and the implantation dosage is 3E13-5E14 atoms/cm3the implanted element is preferably boron (B), and the annealing condition is 1150 ℃/500-100min.
The field oxide layer is fabricated on the upper side of the substrate 1, and two processes are currently available for fabricating the field oxide layer, namely a FOX process, wherein a field oxide layer with the thickness of about 15000 angstrom is firstly grown through a furnace tube wet method, and then photoetching and dry etching are carried out. Also known is the LOCOS process, in which a layer of silicon nitride (Si3N4) Then the region needing to grow the oxide layer is opened through a photoetching process, a field oxide layer with about 15000 angstrom is grown through a furnace tube wet method, and then the silicon nitride is removed. The structure formed in the above two steps is in the termination region and is not shown here.
referring to fig. 2, a main trench 2 is etched in an upper side of a substrate 1. Specifically, a layer of SiO is deposited on the front surface of the substrate 12The hard mask layer is made, the thickness of the mask layer is about 3000 angstroms, and the thickness of the mask layer can be adjusted according to the depth of the groove. Then the structure of the main groove 2 is formed by two processes of photoetching and etching, the depth of the main groove 2 is 4-6um, and the width of the main groove 2 is 0.6-1.1 um. The sidewall of the main trench 2 is inclined at 89.5 deg. for subsequent filling of the polysilicon.
referring to fig. 3, a gate oxide layer 3 is grown in the main trench 2. The gate oxide layer 3 can be grown by furnace tube dry oxidation, the thickness is 800-2000 angstrom, and the oxidation temperature is 1000-1150 ℃. Before the gate oxide layer 3 is grown, a layer of 500-1500 angstrom sacrificial oxide layer can be grown by dry oxidation of a furnace tube, the growth temperature is 1000-1150 ℃, and then all the sacrificial oxide layers are removed by a wet etching process, so that damages generated when the main groove 2 is etched are removed.
Referring to fig. 4, a main control gate 4 is formed in the main trench 2. Specifically, a layer of polysilicon is deposited on the upper side of the substrate 1, and then the main control gate 4 can be formed by photoetching and etching processes, wherein the doping concentration of the deposited polysilicon is 1E19-6E19 atoms/cm3the doping element is preferably phosphorus (P), and the thickness of the deposited layer is more than 8000 angstroms.
referring to fig. 5, a body region 5 (Pwell) and a source region 6 (n+) are formed on the upper side of the substrate 1. Specifically, element B is injected on the upper side of the substrate 1, the injection energy is between 60 and 150Kev, and the injection dosage is between 5E12 and 5E13 atoms/cm3And the Vth parameter requirement and the PN junction depth requirement. The body region 5 is formed by high temperature annealing, typically at a temperature of 1100 c or higher, for a period of between 50 and 100 minutes. The source region 6 is formed by three steps of lithography, implantation and advancement, and the implantation element may be P or As, or the two elements may be implanted in two times. The energy of implantation was around 60kev and the annealing conditions were 950 ℃/60min.
Referring to fig. 6, an upper dielectric layer 7 with a thickness of 8000-12000 angstrom is deposited on the upper side of the substrate 1, and a certain proportion of B element and P element can be doped in the upper dielectric layer 7 to absorb movable Na and K ions, thereby improving the reliability of the device. Then, the connecting hole 8 is formed by photolithography and etching, and the depth of the connecting hole 8 is generally 0.3-0.6um. B/BF2 can also be injected into the contact hole to reduce contact resistance, and the injection dosage is 2E14-5E14 atoms/cm3the implantation energy is 30-40KeV, rapid Thermal Annealing (RTA) is used for activating impurity ions to repair implantation damage, and the annealing condition is 950 ℃/30s; then depositing a Ti/TiN layer to form an ohmic contact; finally, depositing tungsten metal.
Referring to fig. 7, a metal layer is deposited on the upper side of the upper dielectric layer 7 and in the connection hole 8, and then an Emitter metal 9 (Emitter) connected to the body region 5 and the source region 6 and a main gate metal (not shown) connected to the main gate 4 are etched. The metal layer is preferably an AL/Si/Cu alloy layer, and the thickness thereof is preferably about 4 um. Through the above process steps, a cell structure and a terminal structure can be formed on the upper side of the substrate 1.
In addition, 7000-12000 angstrom silicon nitride passivation layers can be deposited on the upper side of the emitter metal, or an SRO layer can be deposited under the silicon nitride. And then, using photoetching and etching processes to leave openings in the areas needing to be wire-bonded during packaging.
A layer of polyimide with about 4um can be deposited on the upper side of the passivation layer, an opening is reserved in a region which needs to be wire-bonded during packaging by using photoetching and etching processes, and then the polyimide is baked to be solidified.
Referring to fig. 8, the device is thinned from the lower side of the substrate 1, and an N-type doped region 10 (N-buffer) and a P-type doped region 11 (p+collector) disposed on the lower side of the N-type doped region 10 are sequentially formed at the lower end of the substrate 1. Specifically, when the device is thinned, the device can be thinned to a preset thickness (about 150 um), and then the middle part of the substrate is thinned to 90-120um by using the Taiko process. The N-type doped region 10 is preferably formed by implanting phosphorus element at an energy of 230-450kev at a dose of 1E12-4E12 atoms/cm3. The P-type doped region 11 is preferably formed by implanting boron with an energy of 20-40kev at a dose of 3E12-1E13 atoms/cm3。
Referring to fig. 9, a plurality of first and second sub-trenches 12 and 13 are etched at the lower side of the substrate 1, and the depths of the first and second sub-trenches 12 and 13 are greater than the depth of the N-type doped region 10. The positions of the first sub-grooves 12 and the second sub-grooves 13 are not limited to those shown in the drawings, but are preferably alternately formed so as to avoid current concentration.
referring to fig. 10, a P-buried region 14 is formed around the upper end of the second sub-trench 13. The P-buried region 14 is preferably formed by implanting a P-type element, preferably B, into the substrate 1 around the upper end of the second sub-trench 13 at a dose of 1E12-4E12 atoms/cm at an implantation energy of 150-400kev, and laser annealing3。
Referring to fig. 11, an isolation oxide layer 15 is formed in the first sub-trench 12 and the second sub-trench 13. Before the isolation oxide layer 15 is manufactured, a sacrificial oxide layer of about 500 angstroms may be deposited, and then the back oxide layer is etched by wet etching to remove the damage generated when the first sub-trench 12 and the second sub-trench 13 are etched.
Referring to fig. 12, conductive material is then deposited in the first sub-trench 12 and the second sub-trench 13 to form a sub-control gate 16 disposed in the first sub-trench 12 and a self-bias gate 17 disposed in the second sub-trench 13. The conductive material can be polysilicon doped with phosphorus element, and the doping concentration is 1E19-6E19 atoms/cm3. Metal filling may also be used directly.
A lower dielectric layer 18 is deposited at the lower end of the auxiliary control gate 16, and the lower dielectric layer 18 may enclose the auxiliary control gate 16 within the first auxiliary trench 12.
A Collector metal 19 is formed on the underside of the substrate 1, the Collector metal 19 being connected to the self-bias gate 17, and the sub-control gate 16 being led out through a conductor (not shown) interposed on the substrate 1. The metal column is arranged on the substrate 1 to be led out, and the collector metal 19 is provided with a corresponding avoiding port; the gate metal may also be etched simultaneously with the fabrication of the collector metal 19, which has previously been connected to the sub-control gate 16 by etching a connection hole in the lower dielectric layer 18.
Referring to fig. 1 to 13, based on the above embodiments, it can be easily understood by those skilled in the art that the present invention further provides an RC-IGBT with a self-bias structure, which includes an N-type substrate 1, and the substrate 1 is generally manufactured by FZ zone melting method, and the appropriate resistivity is selected according to the rated voltage of the design device.
A cell structure and a terminal structure are disposed on the upper side of the substrate 1, and specific structures and fabrication processes of the cell structure and the terminal structure can be referred to in fig. 1 to 7 and descriptions in the above fabrication methods, which are not repeated. An N-type doped region 10 and a P-type doped region 11 are arranged on the lower side of the substrate 1, wherein the N-type doped region 10 is preferably formed by injecting phosphorus element with the energy of 230-450kev and the injection dosage of 1E12-4E12 atoms/cm3. The P-type doped region 11 is preferably formed by implanting boron with an energy of 20-40kev at a dose of 3E12-1E13 atoms/cm3。
A plurality of first sub-trenches 12 and second sub-trenches 13 are provided on the underside of the substrate 1, the first sub-trenches 12 and second sub-trenches 13 having a depth greater than the depth of the N-type doped region 10. The positions of the first sub-grooves 12 and the second sub-grooves 13 are not limited to those shown in the drawings, but are preferably alternately formed so as to avoid current concentration.
A P-buried region 14 is arranged around the upper end of the second auxiliary groove 13. The P-buried region 14 is preferably formed by implanting a P-type element, preferably B, into the substrate 1 around the upper end of the second sub-trench 13 at a dose of 1E12-4E12 atoms/cm at an implantation energy of 150-400kev, and laser annealing3。
An isolation oxide layer 15 is arranged in the first auxiliary groove 12 and the second auxiliary groove 13, conductive substances are deposited in the first auxiliary groove 12 and the second auxiliary groove 13 inside the isolation oxide layer 15 to form an auxiliary control gate 16 arranged in the first auxiliary groove 12 and a self-bias gate 17 arranged in the second auxiliary groove 13, the conductive substances can be polysilicon doped with phosphorus element, and the doping concentration is 1E19-6E19 atoms/cm3. Metal filling may also be used directly.
a lower dielectric layer 18 is arranged at the lower end of the auxiliary control gate 16, the auxiliary control gate 16 is enclosed in the first auxiliary groove 12 by the lower dielectric layer 18, a collector metal 19 is arranged at the lower side of the substrate 1, the collector metal 19 is connected with the self-bias gate 17, and the auxiliary control gate 16 is led out through a conductor (not shown in the figure) inserted on the substrate 1. The metal column is arranged on the substrate 1 to be led out, and the collector metal 19 is provided with a corresponding avoiding port; the gate metal may also be etched simultaneously with the fabrication of the collector metal 19, which has previously been connected to the sub-control gate 16 by etching a connection hole in the lower dielectric layer 18.
According to the invention, the first auxiliary groove 12 and the second auxiliary groove 13 are added on the basis of a common IGBT, the N-type doped region 10 is etched through at the bottoms of the first auxiliary groove 12 and the second auxiliary groove 13, the P-buried region 14 is not arranged at the bottom of the first auxiliary groove 12, and after the first groove 12 is filled with a conductive substance, a lower dielectric layer 18 is deposited to be isolated from the collector metal 19 below to serve as an auxiliary control gate 16; the bottom of the second sub-trench 13 has a P-buried region 14, and after filling the second trench 13 with a conductive material, a lower dielectric layer 18 is not deposited, so that the conductive material in the second trench 13 is shorted to the collector metal 19 on the back side. The side walls of the first auxiliary groove 12 and the second auxiliary groove 13 are provided with an isolation oxide layer 15 to achieve the isolation effect. Referring to fig. 12, the self-biased PMOS is identified by a dashed box, and the P-doped region 14, the N-doped region 10, the P-doped region 11, and the self-biased gate 17 in the second sub-trench 13 respectively form the source, the substrate, the drain, and the gate of the self-biased PMOS, and an equivalent circuit of the formed device is shown in fig. 13. The collector metal 19 is connected with positive potential during forward conduction, the self-biased PMOS is turned off, the main control gate 4 is connected with positive potential, the auxiliary control gate 16 is connected with zero potential, and the device is consistent with that of a common IGBT during forward conduction, and no rebound phenomenon exists because the process of converting a MOSFET conduction mode into an IGBT conduction mode does not exist during forward conduction of the device. When in reverse conduction, the emitter metal 9 is connected with positive potential, the main control gate 4 is connected with zero potential, and the auxiliary control gate 16 is connected with positive potential. The NMOS controlled by the secondary control gate 16 turns on and the device turns on in the opposite direction, electrons are injected from the collector metal 19 into the substrate 1, the PMOS consisting of the body region 5, the substrate 1 and the P-buried region 14 turns on, and the potential of the N-doped region in the self-biased PMOS starts to rise, which is zero potential because the gate of the self-biased PMOS is shorted to the collector metal 19. When the absolute value of the potential difference between the N-type doped region 10 and the grid electrode of the self-bias PMOS is larger than the threshold voltage of the self-bias PMOS, the self-bias PMOS tube is started to provide a flow path for holes, and the flow path of the holes is that the body region 5 is → the substrate 1 is → the P-doped region 14 is → the N-type doped region 10 is → the P-type doped region 11. After the self-bias PMOS is turned on, the FWD (freewheeling diode) integrated inside the RC-IGBT becomes a bipolar device, and the resistance of the substrate 1 becomes very small due to the conductance modulation effect, and the reverse conduction voltage drop of the device is also greatly reduced.
The foregoing is merely a preferred embodiment of the present invention, and it should be noted that other parts not specifically described are within the prior art or common general knowledge to a person of ordinary skill in the art. Modifications and alterations may be made without departing from the principles of this invention, and such modifications and alterations should also be considered as being within the scope of the invention.
Claims (10)
1. The manufacturing method of the RC-IGBT with the self-bias structure is characterized by comprising the following steps of:
Providing an N-type substrate;
forming a cell structure and a terminal structure on the upper side of the substrate;
thinning the device from the lower side of the substrate, and sequentially manufacturing an N-type doped region and a P-type doped region arranged on the lower side of the N-type doped region at the lower end of the substrate;
Etching a plurality of first auxiliary grooves and second auxiliary grooves on the lower side of the substrate, wherein the depth of the first auxiliary grooves and the second auxiliary grooves is larger than that of the N-type doped region;
Forming a P-buried area around the upper end of the second auxiliary groove;
forming isolation oxide layers in the first auxiliary groove and the second auxiliary groove, and then depositing conductive substances in the first auxiliary groove and the second auxiliary groove to form an auxiliary control gate arranged in the first auxiliary groove and a self-bias gate arranged in the second auxiliary groove;
depositing a dielectric layer at the lower end of the auxiliary control gate so as to seal the auxiliary control gate in the first auxiliary groove;
and manufacturing collector metal on the lower side of the substrate, wherein the collector metal is connected with the self-bias gate, and the auxiliary control gate is led out through a conductor inserted on the substrate.
2. The method for manufacturing the RC-IGBT with the self-bias structure according to claim 1, wherein when the device is thinned, the device is thinned to a preset thickness, and then the middle part of the substrate is thinned to 90-120um by using a Taiko process.
3. The method of claim 1, wherein the N-doped region is formed by implanting phosphorus element with an energy of 230-450kev, and a dose of 1E12-4E12 atoms/cm3。
4. The method of claim 1, wherein the P-type doped region is formed by implanting boron with an energy of 20-40kev at a dose of 3E12-1E13 atoms/cm3。
5. The method of claim 1 wherein the P-series region is formed by implanting P-type elements into the substrate around the upper end of the second sub-trench and laser annealing at an implantation energy of 150-400kev, and an implantation dose of 1E12-4E12 atoms/cm3。
6. The method of claim 1, wherein the conductive material is polysilicon doped with phosphorus element, and the doping concentration is 1E19-6E19 atoms/cm3。
7. The RC-IGBT with the self-bias structure is characterized by comprising an N-type substrate, wherein a cellular structure and a terminal structure are arranged on the upper side of the substrate, an N-type doping region and a P-type doping region are arranged on the lower side of the N-type doping region, a plurality of first sub-grooves and second sub-grooves are arranged on the lower side of the substrate, the depth of the first sub-grooves and the depth of the second sub-grooves are larger than that of the N-type doping region, P-buried regions are arranged on the periphery of the upper end of the second sub-grooves, an isolation oxide layer is arranged in the first sub-grooves and the second sub-grooves, conductive substances are deposited in the first sub-grooves and the second sub-grooves on the inner side of the isolation oxide layer so as to form a sub-control gate arranged in the first sub-groove and a self-bias gate arranged in the second sub-groove, a lower medium layer is arranged on the lower end of the sub-control gate, the sub-control gate is sealed in the first sub-groove, a metal is arranged on the lower side of the substrate, the metal is connected with the self-bias gate, and a collector conductor is led out from the substrate through the plug-in the gate.
8. The RC-IGBT with self-biasing structure as claimed in claim 7, wherein the N-doped region is formed by implanting phosphorus element with an energy of 230-450kev, the implant dose being 1E12-4E12 atoms/cm3。
9. The RC-IGBT with self-biasing structure as claimed in claim 7, wherein the P-type doped region is formed by implanting boron element with an energy of 20-40kev at a dose of 3E12-1E13 atoms/cm3。
10. The RC-IGBT with self-biasing structure of claim 7, wherein said P-series region is formed by implanting P-type element into the substrate around the upper end of the second sub-trench and laser annealing at an implantation energy of 150-400kev at a dose of 1E12-4E12 atoms/cm3。
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