WO2023093132A1 - Iegt structure and method for manufacturing same - Google Patents

Iegt structure and method for manufacturing same Download PDF

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WO2023093132A1
WO2023093132A1 PCT/CN2022/111787 CN2022111787W WO2023093132A1 WO 2023093132 A1 WO2023093132 A1 WO 2023093132A1 CN 2022111787 W CN2022111787 W CN 2022111787W WO 2023093132 A1 WO2023093132 A1 WO 2023093132A1
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trench
emitter
gate
forming
layer
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PCT/CN2022/111787
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French (fr)
Chinese (zh)
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李巍
芮强
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无锡华润华晶微电子有限公司
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395—Vertical transistors, e.g. vertical IGBT
    • H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
    • H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0804—Emitter regions of bipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates
    • H01L29/407—Recessed field plates, e.g. trench field plates, buried field plates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
    • H01L29/66333—Vertical insulated gate bipolar transistors
    • H01L29/66348—Vertical insulated gate bipolar transistors with a recessed gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate

Definitions

  • the invention relates to the technical field of power semiconductor devices, in particular to an IEGT structure and a manufacturing method thereof.
  • IGBT Insulated Gate Bipolar Transistor
  • IGBT Insulated Gate Bipolar Transistor
  • MOS Metal-Oxide-Semiconductor Field-Effect Transistor, Metal-Oxide Semiconductor Field Effect Transistor
  • BJT Bipolar Junction Transistor, bipolar Junction transistor
  • IEGT electron injection enhanced gate transistor
  • the trench gate generally has a larger etching depth and a larger contact area with the collector, which will inevitably lead to the problem of increased Miller capacitance. A large value will cause an increase in the switching loss of the IGBT device.
  • FIG. 1 is a schematic diagram of a conventional trench gate IGBT structure.
  • the existing N-type IGBT structure includes a substrate (N+ type) 10, on which a drift layer (N-type epitaxial layer, also referred to as an N-drift layer) 11 is provided,
  • the epitaxial layer 11 is provided with a base region (for P type, also called body region) 12, and on both sides of base region 12 is provided with emitter region (for N+ type, also called source region) 14, in base region 12
  • a gate trench is provided, a gate oxide layer is formed on the inner surface of the gate trench and filled with a gate 13, and a metal emitter 15 is provided on the front surface of the substrate 10, which is connected to the emitter via an emitter contact plug 16.
  • the region 14 is electrically connected, and a collector region (P+ type) 17 is provided on the back of the substrate 10, and a metal collector electrode in ohmic contact with the collector region 17 may be formed on the bottom surface.
  • the industry has proposed an electron injection enhanced gate transistor (Injection Enhanced Gate Transistor, IEGT), the specific structure is shown in Figure 2, compared with the traditional trench gate IGBT in Figure 1, in In a cell, only one side of the trench has an N+ active region, so only one side of the trench can pass electrons, and in the N- region on the other side of the trench, there is no emitter to extract holes, so The N-type region on this side can store holes, and the increased holes and electrons in the drift layer further have a conductance modulation effect, achieving the purpose of reducing the IGBT turn-on voltage drop.
  • IEGT electron injection enhanced gate transistor
  • the trench gate generally has a large downward etching depth and a large contact area with the collector, which will lead to increased Miller capacitance.
  • the problem is that the increase of Miller capacitance will cause the increase of switching loss of IGBT device.
  • the object of the present invention is to provide an IEGT structure and a manufacturing method thereof, so as to solve the problem that the IEGT device has a large Miller capacitance, which causes an increase in switching loss.
  • the gate and at least one first emitter are formed in the first trench, and a left and right separation structure is formed between the first emitter and the gate through a first isolation layer;
  • the second emitter is formed on the body region and is electrically connected with the body region and the active region.
  • the vertical length of the gate is greater than the junction depth of the body region.
  • At least one first emitter is formed in each of the first trenches, and is half-surrounded on one side and the bottom of the gate.
  • the first emitter when it is a whole, it is L-shaped and surrounds one side and the bottom of the gate; when there are multiple first emitters, several first emitters are evenly distributed on the One side and the bottom of the grid are semi-surrounded.
  • the drift layer is a drift layer of the first conductivity type, and the bottom surface of the first trench is higher than the bottom surface of the drift layer.
  • the IEGT structure further includes a gate oxide layer formed in the first trench, and the gate oxide layer covers sidewalls and bottom surfaces of the first trench.
  • the IEGT structure further includes a second isolation layer formed on the substrate.
  • the IEGT structure further includes a collector of the second conductivity type, and the collector of the second conductivity type is formed on the bottom surface of the substrate.
  • the present invention provides a method for fabricating an IEGT structure, including:
  • a gate and at least one first emitter are formed in the first trench, and the first emitter and the gate form a left and right separation structure through a first isolation layer;
  • a second emitter is formed on the body region, the second emitter being connected to the body region and the active region.
  • forming the gate and at least one first emitter in the first trench includes:
  • a second polysilicon layer is formed, the second polysilicon layer covers and fills up the second trench to form a gate.
  • a gate oxide layer is formed in the trench, and the gate oxide layer covers sidewalls and bottom surfaces of the first trench.
  • forming the gate and at least one first emitter in the first trench includes:
  • Etching the second polysilicon layer to form a gate and another part of the first emitter Etching the second polysilicon layer to form a gate and another part of the first emitter.
  • forming the gate and at least one first emitter in the first trench includes:
  • the gate oxide layer fills at least one third of the height of the first trench
  • the shape of the first emitter is an inverted triangle.
  • forming the gate and at least one first emitter in the first trench includes:
  • a second gate oxide layer is formed, and the second gate oxide layer covers the gate and the first emitter .
  • etching the second isolation layer and the active region to form a contact hole before forming the second emitter, etching the second isolation layer and the active region to form a contact hole.
  • FIG. 1 is a schematic diagram of a trench gate IGBT structure in the prior art
  • Fig. 2 is a schematic diagram of an IEGT structure in the prior art
  • Fig. 3 is a flow chart of a fabrication method of an IEGT structure according to an embodiment of the present invention.
  • 4 to 13 are structural schematic diagrams corresponding to the fabrication method of the IEGT structure according to the embodiment of the present invention.
  • FIG. 14 is a schematic diagram of another IEGT structure according to an embodiment of the present invention.
  • FIG. 15 is a schematic diagram of another IEGT structure according to an embodiment of the present invention.
  • Fig. 16 is a schematic diagram of another IEGT structure according to an embodiment of the present invention.
  • first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.
  • Spatial terms such as “under”, “beneath”, “underneath”, “over”, “above”, “above”, etc., may be used herein for convenience of description The relationship of one element or feature to other elements or features shown in the figures is thus described. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as “beneath,” “beneath,” or “beneath” would then be oriented “above” the other elements or features.
  • the device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.
  • the terminology used herein is for the purpose of describing particular embodiments only and not as limitations of the present invention.
  • the singular forms "a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly dictates otherwise.
  • the term “comprising” is used to determine the presence of certain features, steps, operations, elements and/or components, but does not exclude the presence or presence of one or more other features, steps, operations, elements, components and/or groups. Add to.
  • the term “and/or” includes any and all combinations of the associated listed items.
  • the large Miller capacitance of IEGT will cause increased switching loss.
  • the structure shown in Figure 2 is usually selected.
  • the thickness of the gate oxide layer is thickened to reduce the Miller capacitance.
  • increasing the thickness of the gate oxide can reduce the Miller capacitance, it will cause the rise of the threshold voltage of the device and the rise of the turn-on loss.
  • Another method is to make the groove smaller, and further reduce the Miller capacitance as a whole.
  • the method of making the trench smaller and reducing the total area will bring challenges to the manufacturing process.
  • the trench width is already relatively small, and further reducing the trench width will cause an increase in the abnormal rate when backfilling polysilicon (Poly), thus affecting product quality. yield.
  • a shielded gate power MOS device includes a main structure and its variable structure, and its trench is divided into upper and lower poles.
  • the groove is not connected to the electrode, and is arranged in a floating position, which can also reduce the contact area between the gate (Gate) and the collector, thereby achieving the effect of reducing the Maitreya capacitance.
  • the upper part of this variable structure is divided into left and right electrodes, because in the application of MOS devices, both of them must be connected to the gate, and there is no way to connect other electrodes, otherwise the main function of the MOS device will be affected.
  • the lower electrode is generally floating or connected to the emitter, and the upper electrode is the gate, which divides the upper gate into two small gates.
  • the contact area with the collector can achieve the purpose of reducing the Miller capacitance, but the area of the gate is still relatively large, which cannot further reduce the Miller capacitance.
  • the present invention provides an IEGT structure and its fabrication method.
  • the gate and collector in the first trench are reduced.
  • the small contact area makes the Miller capacitance of the IEGT structure greatly reduced.
  • At least one first emitter in the first trench is connected to the second emitter.
  • the first emitter can be used as a field plate without affecting the IEGT.
  • the turn-on and turn-off characteristics can accelerate the depletion of the area between the trenches and improve the withstand voltage reliability of the product.
  • FIG. 13 is a schematic diagram of another IEGT structure according to an embodiment of the present invention.
  • the IEGT structure provided in this embodiment includes a substrate 101, a drift layer 102, a first trench 103, and a first emitter. 105 a , gate 106 , body region 107 , active region 108 and second emitter 111 .
  • a drift layer 102 is formed on the substrate 101 .
  • the first trench 103 is formed in the drift layer 102 .
  • the gate 106 and at least one first emitter 105a are formed in the first trench 103, the first emitter 105a is isolated from the gate 106 by a first isolation layer 104a, and the first emitter
  • the electrode 105 a and the gate 106 are in a left and right separation structure in the first trench 103 .
  • the body region 107 is formed in the drift layer 102 on both sides of the first trench 103 .
  • An active region 108 is formed in the body region 107 on one side of the first trench 103 , and the active region is located in the body region 107 on a side close to the gate 105 a.
  • the second emitter 111 is formed on the body region 107 and electrically connected to the body region 107 and the active region 108 .
  • the drift layer 102 of the first conductivity type is stacked on the substrate 101 of the first conductivity type, the first trench 103 is formed in the drift layer 102 of the first conductivity type, and the first trench 103 The bottom surface is higher than the bottom surface of the drift layer 102 .
  • the substrate 101 is an N+ substrate
  • the drift layer 102 of the first conductivity type is an N-drift layer
  • N - The drift layer may be an N- epitaxial layer formed on an N+ substrate by an epitaxial growth process, or an ion implantation layer formed by an ion implantation process or the like.
  • the material of the N+ substrate can be any suitable substrate material, such as silicon, germanium, silicon-on-insulator, silicon germanium or gallium arsenide.
  • the body region 107 is a P-type body region, and the P-type body region is formed on the upper part of the N-drift layer.
  • An N+ active region is formed in one side of the P-type body region.
  • the N+ active region is located in the body region 107 on a side close to the gate 106 .
  • the body region 107 is a P-type body region
  • the drift layer 102 is an N-type drift layer
  • the body region 107 and the drift layer 102 form a PN junction.
  • the vertical length of the gate 106 is greater than the junction depth of the PN junction of the body region to ensure the opening and closing of the channel. Under the condition of ensuring the opening and closing of the channel, the contact between the gate 106 and the collector The smaller the area, the better.
  • the shape of the first emitter 105a can be set according to the actual situation, and there can be one or more. At least one first emitter 105a is formed in each of the first trenches, and is half-surrounded on one side and the bottom of the gate 106.
  • the first emitter 105a when the first emitter 105a is integrated, Surrounding one side and the bottom of the gate 106 in an L shape; when there are multiple first emitters 105a, several first emitters 105a are evenly distributed on one side and the bottom of the gate 106, It is semi-enclosed.
  • the N-type drift layer and the P-type body region form a PN junction, and the vertical length of the gate is greater than the junction depth of the PN junction.
  • a first emitter 105 a is formed in each of the first trenches 103 .
  • the longitudinal cross-sectional shape of the first emitter 105 a is L-shaped.
  • the IEGT structure further includes a gate oxide layer 104 formed in the first trench 103 , and the gate oxide layer 104 covers sidewalls and bottom surfaces of the first trench 103 .
  • the IEGT structure further includes a second isolation layer 109, the second isolation layer 109 is formed on the first trench 103, specifically, the second isolation layer 109 covers the body region 107, the active region 108 and The first isolation layer 104a.
  • the IEGT structure further includes a collector electrode 112 of a second conductivity type formed on the bottom surface of the substrate 101 .
  • the collector of the second conductivity type is a P-type collector, and the P-type collector is formed on the back side of the N+ substrate, and can be formed by an ion implantation process or an epitaxial growth process.
  • FIG. 3 is a flowchart of a method for fabricating an IEGT structure according to an embodiment of the present invention. As shown in Figure 3, a fabrication method of an IEGT structure includes,
  • Step S10 providing a substrate on which a drift layer is formed
  • Step S20 forming a first trench in the drift layer
  • Step S30 forming a gate and at least one first emitter in the first trench, the first emitter and the gate forming a left and right separation structure through a first isolation layer;
  • Step S40 forming body regions in the drift layer on both sides of the first trench
  • Step S50 forming an active region on the body region on the side of the first trench close to the gate
  • Step S60 forming a second emitter on the body region, the second emitter being connected to the body region and the active region.
  • FIGS. 4 to 13 are structural diagrams corresponding to the fabrication method of the IEGT structure according to the embodiment of the present invention; the semiconductor structure fabrication method provided by the embodiment of the present invention will be described in detail below in conjunction with FIGS. 4 to 13 .
  • a substrate 101 is provided, and a drift layer 102 is formed on the substrate 101 .
  • the substrate 101 is, for example, a heavily doped N-type (N+) substrate, and the drift layer 102 is, for example, an N-type (N ⁇ ) drift layer.
  • the drift layer 102 is etched to form a first trench 103 .
  • a patterned photoresist is formed on the drift layer 102, and the patterned photoresist is used as a mask to etch the drift layer 102, etch The process is, for example, a dry etching process.
  • a first polysilicon layer 105 is formed in the first trench 103 .
  • the first polysilicon layer 105 is deposited by a chemical vapor deposition process.
  • the top of the polysilicon may be planarized by a chemical mechanical polishing process, so as to remove excess polysilicon around the first trench 103 .
  • a first gate oxide layer may be formed in the first trench 103 , and the first polysilicon layer 105 covers the first gate oxide layer.
  • the process for forming the first gate oxide layer is, for example, a suitable process such as a thermal oxidation process or a deposition process.
  • a partial depth of the first polysilicon layer 105 is etched to form a second trench 103 a and a first emitter 105 a at the same time.
  • Etching part of the first polysilicon layer 105 is, for example, a dry etching process.
  • a patterned photoresist is formed on the first polysilicon layer 105, and the patterned photoresist exposes part of the first polysilicon layer.
  • each first trench 103 includes only one first emitter, and the first emitter 105a is L-shaped.
  • a first isolation layer 104a is formed in the second trench 103a. Used to isolate the gate 106 and the first emitter 105a. Then, a second polysilicon layer is deposited, and the second polysilicon layer covers and fills up the second trench 103 a to form the gate 106 .
  • the second polysilicon layer can be deposited by a chemical vapor deposition process. After forming the first emitter 105a and the gate 106 in the first trench 103a, a second gate oxide layer is deposited, and the second gate oxide covers the gate 106 and the first emitter 105a .
  • the first gate oxide layer and the second gate oxide layer formed in two processes together constitute the gate oxide layer 104 .
  • a P-type impurity is selectively implanted on the surface of the drift layer 102 and pushed to form a body region 107 .
  • the body region 107 is a P-type body region, and the body region 107 is located on both sides of the first trench 103 .
  • the process of implanting P-type impurities is, for example, a self-aligned implant process.
  • an active region 108 is formed in the body region 107 on one side of the first trench 103 .
  • the active region 108 is, for example, an N+ active region. That is, the active region 108 is formed in the body region 107 on one side of the first trench 103 , and no active region is formed in the body region 107 on the other side of the first trench 103 .
  • a second isolation layer 109 is formed, and the second isolation layer 109 covers the active region 108 , the first trench 103 and the body region 107 .
  • the process for forming the second isolation layer 109 is, for example, a chemical vapor deposition process.
  • the second isolation layer 109 and the active region 108 are etched to form a contact hole 110 .
  • the contact hole 110 penetrates through the second isolation layer 109 and the active region 108 , and extends to the surface of the body region 107 .
  • a second emitter 111 is formed, and the second emitter 111 is electrically connected to the body region 107 and the active region 108 .
  • the first emitter 105a is electrically connected to the second emitter, and the first emitter 105a can function as a field plate, which can further improve the reliability of the withstand voltage characteristic of the product.
  • One side of the body region 107 is electrically connected to the second emitter 111, and the other side of the body region 107 is isolated from the second emitter 111, because there is no emitter to extract holes, so the holes can be in P
  • the increased hole concentration can further produce conductance modulation effect to reduce the conduction voltage drop.
  • P-type impurities are implanted on the side of the substrate 101 away from the drift layer 102 (the back side of the substrate 101) to form a collector electrode 112, and the collector electrode 112 is a P-type collector electrode, that is, P+ area.
  • metal is deposited on the collector 112 to form a collector metal 113 for leading out the collector, and the metal is, for example, aluminum.
  • the initial Miller capacitance of the traditional IEGT structure is 2.2*10 -3 Mhos/um.
  • the initial Miller capacitance of the IEGT structure in this embodiment is 0.4*10 -3 Mhos/um.
  • the initial Miller capacitance of the IEGT structure in this embodiment is only
  • the traditional IEGT structure is about 20% of the initial Miller capacitance, and the simulation results show that the IEGT structure in this embodiment can greatly reduce the value of the Miller capacitance CGC.
  • the Miller capacitance of the IEGT structure in this embodiment is greatly reduced, reducing the switching loss of the IEGT structure, and at the same time improving the withstand voltage characteristics of the IEGT structure device.
  • Fig. 14 is a schematic diagram of another IEGT structure according to an embodiment of the present invention. As shown in Figure 14, the formation process of the IEGT structure includes:
  • a substrate 101 is provided, on which a drift layer 102 is formed;
  • a gate and at least one first emitter are formed in the first trench.
  • it specifically includes the following steps: forming a first polysilicon layer in the first trench; filling the first trench with the first polysilicon layer; etching part of the first polysilicon layer; to form the second trench, and at the same time form the bottom first emitter 105c; deposit the first isolation layer 104a in the second trench; the first isolation layer 104a covers the second trench, and the first isolation layer 104a is used for
  • the gate 106 is isolated from the bottom first emitter 105c and the top first emitter 105b.
  • a second gate oxide layer is deposited, and the second gate oxide layer covers the gate and the first emitter.
  • the second gate oxide is also used to isolate the gate 106 and the top first emitter 105b.
  • two first emitters are formed in each of the first trenches 103, and a part of the first emitters is the bottom first emitter.
  • An emitter 105c is located at the bottom of the first trench, and another part of the first emitter, that is, the top first emitter 105b is arranged side by side with the gate 106 .
  • the top first emitter 105 b is flush with the bottom surface of the gate 106 .
  • the first emitter located at the bottom of the first trench, that is, the bottom first emitter 105c has a rectangular longitudinal cross-sectional shape, and the top first emitter 105b has a longitudinal cross-sectional shape that is also rectangular.
  • Fig. 15 is a schematic diagram of another IEGT structure according to an embodiment of the present invention.
  • the formation process of the IEGT structure shown in Figure 15 includes:
  • a substrate 101 is provided, on which a drift layer 102 is formed;
  • a gate and at least one first emitter are formed in the first trench.
  • the specific steps include: depositing a gate oxide layer 104 in the first trench; the gate oxide layer 104 filling at least one-third of the height of the first trench; In 104, etch a second groove, the second groove is an inverted triangle; deposit a first polysilicon layer, and the first polysilicon layer covers the second groove; in the first polysilicon layer
  • the silicon layer forms a patterned photoresist, and exposes a part of the first polysilicon layer to be etched, and etches a part of the first polysilicon layer to form a third trench, and at the same time forms a bottom first emitter 105c ; depositing a first isolation layer 104a in the third trench; the first isolation layer 104a covers the third trench, and the first isolation layer 104a is used to isolate the gate 106 from the bottom first emitter 105c and The top first emitter 105b, depositing a second polysilicon layer, the second polysili
  • a second gate oxide layer is deposited covering the gate 106 and the top first emitter 105b.
  • the second gate oxide is also used to isolate the gate 106 and the top first emitter 105b.
  • the first emitter formed in the first trench includes a top first emitter 105b and a bottom first emitter 105c, and the top first emitter 105b is flush with the bottom surface of the gate 106 .
  • the longitudinal section shape of the bottom first emitter 105c is an inverted triangle, and the longitudinal section shape of the top first emitter 105b is a rectangle.
  • Fig. 16 is a schematic diagram of another IEGT structure according to an embodiment of the present invention.
  • the formation process of the IEGT structure shown in Figure 16 includes:
  • a substrate 101 is provided, on which a drift layer 102 is formed;
  • forming the gate and at least one first emitter in the first trench includes: forming a first polysilicon layer in the first trench; forming a patterned polysilicon layer in the first polysilicon layer photoresist, and expose a part of the first polysilicon layer to be etched, etch a part of the first polysilicon layer to form a second trench, and simultaneously form two bottom first emitters 105c;
  • the first isolation layer 104a is deposited in the second trench, the first isolation layer 104a is used to isolate the gate 106 from the bottom first emitter 105c and the top first emitter 105b; deposit a second polysilicon layer, the first Two polysilicon layers cover the second trench and fill up the second trench; a patterned photoresist is formed on the second polysilicon layer, and the patterned photoresist exposes Part of the second polysilicon layer, etching the second polysilicon layer to form the gate 106 and the top first emitter 105b;
  • the first emitter formed in the first trench includes one top first emitter 105b and two bottom first emitters 105c.
  • the vertical cross-sectional shapes of the two bottom first emitters 105c are both rectangular, and the vertical cross-sectional shape of the top first emitter 105b is also rectangular.
  • an IEGT structure and its manufacturing method are provided.
  • the IEGT structure includes a substrate, a drift layer, a first trench, a first emitter, a gate, a body region, an active region and the second emitter.
  • a drift layer is formed on the substrate.
  • a first trench is formed in the drift layer.
  • At least one first emitter and gate are formed in the first trench, the first emitter and the gate are in a left and right separation structure in the first trench, and formed in the drift region
  • a body region, an active region is formed in the body region on a side close to the gate, and the second emitter is electrically connected to the body region and the active region.
  • At least one first emitter and gate in the first trench By forming at least one first emitter and gate in the first trench, the contact area between the gate and the collector in the first trench is reduced, and the Miller capacitance of the IEGT structure is greatly reduced. Simulation results show that, The initial value is only about 20% of the traditional IEGT. At least one first emitter in the first trench is connected to the second emitter. On the one hand, it reduces the Miller capacitance and reduces the switching loss. On the other hand, the first emitter The pole can be used as a field plate, without affecting the turn-on and turn-off characteristics of the IEGT, it can accelerate the depletion of the area between the trenches, and improve the withstand voltage reliability of the product.

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Abstract

Provided in the present invention is a method for manufacturing an IEGT structure. The IEGT structure comprises: a substrate, on which a drift layer is formed; a first trench, which is formed in the drift layer; at least one first emitter electrode and a gate electrode, which are formed in the first trench, wherein the first emitter electrode and the gate electrode are isolated by means of a first isolation layer, and the first emitter electrode and the gate electrode are of a left-right separation structure in the first trench; body regions, which are formed in the drift layer on two sides of the first trench; an active region, which is formed in the body region on one side of the first trench, wherein the active region is located in the body region on the side close to the gate electrode; and a second emitter electrode, which is formed in the body region and is electrically connected to the body region and the active region. By means of the present invention, the contact area between a gate electrode and a collector electrode in a first trench is reduced, such that a Miller capacitance of the IEGT structure is greatly reduced, thereby reducing the switching loss, and facilitating an improvement in the voltage-withstanding reliability of the product.

Description

IEGT结构及其制作方法IEGT structure and its fabrication method 技术领域technical field
本发明涉及功率半导体器件技术领域，特别涉及一种IEGT结构及其制作方法。The invention relates to the technical field of power semiconductor devices, in particular to an IEGT structure and a manufacturing method thereof.
背景技术Background technique
IGBT(Insulated Gate Bipolar Transistor，绝缘栅双极型晶体管)器件结合了MOS(Metal-Oxide-Semiconductor Field-Effect Transistor,金属-氧化物半导体场效应晶体管)的电压控制和BJT(Bipolar Junction Transistor，双极结型晶体管)的电导调制电流的特性，具有输入阻抗高、开关损耗小、速度快、电压驱动功率小等特点，广泛地应用于电力输变送、高速列车牵引、工业驱动、清洁能源等诸多领域。为了进一步降低沟槽栅IGBT的导通损耗，业界提出了电子注入增强栅晶体管(Injection Enhanced Gate Transistor，IEGT)。但是传统沟槽栅IGBT和IEGT都存在一个问题，沟槽栅极一般往下刻蚀深度较大，与集电极接触面积较多，势必会带来米勒电容变大的问题，米勒电容增大则会引起IGBT器件开关损耗的增大。IGBT (Insulated Gate Bipolar Transistor, Insulated Gate Bipolar Transistor) device combines the voltage control of MOS (Metal-Oxide-Semiconductor Field-Effect Transistor, Metal-Oxide Semiconductor Field Effect Transistor) and BJT (Bipolar Junction Transistor, bipolar Junction transistor) has the characteristics of conductance modulation current, has the characteristics of high input impedance, small switching loss, fast speed, and low voltage drive power, and is widely used in power transmission and transmission, high-speed train traction, industrial drive, clean energy, etc. field. In order to further reduce the conduction loss of the trench gate IGBT, the industry has proposed an electron injection enhanced gate transistor (Injection Enhanced Gate Transistor, IEGT). However, there is a problem in both the traditional trench gate IGBT and IEGT. The trench gate generally has a larger etching depth and a larger contact area with the collector, which will inevitably lead to the problem of increased Miller capacitance. A large value will cause an increase in the switching loss of the IGBT device.
图1为常规的沟槽栅IGBT结构的示意图。如图1所示，现有的N型IGBT结构包括衬底(N+型)10，在衬底10上设有漂移层(为N-型外延层，也可以称为N-漂移层)11，外延层11上设有基区(为P型，又称为体区)12，在基区12的两侧设有发射区(为N+型，也称为源区)14，在基区12中设有栅极沟槽，栅极沟槽的内表面上形成有栅氧层并填充有栅极13，在衬底10的正面设有金属发射极15，其通过发射极接触插塞16与发射区14电性连接，在衬底10的背面设有集电区(P+型)17，集电区17的底面上可以形成有与其欧姆接触的金属集电极。FIG. 1 is a schematic diagram of a conventional trench gate IGBT structure. As shown in FIG. 1, the existing N-type IGBT structure includes a substrate (N+ type) 10, on which a drift layer (N-type epitaxial layer, also referred to as an N-drift layer) 11 is provided, The epitaxial layer 11 is provided with a base region (for P type, also called body region) 12, and on both sides of base region 12 is provided with emitter region (for N+ type, also called source region) 14, in base region 12 A gate trench is provided, a gate oxide layer is formed on the inner surface of the gate trench and filled with a gate 13, and a metal emitter 15 is provided on the front surface of the substrate 10, which is connected to the emitter via an emitter contact plug 16. The region 14 is electrically connected, and a collector region (P+ type) 17 is provided on the back of the substrate 10, and a metal collector electrode in ohmic contact with the collector region 17 may be formed on the bottom surface.
为了进一步降低沟槽栅IGBT的导通损耗，业界提出了电子注入增强栅晶体管(Injection Enhanced Gate Transistor，IEGT)，具体结构如图2所示，与图1中传统沟槽栅IGBT相比，在一个元胞中，只有沟槽的一侧是有N+有源区的，所以只有一侧有沟道可以通过电子，而在沟槽另一侧N-区中，没有发射极抽 取空穴，所以在这一侧的N型区域可以储存空穴，漂移层内增加的空穴与电子进一步发生电导调制效应，达到减小IGBT导通压降的目的。In order to further reduce the conduction loss of the trench gate IGBT, the industry has proposed an electron injection enhanced gate transistor (Injection Enhanced Gate Transistor, IEGT), the specific structure is shown in Figure 2, compared with the traditional trench gate IGBT in Figure 1, in In a cell, only one side of the trench has an N+ active region, so only one side of the trench can pass electrons, and in the N- region on the other side of the trench, there is no emitter to extract holes, so The N-type region on this side can store holes, and the increased holes and electrons in the drift layer further have a conductance modulation effect, achieving the purpose of reducing the IGBT turn-on voltage drop.
但是发明人研究发现，传统沟槽栅IGBT和IEGT都存在一个问题，沟槽栅极一般向下刻蚀深度较大，与集电极接触面积较多，这就会带来米勒电容变大的问题，米勒电容增大则会引起IGBT器件开关损耗的增大。However, the inventors found that there is a problem in both the traditional trench gate IGBT and IEGT. The trench gate generally has a large downward etching depth and a large contact area with the collector, which will lead to increased Miller capacitance. The problem is that the increase of Miller capacitance will cause the increase of switching loss of IGBT device.
发明内容Contents of the invention
本发明的目的在于提供一种IEGT结构及其制作方法，以解决IEGT器件米勒电容大，会引起开关损耗增大的问题。The object of the present invention is to provide an IEGT structure and a manufacturing method thereof, so as to solve the problem that the IEGT device has a large Miller capacitance, which causes an increase in switching loss.
为解决上述技术问题，本发明提供一种IEGT结构，包括，In order to solve the above technical problems, the present invention provides an IEGT structure, including:
衬底和形成于所述衬底上的漂移层；a substrate and a drift layer formed on the substrate;
第一沟槽，形成于所述漂移层中；a first trench formed in the drift layer;
栅极和至少一个第一发射极，形成于所述第一沟槽中，所述第一发射极与所述栅极之间通过第一隔离层形成左右分离结构；The gate and at least one first emitter are formed in the first trench, and a left and right separation structure is formed between the first emitter and the gate through a first isolation layer;
体区，形成于所述第一沟槽的两侧的漂移层中；a body region formed in the drift layer on both sides of the first trench;
有源区，形成于所述第一沟槽靠近所述栅极的一侧的体区中；以及，an active region formed in a body region on a side of the first trench close to the gate; and,
第二发射极，形成于所述体区上，并与所述体区和所述有源区电连接。The second emitter is formed on the body region and is electrically connected with the body region and the active region.
可选的，所述栅极的纵向长度大于所述体区的结深。Optionally, the vertical length of the gate is greater than the junction depth of the body region.
可选的，每个所述第一沟槽中形成至少一个第一发射极，并在所述栅极的一侧和底部呈半包围分布。Optionally, at least one first emitter is formed in each of the first trenches, and is half-surrounded on one side and the bottom of the gate.
可选的，所述第一发射极为一整体时，呈L型将所述栅极的一侧和底部包围；所述第一发射极为多个时，若干所述第一发射极均匀分布于所述栅极的一侧和底部，呈半包围状。Optionally, when the first emitter is a whole, it is L-shaped and surrounds one side and the bottom of the gate; when there are multiple first emitters, several first emitters are evenly distributed on the One side and the bottom of the grid are semi-surrounded.
可选的，所述漂移层为第一导电类型的漂移层，且所述第一沟槽的底面高于所述漂移层的底面。Optionally, the drift layer is a drift layer of the first conductivity type, and the bottom surface of the first trench is higher than the bottom surface of the drift layer.
可选的，所述IEGT结构还包括形成于所述第一沟槽中的栅氧化层，所述栅氧化层覆盖所述第一沟槽的侧壁和底面。Optionally, the IEGT structure further includes a gate oxide layer formed in the first trench, and the gate oxide layer covers sidewalls and bottom surfaces of the first trench.
可选的，所述IEGT结构还包括第二隔离层，所述第二隔离层形成于所述衬底上。Optionally, the IEGT structure further includes a second isolation layer formed on the substrate.
可选的，所述IEGT结构还包括第二导电类型的集电极，所述第二导电类型的集电极形成于所述衬底的底面上。Optionally, the IEGT structure further includes a collector of the second conductivity type, and the collector of the second conductivity type is formed on the bottom surface of the substrate.
基于同一发明构思，本发明提供一种IEGT结构的制作方法，包括，Based on the same inventive concept, the present invention provides a method for fabricating an IEGT structure, including:
提供一衬底，所述衬底上形成有漂移层；providing a substrate on which a drift layer is formed;
在所述漂移层中形成第一沟槽；forming a first trench in the drift layer;
在所述第一沟槽内形成栅极和至少一个第一发射极，所述第一发射极和所述栅极通过第一隔离层形成左右分离结构；A gate and at least one first emitter are formed in the first trench, and the first emitter and the gate form a left and right separation structure through a first isolation layer;
在所述第一沟槽的两侧的漂移层中形成体区；forming body regions in the drift layer on both sides of the first trench;
在所述第一沟槽靠近所述栅极的一侧的体区中形成有源区；以及，forming an active region in a body region of a side of the first trench close to the gate; and,
在所述体区上形成第二发射极，所述第二发射极与所述体区和所述有源区连接。A second emitter is formed on the body region, the second emitter being connected to the body region and the active region.
可选的，在所述第一沟槽内形成栅极以及至少一个第一发射极包括：Optionally, forming the gate and at least one first emitter in the first trench includes:
在所述第一沟槽内形成第一多晶硅层；forming a first polysilicon layer in the first trench;
刻蚀部分第一多晶硅层以形成第二沟槽，同时形成第一发射极；Etching part of the first polysilicon layer to form a second trench, and simultaneously forming a first emitter;
在所述第二沟槽中形成所述第一隔离层；forming the first isolation layer in the second trench;
形成第二多晶硅层，所述第二多晶硅层覆盖所述第二沟槽并填满所述第二沟槽以形成栅极。A second polysilicon layer is formed, the second polysilicon layer covers and fills up the second trench to form a gate.
可选的，在所述沟槽内形成第一多晶硅层之前，在所述沟槽内形成栅氧化层，所述栅氧化层覆盖所述第一沟槽的侧壁和底面。Optionally, before forming the first polysilicon layer in the trench, a gate oxide layer is formed in the trench, and the gate oxide layer covers sidewalls and bottom surfaces of the first trench.
可选的，在所述第一沟槽内形成栅极以及至少一个第一发射极包括：Optionally, forming the gate and at least one first emitter in the first trench includes:
在所述第一沟槽内形成第一多晶硅层；forming a first polysilicon layer in the first trench;
刻蚀部分第一多晶硅层以形成第二沟槽，同时形成一部分的第一发射极；etching a part of the first polysilicon layer to form a second trench, and simultaneously forming a part of the first emitter;
在所述第二沟槽中形成第一隔离层；forming a first isolation layer in the second trench;
形成第二多晶硅层，所述第二多晶硅层覆盖所述第二沟槽并填满所述第二沟槽；forming a second polysilicon layer, the second polysilicon layer covering the second trench and filling the second trench;
刻蚀所述第二多晶硅层以形成栅极和另一部分的第一发射极。Etching the second polysilicon layer to form a gate and another part of the first emitter.
可选的，在所述第一沟槽内形成栅极和至少一个第一发射极包括：Optionally, forming the gate and at least one first emitter in the first trench includes:
在所述第一沟槽内形成栅氧化层；所述栅氧化层至少填充所述第一沟槽的三分之一的高度；forming a gate oxide layer in the first trench; the gate oxide layer fills at least one third of the height of the first trench;
在所述栅氧化层中刻蚀第二沟槽，所述第二沟槽为倒三角形；etching a second trench in the gate oxide layer, the second trench being an inverted triangle;
形成第一多晶硅层，所述第一多晶硅层覆盖所述第二沟槽；forming a first polysilicon layer, the first polysilicon layer covering the second trench;
刻蚀部分第一多晶硅层以形成第三沟槽，同时形成一部分的第一发射极；Etching part of the first polysilicon layer to form a third trench, and simultaneously forming a part of the first emitter;
在所述第三沟槽内形成第一隔离层；forming a first isolation layer in the third trench;
形成第二多晶硅层，所述第二多晶硅层覆盖所述第三沟槽并填满所述第三沟槽；forming a second polysilicon layer, the second polysilicon layer covering the third trench and filling the third trench;
刻蚀所述第二多晶硅层，以形成所述栅极和另一部分的第一发射极；etching the second polysilicon layer to form the gate and another part of the first emitter;
其中，所述第一发射极的形状为倒三角形。Wherein, the shape of the first emitter is an inverted triangle.
可选的，在所述第一沟槽内形成栅极以及至少一个第一发射极包括：Optionally, forming the gate and at least one first emitter in the first trench includes:
在所述第一沟槽内形成第一多晶硅层；forming a first polysilicon layer in the first trench;
刻蚀部分第一多晶硅层以形成第二沟槽，同时形成一部分的第一发射极；etching a part of the first polysilicon layer to form a second trench, and simultaneously forming a part of the first emitter;
在所述第二沟槽中形成第一隔离层；forming a first isolation layer in the second trench;
形成第二多晶硅层，所述第二多晶硅层覆盖所述第二沟槽并填满所述第二沟槽；forming a second polysilicon layer, the second polysilicon layer covering the second trench and filling the second trench;
刻蚀所述第二多晶硅层，以形成栅极和另一部分的第一发射极。Etching the second polysilicon layer to form the gate and another part of the first emitter.
可选的，在所述第一沟槽中形成栅极以及至少一个第一发射极后，形成第二栅氧化层，所述第二栅氧化层覆盖所述栅极和所述第一发射极。Optionally, after the gate and at least one first emitter are formed in the first trench, a second gate oxide layer is formed, and the second gate oxide layer covers the gate and the first emitter .
可选的，在所述第一沟槽的一侧的所述体区上形成所述有源区之后，形成第二隔离层，所述第二隔离层覆盖所述有源区、所述第一沟槽和所述体区。Optionally, after the active region is formed on the body region on one side of the first trench, a second isolation layer is formed, and the second isolation layer covers the active region, the first trench, and the active region. a trench and the body region.
可选的，在形成第二发射极之前，刻蚀所述第二隔离层和所述有源区以形成接触孔。Optionally, before forming the second emitter, etching the second isolation layer and the active region to form a contact hole.
与现有技术相比，本发明的有益效果如下：Compared with the prior art, the beneficial effects of the present invention are as follows:
本发明提供的一种IEGT结构及其制作方法，通过在所述第一沟槽内形成至少一个第一发射极和栅极，减小了第一沟槽内的栅极与集电极的接触面积，使得IEGT结构的米勒电容大幅降低，第一沟槽内的至少一个第一发射极与第二发射极连接，一方面起到降低米勒电容减小了开关损耗，另一方面，第一发射极可以作为场板，在不影响IEGT开启特性和关断特性，可以加速沟槽之间的区域耗尽，提升产品的耐压可靠性。In the IEGT structure and its manufacturing method provided by the present invention, by forming at least one first emitter and gate in the first trench, the contact area between the gate and the collector in the first trench is reduced , so that the Miller capacitance of the IEGT structure is greatly reduced. At least one first emitter in the first trench is connected to the second emitter. On the one hand, it reduces the Miller capacitance and reduces the switching loss. On the other hand, the first The emitter can be used as a field plate, without affecting the turn-on and turn-off characteristics of the IEGT, it can accelerate the depletion of the area between the trenches and improve the withstand voltage reliability of the product.
附图说明Description of drawings
图1是现有技术中一种沟槽栅IGBT结构的示意图；1 is a schematic diagram of a trench gate IGBT structure in the prior art;
图2是现有技术中一种IEGT结构的示意图；Fig. 2 is a schematic diagram of an IEGT structure in the prior art;
图3是本发明实施例的一种IEGT结构的制作方法流程图；Fig. 3 is a flow chart of a fabrication method of an IEGT structure according to an embodiment of the present invention;
图4至图13是本发明实施例的IEGT结构的制作方法对应的结构示意图；4 to 13 are structural schematic diagrams corresponding to the fabrication method of the IEGT structure according to the embodiment of the present invention;
图14是本发明实施例的另一种IEGT结构的示意图；FIG. 14 is a schematic diagram of another IEGT structure according to an embodiment of the present invention;
图15是本发明实施例的另一种IEGT结构的示意图；FIG. 15 is a schematic diagram of another IEGT structure according to an embodiment of the present invention;
图16是本发明实施例的另一种IEGT结构的示意图。Fig. 16 is a schematic diagram of another IEGT structure according to an embodiment of the present invention.
图中，In the figure,
10-衬底；11-外延层；13-栅极；14-发射区；15-金属发射极；16-发射极接触插塞；17-集电区；10-substrate; 11-epitaxial layer; 13-gate; 14-emitter; 15-metal emitter; 16-emitter contact plug; 17-collector;
101-衬底；102-漂移层；103-第一沟槽；103a-第二沟槽；104-栅氧化层；104a-第一隔离层；105-第一多晶硅层；105a-第一发射极；105b-顶部第一发射极；105c-底部第一发射极；106-栅极；107-体区；108-有源区；109-第二隔离层；110-接触孔；111-第二发射极；112-集电极；113-集电极金属。101-substrate; 102-drift layer; 103-first trench; 103a-second trench; 104-gate oxide layer; 104a-first isolation layer; 105-first polysilicon layer; 105a-first Emitter; 105b-top first emitter; 105c-bottom first emitter; 106-gate; 107-body region; 108-active region; 109-second isolation layer; 110-contact hole; 111-th Two emitters; 112-collector; 113-collector metal.
具体实施方式Detailed ways
在下文的描述中，给出了大量具体的细节以便提供对本实用新型更为彻底的理解。然而，对于本领域技术人员而言显而易见的是，本实用新型可以无需一个或多个这些细节而得以实施。在其他的例子中，为了避免与本实用新型发生混淆，对于本领域公知的一些技术特征未进行描述。应当理解的是，本实用新型能够以不同形式实施，而不应当解释为局限于这里提出的实施例。相反地，提供这些实施例将使公开彻底和完全，并且将本实用新型的范围完全地传递给本领域技术人员。在附图中，为了清楚，层和区的尺寸以及相对尺寸可能被夸大。自始至终相同附图标记表示相同的元件。应当明白，当元件或层被称为"在…上"、"连接到"其它元件或层时，其可以直接地在其它元件或层上、连接其它元件或层，或者可以存在居间的元件或层。相反，当元件被称为"直接在…上"、"直接连接到"其它元件或层时，则不存在居间的元件或层。尽管可使用术语第一、第二、第三等描述各种元件、部件、区、层和/或 部分，这些元件、部件、区、层和/或部分不应当被这些术语限制。这些术语仅仅用来区分一个元件、部件、区、层或部分与另一个元件、部件、区、层或部分。因此，在不脱离本实用新型教导之下，下面讨论的第一元件、部件、区、层或部分可表示为第二元件、部件、区、层或部分。空间关系术语例如“在……之下”、“在下面”、“下面的”、“在……之上”、“在上面”、“上面的”等，在这里可为了方便描述而被使用从而描述图中所示的一个元件或特征与其它元件或特征的关系。应当明白，除了图中所示的取向以外，空间关系术语意图还包括使用和操作中的器件的不同取向。例如，如果附图中的器件翻转，然后，描述为“在……之下”、“在下面”、“下面的”元件或特征将取向为在其它元件或特征“上”。器件可以另外地取向(旋转90度或其它取向)并且在此使用的空间描述语相应地被解释。在此使用的术语的目的仅在于描述具体实施例并且不作为本实用新型的限制。在此使用时，单数形式的"一"、"一个"和"所述/该"也意图包括复数形式，除非上下文清楚的指出另外的方式。还应明白术语“包括”用于确定可以特征、步骤、操作、元件和/或部件的存在，但不排除一个或更多其它的特征、步骤、操作、元件、部件和/或组的存在或添加。在此使用时，术语"和/或"包括相关所列项目的任何及所有组合。In the following description, numerous specific details are given in order to provide a more thorough understanding of the present invention. It will be apparent, however, to one skilled in the art that the present invention may be practiced without one or more of these details. In other examples, in order to avoid confusion with the present invention, some technical features known in the art are not described. It should be understood that the invention can be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity. Like reference numerals refer to like elements throughout. It will be understood that when an element or layer is referred to as being "on" or "connected to" another element or layer, it can be directly on, connected to the other element or layer, or intervening elements or layers may be present. layer. In contrast, when an element is referred to as being "directly on" or "directly connected to" another element or layer, there are no intervening elements or layers present. Although the terms first, second, third etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention. Spatial terms such as "under", "beneath", "underneath", "over", "above", "above", etc., may be used herein for convenience of description The relationship of one element or feature to other elements or features shown in the figures is thus described. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as "beneath," "beneath," or "beneath" would then be oriented "above" the other elements or features. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly. The terminology used herein is for the purpose of describing particular embodiments only and not as limitations of the present invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly dictates otherwise. It should also be understood that the term "comprising" is used to determine the presence of certain features, steps, operations, elements and/or components, but does not exclude the presence or presence of one or more other features, steps, operations, elements, components and/or groups. Add to. As used herein, the term "and/or" includes any and all combinations of the associated listed items.
IEGT米勒电容大，会引起开关损耗增大，针对此问题，通常选择在图2所示的结构中，与常规IEGT相比，加厚栅氧化层厚度从而达到降低米勒电容的目的。增加栅氧厚度虽然能降低米勒电容，但是会引起器件阈值电压的上升和开启损耗的上升。另外一种方法则是将沟槽做小，进一步总体来达到降低米勒电容的目的。然而，沟槽做小、总面积降低的方法会给制备工艺带来挑战，目前沟槽宽度已经比较小，进一步缩小沟槽宽度会引起回填多晶硅(Poly)时异常率的提升，从而影响产品的良率。The large Miller capacitance of IEGT will cause increased switching loss. To solve this problem, the structure shown in Figure 2 is usually selected. Compared with the conventional IEGT, the thickness of the gate oxide layer is thickened to reduce the Miller capacitance. Although increasing the thickness of the gate oxide can reduce the Miller capacitance, it will cause the rise of the threshold voltage of the device and the rise of the turn-on loss. Another method is to make the groove smaller, and further reduce the Miller capacitance as a whole. However, the method of making the trench smaller and reducing the total area will bring challenges to the manufacturing process. At present, the trench width is already relatively small, and further reducing the trench width will cause an increase in the abnormal rate when backfilling polysilicon (Poly), thus affecting product quality. yield.
发明人进一步研究发现，在低压MOS领域，主流的结构是分离栅结构，例如，一种屏蔽栅功率MOS的器件包括主结构及其可变结构，其沟槽分为上下两个极，下面的沟槽不接电极，浮空布置，这样也能减少栅极(Gate)与集电极的接触面积，从而达到降低弥勒电容的作用。然而，这种可变结构上部分为左右两个电极，因为在MOS器件应用时，必须是二者都要连接栅极，没办法连接其他电极，不然会影响MOS器件的主要功能。此外，低压SGT中 的分离栅结构，下面的电极一般是浮空布置或者连接发射极，上面的电极为栅极，其将上面栅极分成两个的小的栅极，由于减小了栅极与集电极的接触面积，可以实现降低米勒电容的目的，但是栅极的面积依然比较大，无法进一步降低米勒电容。The inventor further researched and found that in the field of low-voltage MOS, the mainstream structure is a split gate structure. For example, a shielded gate power MOS device includes a main structure and its variable structure, and its trench is divided into upper and lower poles. The groove is not connected to the electrode, and is arranged in a floating position, which can also reduce the contact area between the gate (Gate) and the collector, thereby achieving the effect of reducing the Maitreya capacitance. However, the upper part of this variable structure is divided into left and right electrodes, because in the application of MOS devices, both of them must be connected to the gate, and there is no way to connect other electrodes, otherwise the main function of the MOS device will be affected. In addition, in the split-gate structure in low-voltage SGT, the lower electrode is generally floating or connected to the emitter, and the upper electrode is the gate, which divides the upper gate into two small gates. The contact area with the collector can achieve the purpose of reducing the Miller capacitance, but the area of the gate is still relatively large, which cannot further reduce the Miller capacitance.
基于此，本发明提供的一种IEGT结构及其制作方法，通过在所述第一沟槽内形成至少一个第一发射极和栅极，减小了第一沟槽内的栅极与集电极的接触面积，使得IEGT结构的米勒电容大幅降低。第一沟槽内的至少一个第一发射极与第二发射极连接，一方面起到降低米勒电容减小了开关损耗，另一方面，第一发射极可以作为场板，在不影响IEGT开启特性和关断特性，可以加速沟槽之间的区域耗尽，提升产品的耐压可靠性。Based on this, the present invention provides an IEGT structure and its fabrication method. By forming at least one first emitter and gate in the first trench, the gate and collector in the first trench are reduced. The small contact area makes the Miller capacitance of the IEGT structure greatly reduced. At least one first emitter in the first trench is connected to the second emitter. On the one hand, it can reduce the Miller capacitance and reduce the switching loss. On the other hand, the first emitter can be used as a field plate without affecting the IEGT. The turn-on and turn-off characteristics can accelerate the depletion of the area between the trenches and improve the withstand voltage reliability of the product.
以下结合附图和具体实施例对本发明提出的一种IEGT结构及其制作方法作进一步详细说明。根据下面说明和权利要求书，本发明的优点和特征将更清楚。需说明的是，附图均采用非常简化的形式且均使用非精准的比例，仅用以方便、明晰地辅助说明本发明实施例的目的。An IEGT structure proposed by the present invention and its manufacturing method will be further described in detail below in conjunction with the accompanying drawings and specific embodiments. Advantages and features of the present invention will be apparent from the following description and claims. It should be noted that all the drawings are in very simplified form and use inaccurate scales, and are only used to facilitate and clearly assist the purpose of illustrating the embodiments of the present invention.
具体的，请参考图13，其为本发明实施例的另一种IEGT结构的示意图，本实施例提供的IEGT结构，包括衬底101、漂移层102、第一沟槽103、第一发射极105a、栅极106、体区107、有源区108以及第二发射极111。所述衬底101上形成有漂移层102。第一沟槽103形成于所述漂移层102中。栅极106和至少一个第一发射极105a形成于所述第一沟槽103中，所述第一发射极105a与所述栅极106之间通过第一隔离层104a隔离，所述第一发射极105a与所述栅极106在所述第一沟槽103内呈左右分离结构。体区107形成于所述第一沟槽103的两侧的漂移层102中。有源区108形成于所述第一沟槽103的一侧的所述体区107中，所述有源区位于靠近所述栅极105a的一侧所述体区107中。所述第二发射极111形成于所述体区107上，并与所述体区107和所述有源区108电连接。Specifically, please refer to FIG. 13, which is a schematic diagram of another IEGT structure according to an embodiment of the present invention. The IEGT structure provided in this embodiment includes a substrate 101, a drift layer 102, a first trench 103, and a first emitter. 105 a , gate 106 , body region 107 , active region 108 and second emitter 111 . A drift layer 102 is formed on the substrate 101 . The first trench 103 is formed in the drift layer 102 . The gate 106 and at least one first emitter 105a are formed in the first trench 103, the first emitter 105a is isolated from the gate 106 by a first isolation layer 104a, and the first emitter The electrode 105 a and the gate 106 are in a left and right separation structure in the first trench 103 . The body region 107 is formed in the drift layer 102 on both sides of the first trench 103 . An active region 108 is formed in the body region 107 on one side of the first trench 103 , and the active region is located in the body region 107 on a side close to the gate 105 a. The second emitter 111 is formed on the body region 107 and electrically connected to the body region 107 and the active region 108 .
第一导电类型的漂移层102层叠于第一导电类型的衬底101上，所述第一沟槽103形成于所述第一导电类型的漂移层102中，且所述第一沟槽103的底面高于所述漂移层102的底面。以第一导电类型为N型、第二导电类型为P为例，本实施例中，所述衬底101为N+衬底，所述第一导电类型的漂移 层102为N-漂移层，N-漂移层可以是通过外延生长工艺形成在N+衬底上的N-外延层，也可以是通过离子注入工艺等形成的离子注入层。N+衬底的材料可以是任意合适的衬底材料，例如硅、锗、绝缘体上硅、硅锗或砷化镓。所述体区107为P型体区，所述P型体区形成在N-漂移层的上部。所述P型体区的一侧中形成有N+有源区。所述N+有源区位于靠近所述栅极106的一侧所述体区107中。所述体区107为P型体区，所述漂移层102为N型漂移层，所述体区107与所述漂移层102形成PN结。The drift layer 102 of the first conductivity type is stacked on the substrate 101 of the first conductivity type, the first trench 103 is formed in the drift layer 102 of the first conductivity type, and the first trench 103 The bottom surface is higher than the bottom surface of the drift layer 102 . Taking the first conductivity type as N-type and the second conductivity type as P as an example, in this embodiment, the substrate 101 is an N+ substrate, the drift layer 102 of the first conductivity type is an N-drift layer, and N - The drift layer may be an N- epitaxial layer formed on an N+ substrate by an epitaxial growth process, or an ion implantation layer formed by an ion implantation process or the like. The material of the N+ substrate can be any suitable substrate material, such as silicon, germanium, silicon-on-insulator, silicon germanium or gallium arsenide. The body region 107 is a P-type body region, and the P-type body region is formed on the upper part of the N-drift layer. An N+ active region is formed in one side of the P-type body region. The N+ active region is located in the body region 107 on a side close to the gate 106 . The body region 107 is a P-type body region, the drift layer 102 is an N-type drift layer, and the body region 107 and the drift layer 102 form a PN junction.
所述栅极106的纵向长度大于所述体区PN结的结深，以保证开启和关闭沟道，在保证开启和关闭沟道的条件下，所述栅极106和所述集电极的接触面积越小越好，所述第一发射极105a的形状可以根据实际情况设定，可以是一个也可以是多个。每个所述第一沟槽中形成至少一个第一发射极105a，并在所述栅极106的一侧和底部呈半包围分布，具体的，所述第一发射极105a为一整体时，呈L型将所述栅极106的一侧和底部包围；所述第一发射极105a为多个时，若干所述第一发射极105a均匀分布于所述栅极106的一侧和底部，呈半包围状。在本实施例中，N型漂移层和P型体区形成PN结，所述栅极的纵向长度大于所述PN结的结深。在本实施例中，每个所述第一沟槽103中形成有一个第一发射极105a。如图13所示，所述第一发射极105a的纵截面形状为L型。The vertical length of the gate 106 is greater than the junction depth of the PN junction of the body region to ensure the opening and closing of the channel. Under the condition of ensuring the opening and closing of the channel, the contact between the gate 106 and the collector The smaller the area, the better. The shape of the first emitter 105a can be set according to the actual situation, and there can be one or more. At least one first emitter 105a is formed in each of the first trenches, and is half-surrounded on one side and the bottom of the gate 106. Specifically, when the first emitter 105a is integrated, Surrounding one side and the bottom of the gate 106 in an L shape; when there are multiple first emitters 105a, several first emitters 105a are evenly distributed on one side and the bottom of the gate 106, It is semi-enclosed. In this embodiment, the N-type drift layer and the P-type body region form a PN junction, and the vertical length of the gate is greater than the junction depth of the PN junction. In this embodiment, a first emitter 105 a is formed in each of the first trenches 103 . As shown in FIG. 13 , the longitudinal cross-sectional shape of the first emitter 105 a is L-shaped.
所述IEGT结构还包括形成于所述第一沟槽103中的栅氧化层104，所述栅氧化层104覆盖所述第一沟槽103的侧壁和底面。The IEGT structure further includes a gate oxide layer 104 formed in the first trench 103 , and the gate oxide layer 104 covers sidewalls and bottom surfaces of the first trench 103 .
所述IEGT结构还包括第二隔离层109，所述第二隔离层109形成于所述第一沟槽103上，具体的，所述第二隔离层109覆盖体区107、有源区108和第一隔离层104a。The IEGT structure further includes a second isolation layer 109, the second isolation layer 109 is formed on the first trench 103, specifically, the second isolation layer 109 covers the body region 107, the active region 108 and The first isolation layer 104a.
所述IEGT结构还包括第二导电类型的集电极112，所述第二导电类型的集电极形成于所述衬底101的底面上。所述第二导电类型的集电极为P型集电极，所述P型集电极形成在N+衬底的背面上，可以通过离子注入工艺或者外延生长工艺等形成。The IEGT structure further includes a collector electrode 112 of a second conductivity type formed on the bottom surface of the substrate 101 . The collector of the second conductivity type is a P-type collector, and the P-type collector is formed on the back side of the N+ substrate, and can be formed by an ion implantation process or an epitaxial growth process.
图3是本发明实施例的IEGT结构的制作方法流程图。如图3所示，一种IEGT结构的制作方法，包括，FIG. 3 is a flowchart of a method for fabricating an IEGT structure according to an embodiment of the present invention. As shown in Figure 3, a fabrication method of an IEGT structure includes,
步骤S10，提供一衬底，所述衬底上形成有漂移层；Step S10, providing a substrate on which a drift layer is formed;
步骤S20，在所述漂移层中形成第一沟槽；Step S20, forming a first trench in the drift layer;
步骤S30，在所述第一沟槽内形成栅极以及至少一个第一发射极，所述第一发射极和所述栅极通过第一隔离层形成左右分离结构；Step S30, forming a gate and at least one first emitter in the first trench, the first emitter and the gate forming a left and right separation structure through a first isolation layer;
步骤S40，在所述第一沟槽的两侧的漂移层中形成体区；Step S40, forming body regions in the drift layer on both sides of the first trench;
步骤S50，在所述第一沟槽靠近所述栅极的一侧的体区上形成有源区；Step S50, forming an active region on the body region on the side of the first trench close to the gate;
步骤S60，在所述体区上形成第二发射极，所述第二发射极与所述体区和所述有源区连接。Step S60, forming a second emitter on the body region, the second emitter being connected to the body region and the active region.
图4至图13是本发明实施例的IEGT结构的制作方法对应的结构示意图；以下结合附图4～13对本发明实施例提供的半导体结构制作方法进行详细描述。4 to 13 are structural diagrams corresponding to the fabrication method of the IEGT structure according to the embodiment of the present invention; the semiconductor structure fabrication method provided by the embodiment of the present invention will be described in detail below in conjunction with FIGS. 4 to 13 .
如图4所示，提供一衬底101，所述衬底101上形成有漂移层102。所述衬底101例如是重掺杂N型(N+)衬底，所述漂移层102例如是N型(N-)漂移层。刻蚀所述漂移层102，形成第一沟槽103。具体实施时，在刻蚀所述漂移层102之前，在所述漂移层102上形成图形化的光刻胶，以图形化的光刻胶为掩膜，刻蚀所述漂移层102，刻蚀工艺例如是干法刻蚀工艺。As shown in FIG. 4 , a substrate 101 is provided, and a drift layer 102 is formed on the substrate 101 . The substrate 101 is, for example, a heavily doped N-type (N+) substrate, and the drift layer 102 is, for example, an N-type (N−) drift layer. The drift layer 102 is etched to form a first trench 103 . During specific implementation, before etching the drift layer 102, a patterned photoresist is formed on the drift layer 102, and the patterned photoresist is used as a mask to etch the drift layer 102, etch The process is, for example, a dry etching process.
如图5所示，在所述第一沟槽103内形成第一多晶硅层105。本实施例中，通过化学气相沉积工艺沉积第一多晶硅层105。可选地，在沉积第一多晶硅层105后，可以采用化学机械抛光工艺对多晶硅进行顶部平坦化，以去除第一沟槽103外围的多余多晶硅。形成第一多晶硅层105之前，可先在所述第一沟槽103中形成第一栅氧化层，所述第一多晶硅层105覆盖所述第一栅氧化层。形成所述第一栅氧化层的工艺例如是热氧化工艺或者沉积工艺等合适的工艺。As shown in FIG. 5 , a first polysilicon layer 105 is formed in the first trench 103 . In this embodiment, the first polysilicon layer 105 is deposited by a chemical vapor deposition process. Optionally, after depositing the first polysilicon layer 105 , the top of the polysilicon may be planarized by a chemical mechanical polishing process, so as to remove excess polysilicon around the first trench 103 . Before forming the first polysilicon layer 105 , a first gate oxide layer may be formed in the first trench 103 , and the first polysilicon layer 105 covers the first gate oxide layer. The process for forming the first gate oxide layer is, for example, a suitable process such as a thermal oxidation process or a deposition process.
如图6所示，刻蚀部分深度的所述第一多晶硅层105，以形成第二沟槽103a，同时形成第一发射极105a。刻蚀部分所述第一多晶硅层105例如是采用干法刻蚀工艺。在刻蚀部分所述第一多晶硅层105之前，在所述第一多晶硅层105上形成图形化的光刻胶，所述图形化的光刻胶暴露出部分所述第一多晶硅层105，并覆盖另一部分所述第一多晶硅层105，以图形化的光刻胶为掩膜，刻蚀暴露出的部分所述第一多晶硅层105，形成第一发射极105a。在 本实施例中，每个第一沟槽103中仅包括一个第一发射极，所述第一发射极105a呈L型。As shown in FIG. 6 , a partial depth of the first polysilicon layer 105 is etched to form a second trench 103 a and a first emitter 105 a at the same time. Etching part of the first polysilicon layer 105 is, for example, a dry etching process. Before etching part of the first polysilicon layer 105, a patterned photoresist is formed on the first polysilicon layer 105, and the patterned photoresist exposes part of the first polysilicon layer. crystalline silicon layer 105, and cover another part of the first polysilicon layer 105, using the patterned photoresist as a mask, etch the exposed part of the first polysilicon layer 105 to form the first emitter Pole 105a. In this embodiment, each first trench 103 includes only one first emitter, and the first emitter 105a is L-shaped.
如图7所示，在所述第二沟槽103a内形成第一隔离层104a。用于隔离栅极106和第一发射极105a。然后，沉积第二多晶硅层，所述第二多晶硅层覆盖所述第二沟槽103a并填满所述第二沟槽103a，以形成栅极106。本实施例中，可通过化学气相沉积工艺沉积第二多晶硅层。在所述第一沟槽103a内形成第一发射极105a和栅极106后，再沉积第二栅氧化层，所述第二栅氧化层覆盖所述栅极106和所述第一发射极105a。本实施实例中，分两次工艺形成的第一栅氧化层和第二栅氧化层共同构成栅氧化层104。As shown in FIG. 7, a first isolation layer 104a is formed in the second trench 103a. Used to isolate the gate 106 and the first emitter 105a. Then, a second polysilicon layer is deposited, and the second polysilicon layer covers and fills up the second trench 103 a to form the gate 106 . In this embodiment, the second polysilicon layer can be deposited by a chemical vapor deposition process. After forming the first emitter 105a and the gate 106 in the first trench 103a, a second gate oxide layer is deposited, and the second gate oxide covers the gate 106 and the first emitter 105a . In this implementation example, the first gate oxide layer and the second gate oxide layer formed in two processes together constitute the gate oxide layer 104 .
如图8所示，在步骤S40中，在所述漂移层102表面选择性注入P型杂质并推阱，形成体区107。本实施例中，所述体区107为P型体区，所述体区107位于所述第一沟槽103的两侧。注入P型杂质的工艺例如是自对准注入工艺。As shown in FIG. 8 , in step S40 , a P-type impurity is selectively implanted on the surface of the drift layer 102 and pushed to form a body region 107 . In this embodiment, the body region 107 is a P-type body region, and the body region 107 is located on both sides of the first trench 103 . The process of implanting P-type impurities is, for example, a self-aligned implant process.
如图9所示，在步骤S50中，在所述第一沟槽103的一侧的所述体区107中形成有源区108。所述有源区108例如为N+有源区。即，第一沟槽103一侧的体区107中形成了有源区108，第一沟槽103另一侧的体区107中则没有形成有源区。As shown in FIG. 9 , in step S50 , an active region 108 is formed in the body region 107 on one side of the first trench 103 . The active region 108 is, for example, an N+ active region. That is, the active region 108 is formed in the body region 107 on one side of the first trench 103 , and no active region is formed in the body region 107 on the other side of the first trench 103 .
如图10所示，形成第二隔离层109，所述第二隔离层109覆盖所述有源区108、所述第一沟槽103和所述体区107。形成第二隔离层109的工艺例如是化学气相沉积工艺。As shown in FIG. 10 , a second isolation layer 109 is formed, and the second isolation layer 109 covers the active region 108 , the first trench 103 and the body region 107 . The process for forming the second isolation layer 109 is, for example, a chemical vapor deposition process.
如图11所示，在形成第二发射极之前，刻蚀所述第二隔离层109和所述有源区108，以形成接触孔110。所述接触孔110贯穿所述第二隔离层109和所述有源区108，延伸至所述体区107表面上。As shown in FIG. 11 , before forming the second emitter, the second isolation layer 109 and the active region 108 are etched to form a contact hole 110 . The contact hole 110 penetrates through the second isolation layer 109 and the active region 108 , and extends to the surface of the body region 107 .
如图12所示，在步骤S60中，形成第二发射极111，所述第二发射极111与所述体区107和所述有源区108电性连接。所述第一发射极105a与所述第二发射极电性连接，所述第一发射极105a可以起到场板的作用，可以进一步提升产品耐压特性的可靠性。所述体区107的一侧与第二发射极111电性连接，所述体区107的另一侧与第二发射极111隔离，因为没有发射极来抽取空穴，所以空穴可以在P型区域下方堆积，增加的空穴浓度可以进一步发生 电导调制效应而达到降低导通压降的目的。As shown in FIG. 12 , in step S60 , a second emitter 111 is formed, and the second emitter 111 is electrically connected to the body region 107 and the active region 108 . The first emitter 105a is electrically connected to the second emitter, and the first emitter 105a can function as a field plate, which can further improve the reliability of the withstand voltage characteristic of the product. One side of the body region 107 is electrically connected to the second emitter 111, and the other side of the body region 107 is isolated from the second emitter 111, because there is no emitter to extract holes, so the holes can be in P The increased hole concentration can further produce conductance modulation effect to reduce the conduction voltage drop.
如图13所示，在远离所述漂移层102的衬底101的一侧(衬底101的背面)注入P型杂质，形成集电极112，所述集电极112为P型集电极，也就是P+区域。并且，在所述集电极112上沉积金属，形成用于引出集电极的集电极金属113，所述金属例如是铝。As shown in FIG. 13, P-type impurities are implanted on the side of the substrate 101 away from the drift layer 102 (the back side of the substrate 101) to form a collector electrode 112, and the collector electrode 112 is a P-type collector electrode, that is, P+ area. In addition, metal is deposited on the collector 112 to form a collector metal 113 for leading out the collector, and the metal is, for example, aluminum.
传统IEGT结构初始米勒电容为2.2*10 -3Mhos/um，本实施例中的IEGT结构初始米勒电容为0.4*10 -3Mhos/um，本实施例中的IEGT结构初始米勒电容只有传统IEGT结构初始米勒电容的20％左右，仿真结果上显示本实施例中的IEGT结构可以大幅度降低米勒电容CGC的数值。本实施例中的IEGT结构的米勒电容大幅降低，减小了IEGT结构的开关损耗，同时提升了IEGT结构器件的耐压特性。 The initial Miller capacitance of the traditional IEGT structure is 2.2*10 -3 Mhos/um. The initial Miller capacitance of the IEGT structure in this embodiment is 0.4*10 -3 Mhos/um. The initial Miller capacitance of the IEGT structure in this embodiment is only The traditional IEGT structure is about 20% of the initial Miller capacitance, and the simulation results show that the IEGT structure in this embodiment can greatly reduce the value of the Miller capacitance CGC. The Miller capacitance of the IEGT structure in this embodiment is greatly reduced, reducing the switching loss of the IEGT structure, and at the same time improving the withstand voltage characteristics of the IEGT structure device.
图14是本发明实施例的另一IEGT结构的示意图。如图14所示，所述IEGT结构的形成过程包括：Fig. 14 is a schematic diagram of another IEGT structure according to an embodiment of the present invention. As shown in Figure 14, the formation process of the IEGT structure includes:
首先，提供一衬底101，所述衬底上形成有漂移层102；First, a substrate 101 is provided, on which a drift layer 102 is formed;
接着，刻蚀所述漂移层102，形成第一沟槽；Next, etching the drift layer 102 to form a first trench;
接着，在所述第一沟槽内形成栅极以及至少一个第一发射极。例如，具体包括如下步骤：在所述第一沟槽内形成第一多晶硅层；所述第一多晶硅层填满所述第一沟槽，刻蚀部分第一多晶硅层，以形成第二沟槽，同时形成底部第一发射极105c；在所述第二沟槽内沉积第一隔离层104a；第一隔离层104a覆盖所述第二沟槽，第一隔离层104a用于隔离栅极106与底部第一发射极105c和顶部第一发射极105b。沉积第二多晶硅层，所述第二多晶硅层覆盖所述第二沟槽并填满所述第二沟槽；在所述第二多晶硅层上形成图形化的光刻胶，所述图形化的光刻胶暴露出部分第二多晶硅层，刻蚀所述第二多晶硅层，以形成栅极106和顶部第一发射极105b；Next, a gate and at least one first emitter are formed in the first trench. For example, it specifically includes the following steps: forming a first polysilicon layer in the first trench; filling the first trench with the first polysilicon layer; etching part of the first polysilicon layer; to form the second trench, and at the same time form the bottom first emitter 105c; deposit the first isolation layer 104a in the second trench; the first isolation layer 104a covers the second trench, and the first isolation layer 104a is used for The gate 106 is isolated from the bottom first emitter 105c and the top first emitter 105b. depositing a second polysilicon layer, the second polysilicon layer covering the second trench and filling the second trench; forming a patterned photoresist on the second polysilicon layer , the patterned photoresist exposes part of the second polysilicon layer, and the second polysilicon layer is etched to form the gate 106 and the top first emitter 105b;
在所述第一沟槽内形成至少第一发射极(包括顶部第一发射极105b和底部第一发射极105c)和栅极后，沉积第二栅氧化层，所述第二栅氧化层覆盖所述栅极和所述第一发射极。所述第二栅氧化层也用于隔离栅极106和顶部第一发射极105b。After forming at least the first emitter (including the top first emitter 105b and the bottom first emitter 105c) and the gate in the first trench, a second gate oxide layer is deposited, and the second gate oxide layer covers the gate and the first emitter. The second gate oxide is also used to isolate the gate 106 and the top first emitter 105b.
如图14所示，每个所述第一沟槽103中形成有两个第一发射极(包括顶 部第一发射极105b和底部第一发射极105c)，其中一部分第一发射极即底部第一发射极105c位于所述第一沟槽的底部，另一部分第一发射极即顶部第一发射极105b与所述栅极106并排布置。具体的，所述顶部第一发射极105b与所述栅极106的底面齐平。位于所述第一沟槽的底部的第一发射极即底部第一发射极105c的纵截面形状为矩形，所述顶部第一发射极105b的纵截面形状亦为矩形。As shown in FIG. 14, two first emitters (including the top first emitter 105b and the bottom first emitter 105c) are formed in each of the first trenches 103, and a part of the first emitters is the bottom first emitter. An emitter 105c is located at the bottom of the first trench, and another part of the first emitter, that is, the top first emitter 105b is arranged side by side with the gate 106 . Specifically, the top first emitter 105 b is flush with the bottom surface of the gate 106 . The first emitter located at the bottom of the first trench, that is, the bottom first emitter 105c has a rectangular longitudinal cross-sectional shape, and the top first emitter 105b has a longitudinal cross-sectional shape that is also rectangular.
图15是本发明实施例的另一IEGT结构的示意图。如图15所示的IEGT结构的形成过程包括：Fig. 15 is a schematic diagram of another IEGT structure according to an embodiment of the present invention. The formation process of the IEGT structure shown in Figure 15 includes:
首先，提供一衬底101，所述衬底上形成有漂移层102；First, a substrate 101 is provided, on which a drift layer 102 is formed;
接着，刻蚀所述漂移层102，形成第一沟槽；Next, etching the drift layer 102 to form a first trench;
接着，在所述第一沟槽内形成栅极以及至少一个第一发射极。例如，具体包括如下步骤包括：在所述第一沟槽内沉积栅氧化层104；所述栅氧化层104至少填充所述第一沟槽的三分之一的高度；在所述栅氧化层104中刻蚀第二沟槽，所述第二沟槽为倒三角形；沉积第一多晶硅层，所述第一多晶硅层覆盖所述第二沟槽；在所述第一多晶硅层形成图形化的光刻胶，并暴露出待刻蚀的部分第一多晶硅层，刻蚀部分第一多晶硅层，以形成第三沟槽，同时形成底部第一发射极105c；在所述第三沟槽内沉积第一隔离层104a；所述第一隔离层104a覆盖所述第三沟槽，第一隔离层104a用于隔离栅极106与底部第一发射极105c和顶部第一发射极105b，沉积第二多晶硅层，所述第二多晶硅层覆盖所述第三沟槽并填满所述第三沟槽；在所述第二多晶硅层上形成图形化的光刻胶，所述图形化的光刻胶暴露出部分第二多晶硅层，刻蚀所述第二多晶硅层，以形成栅极106和顶部第一发射极105b；Next, a gate and at least one first emitter are formed in the first trench. For example, the specific steps include: depositing a gate oxide layer 104 in the first trench; the gate oxide layer 104 filling at least one-third of the height of the first trench; In 104, etch a second groove, the second groove is an inverted triangle; deposit a first polysilicon layer, and the first polysilicon layer covers the second groove; in the first polysilicon layer The silicon layer forms a patterned photoresist, and exposes a part of the first polysilicon layer to be etched, and etches a part of the first polysilicon layer to form a third trench, and at the same time forms a bottom first emitter 105c ; depositing a first isolation layer 104a in the third trench; the first isolation layer 104a covers the third trench, and the first isolation layer 104a is used to isolate the gate 106 from the bottom first emitter 105c and The top first emitter 105b, depositing a second polysilicon layer, the second polysilicon layer covers the third trench and fills up the third trench; on the second polysilicon layer forming a patterned photoresist, the patterned photoresist exposes part of the second polysilicon layer, and etching the second polysilicon layer to form the gate 106 and the top first emitter 105b;
在所述第一沟槽内形成至少一个第一发射极和栅极后，沉积第二栅氧化层，所述第二栅氧化层覆盖所述栅极106和所述顶部第一发射极105b。所述第二栅氧化层也用于隔离栅极106和顶部第一发射极105b。After forming at least one first emitter and gate in the first trench, a second gate oxide layer is deposited covering the gate 106 and the top first emitter 105b. The second gate oxide is also used to isolate the gate 106 and the top first emitter 105b.
在本实施例中第一沟槽内形成的第一发射极包括顶部第一发射极105b和底部第一发射极105c，所述顶部第一发射极105b与所述栅极106的底面齐平。所述底部第一发射极105c的纵截面形状为倒三角形，所述顶部第一发射极105b的纵截面形状为矩形。In this embodiment, the first emitter formed in the first trench includes a top first emitter 105b and a bottom first emitter 105c, and the top first emitter 105b is flush with the bottom surface of the gate 106 . The longitudinal section shape of the bottom first emitter 105c is an inverted triangle, and the longitudinal section shape of the top first emitter 105b is a rectangle.
图16是本发明实施例的另一IEGT结构的示意图。如图16所示的IEGT结构的形成过程包括：Fig. 16 is a schematic diagram of another IEGT structure according to an embodiment of the present invention. The formation process of the IEGT structure shown in Figure 16 includes:
首先，提供一衬底101，所述衬底101上形成有漂移层102；First, a substrate 101 is provided, on which a drift layer 102 is formed;
接着，刻蚀所述漂移层102，形成第一沟槽；Next, etching the drift layer 102 to form a first trench;
接着，在所述第一沟槽内形成栅极以及至少一个第一发射极包括：在所述第一沟槽内形成第一多晶硅层；在所述第一多晶硅层形成图形化的光刻胶，并暴露出待刻蚀的部分第一多晶硅层，刻蚀部分第一多晶硅层，以形成第二沟槽，同时形成两个底部第一发射极105c；在所述第二沟槽内沉积第一隔离层104a，第一隔离层104a用于隔离栅极106与底部第一发射极105c和顶部第一发射极105b；沉积第二多晶硅层，所述第二多晶硅层覆盖所述第二沟槽并填满所述第二沟槽；在所述第二多晶硅层上形成图形化的光刻胶，所述图形化的光刻胶暴露出部分第二多晶硅层，刻蚀所述第二多晶硅层，以形成栅极106和顶部第一发射极105b；Next, forming the gate and at least one first emitter in the first trench includes: forming a first polysilicon layer in the first trench; forming a patterned polysilicon layer in the first polysilicon layer photoresist, and expose a part of the first polysilicon layer to be etched, etch a part of the first polysilicon layer to form a second trench, and simultaneously form two bottom first emitters 105c; The first isolation layer 104a is deposited in the second trench, the first isolation layer 104a is used to isolate the gate 106 from the bottom first emitter 105c and the top first emitter 105b; deposit a second polysilicon layer, the first Two polysilicon layers cover the second trench and fill up the second trench; a patterned photoresist is formed on the second polysilicon layer, and the patterned photoresist exposes Part of the second polysilicon layer, etching the second polysilicon layer to form the gate 106 and the top first emitter 105b;
在所述第一沟槽内形成至少一个第一发射极和栅极后，沉积第二栅氧化层，所述第二栅氧化层覆盖所述栅极和所述第一发射极。所述第二栅氧化层也用于隔离栅极106和顶部第一发射极105b。After forming at least one first emitter and a gate in the first trench, a second gate oxide layer is deposited, and the second gate oxide covers the gate and the first emitter. The second gate oxide is also used to isolate the gate 106 and the top first emitter 105b.
在本实施例中，第一沟槽内形成的第一发射极包括一个顶部第一发射极105b和两个底部第一发射极105c。两个底部第一发射极105c的纵截面形状均为矩形，顶部第一发射极105b的纵截面形状亦为矩形。In this embodiment, the first emitter formed in the first trench includes one top first emitter 105b and two bottom first emitters 105c. The vertical cross-sectional shapes of the two bottom first emitters 105c are both rectangular, and the vertical cross-sectional shape of the top first emitter 105b is also rectangular.
综上可见，在本发明实施例提供的一种IEGT结构及其制作方法，IEGT结构，包括衬底、漂移层、第一沟槽、第一发射极、栅极、体区、有源区以及第二发射极。所述衬底上形成有漂移层。第一沟槽形成于所述漂移层中。在所述第一沟槽内形成至少一个第一发射极和栅极，所述第一发射极与所述栅极在所述第一沟槽内呈左右分离结构，在所述漂移区中形成体区，在靠近栅极的一侧的所述体区内形成有源区，所述第二发射极与所述体区以及所述有源区电连接。通过在所述第一沟槽内形成至少一个第一发射极和栅极，减小了第一沟槽内的栅极与集电极接触面积，IEGT结构的米勒电容大幅降低，仿真结果显示，初始值只有传统IEGT的20％左右，第一沟槽内的至少一个第一发射极与第二发射极连接，一方面起到降低米勒电容减小了开关损耗，另 一方面，第一发射极可以作为场板，在不影响IEGT开启特性和关断特性，可以加速沟槽之间的区域耗尽，提升产品的耐压可靠性。To sum up, in the embodiment of the present invention, an IEGT structure and its manufacturing method are provided. The IEGT structure includes a substrate, a drift layer, a first trench, a first emitter, a gate, a body region, an active region and the second emitter. A drift layer is formed on the substrate. A first trench is formed in the drift layer. At least one first emitter and gate are formed in the first trench, the first emitter and the gate are in a left and right separation structure in the first trench, and formed in the drift region A body region, an active region is formed in the body region on a side close to the gate, and the second emitter is electrically connected to the body region and the active region. By forming at least one first emitter and gate in the first trench, the contact area between the gate and the collector in the first trench is reduced, and the Miller capacitance of the IEGT structure is greatly reduced. Simulation results show that, The initial value is only about 20% of the traditional IEGT. At least one first emitter in the first trench is connected to the second emitter. On the one hand, it reduces the Miller capacitance and reduces the switching loss. On the other hand, the first emitter The pole can be used as a field plate, without affecting the turn-on and turn-off characteristics of the IEGT, it can accelerate the depletion of the area between the trenches, and improve the withstand voltage reliability of the product.
上述描述仅是对本发明较佳实施例的描述，并非对本发明范围的任何限定，本发明领域的普通技术人员根据上述揭示内容做的任何变更、修饰，均属于权利要求书的保护范围。The above description is only a description of the preferred embodiments of the present invention, and does not limit the scope of the present invention. Any changes and modifications made by those of ordinary skill in the field of the present invention based on the above disclosures shall fall within the protection scope of the claims.

Claims (15)

  1. 一种IEGT结构，其特征在于，包括：A kind of IEGT structure is characterized in that, comprises:
    衬底和形成于所述衬底上的漂移层；a substrate and a drift layer formed on the substrate;
    第一沟槽，形成于所述漂移层中；a first trench formed in the drift layer;
    栅极和至少一个第一发射极，形成于所述第一沟槽中，所述第一发射极与所述栅极之间通过第一隔离层形成左右分离结构；The gate and at least one first emitter are formed in the first trench, and a left and right separation structure is formed between the first emitter and the gate through a first isolation layer;
    体区，形成于所述第一沟槽的两侧的漂移层中；a body region formed in the drift layer on both sides of the first trench;
    有源区，形成于所述第一沟槽靠近所述栅极一侧的体区中；以及，an active region formed in a body region on a side of the first trench close to the gate; and,
    第二发射极，形成于所述体区上，并与所述体区和所述有源区电连接。The second emitter is formed on the body region and is electrically connected with the body region and the active region.
  2. 如权利要求1所述的IEGT结构，其特征在于，所述栅极的纵向长度大于所述体区的结深。The IEGT structure according to claim 1, wherein the vertical length of the gate is greater than the junction depth of the body region.
  3. 如权利要求1所述的IEGT结构，其特征在于，每个所述第一沟槽中形成至少一个第一发射极，并在所述栅极的一侧和底部呈半包围分布。The IEGT structure according to claim 1, wherein at least one first emitter is formed in each of the first trenches, and is half-surrounded on one side and the bottom of the gate.
  4. 如权利要求3所述的IEGT结构，其特征在于，所述第一发射极为一整体时，呈L型将所述栅极的一侧和底部包围；所述第一发射极为多个时，若干所述第一发射极均匀分布于所述栅极的一侧和底部，呈半包围状。The IEGT structure according to claim 3, wherein when the first emitter is integrated, it is L-shaped and surrounds one side and the bottom of the grid; when there are multiple first emitters, several The first emitters are evenly distributed on one side and the bottom of the gate, in a semi-enclosed shape.
  5. 如权利要求1所述的IEGT结构，其特征在于，所述漂移层为第一导电类型的漂移层，且所述第一沟槽的底面高于所述漂移层的底面。The IEGT structure according to claim 1, wherein the drift layer is a drift layer of the first conductivity type, and the bottom surface of the first trench is higher than the bottom surface of the drift layer.
  6. 如权利要求1所述的IEGT结构，其特征在于，还包括形成于所述第一沟槽中的栅氧化层，所述栅氧化层覆盖所述第一沟槽的侧壁和底面。The IEGT structure according to claim 1, further comprising a gate oxide layer formed in the first trench, the gate oxide layer covering sidewalls and bottom surfaces of the first trench.
  7. 如权利要求1所述的IEGT结构，其特征在于，还包括第二隔离层，所述第二隔离层形成于所述衬底上。The IEGT structure according to claim 1, further comprising a second isolation layer formed on the substrate.
  8. 如权利要求1所述的IEGT结构，其特征在于，还包括第二导电类型的集电极，所述第二导电类型的集电极形成于所述衬底的底面上。The IEGT structure according to claim 1, further comprising a collector electrode of a second conductivity type, and the collector electrode of the second conductivity type is formed on the bottom surface of the substrate.
  9. 一种IEGT结构的制作方法，其特征在于，包括：A method for making an IEGT structure, characterized in that it comprises:
    提供一衬底，所述衬底上形成有漂移层；providing a substrate on which a drift layer is formed;
    在所述漂移区中形成第一沟槽；forming a first trench in the drift region;
    在所述第一沟槽内形成栅极以及至少一个第一发射极，所述第一发射极和所述栅极通过第一隔离层形成左右分离结构；A gate and at least one first emitter are formed in the first trench, and the first emitter and the gate form a left and right separation structure through a first isolation layer;
    在所述第一沟槽的两侧的漂移区中形成体区；forming body regions in drift regions on both sides of the first trench;
    在所述第一沟槽靠近所述栅极的一侧的体区中形成有源区；以及，forming an active region in a body region of a side of the first trench close to the gate; and,
    在所述体区上形成第二发射极，所述第二发射极与所述体区和所述有源区电连接。A second emitter is formed on the body region, the second emitter is electrically connected to the body region and the active region.
  10. 如权利要求9所述的IEGT结构的制作方法，其特征在于，在所述第一沟槽内形成栅极以及至少一个第一发射极的步骤包括：The method for manufacturing an IEGT structure according to claim 9, wherein the step of forming a gate and at least one first emitter in the first trench comprises:
    在所述第一沟槽中形成第一多晶硅层；forming a first polysilicon layer in the first trench;
    刻蚀部分第一多晶硅层以形成第二沟槽，同时形成第一发射极；Etching part of the first polysilicon layer to form a second trench, and simultaneously forming a first emitter;
    在所述第二沟槽中形成所述第一隔离层；forming the first isolation layer in the second trench;
    形成第二多晶硅层，所述第二多晶硅层覆盖所述第二沟槽并填满所述第二沟槽以形成所述栅极。A second polysilicon layer is formed, the second polysilicon layer covers and fills up the second trench to form the gate.
  11. 如权利要求9所述的IEGT结构的制作方法，其特征在于，在所述第一沟槽内形成栅极以及至少一个第一发射极的步骤包括：The method for manufacturing an IEGT structure according to claim 9, wherein the step of forming a gate and at least one first emitter in the first trench comprises:
    在所述第一沟槽中形成第一多晶硅层；forming a first polysilicon layer in the first trench;
    刻蚀部分第一多晶硅层以形成第二沟槽，同时形成一部分的第一发射极；etching a part of the first polysilicon layer to form a second trench, and simultaneously forming a part of the first emitter;
    在所述第二沟槽中形成第一隔离层；forming a first isolation layer in the second trench;
    形成第二多晶硅层，所述第二多晶硅层覆盖所述第二沟槽并填满所述第二沟槽；forming a second polysilicon layer, the second polysilicon layer covering the second trench and filling the second trench;
    刻蚀所述第二多晶硅层以形成所述栅极和另一部分的第一发射极。Etching the second polysilicon layer to form the gate and another part of the first emitter.
  12. 如权利要求9所述的IEGT结构的制作方法，其特征在于，在所述第一沟槽内形成栅极以及至少一个第一发射极的步骤包括：The method for manufacturing an IEGT structure according to claim 9, wherein the step of forming a gate and at least one first emitter in the first trench comprises:
    在所述第一沟槽内形成栅氧化层，所述栅氧化层至少填充所述第一沟槽的三分之一的高度；forming a gate oxide layer in the first trench, the gate oxide layer filling at least one third of the height of the first trench;
    在所述栅氧化层中形成第二沟槽，所述第二沟槽为倒三角形；forming a second trench in the gate oxide layer, the second trench being an inverted triangle;
    形成第一多晶硅层，所述第一多晶硅层覆盖所述第二沟槽；forming a first polysilicon layer, the first polysilicon layer covering the second trench;
    刻蚀部分第一多晶硅层以形成第三沟槽，同时形成一部分的第一发射极；Etching part of the first polysilicon layer to form a third trench, and simultaneously forming a part of the first emitter;
    在所述第三沟槽内形成第一隔离层；forming a first isolation layer in the third trench;
    形成第二多晶硅层，所述第二多晶硅层覆盖所述第三沟槽并填满所述第三沟槽；forming a second polysilicon layer, the second polysilicon layer covering the third trench and filling the third trench;
    刻蚀所述第二多晶硅层，以形成所述栅极和另一部分的第一发射极；etching the second polysilicon layer to form the gate and another part of the first emitter;
    其中，所述第一发射极的形状为倒三角形。Wherein, the shape of the first emitter is an inverted triangle.
  13. 如权利要求9所述的IEGT结构的制作方法，其特征在于，在所述第一沟槽内形成栅极以及至少一个第一发射极的步骤包括：The method for manufacturing an IEGT structure according to claim 9, wherein the step of forming a gate and at least one first emitter in the first trench comprises:
    在所述第一沟槽中形成第一多晶硅层；forming a first polysilicon layer in the first trench;
    刻蚀部分第一多晶硅层以形成第二沟槽，同时形成一部分的第一发射极；etching a part of the first polysilicon layer to form a second trench, and simultaneously forming a part of the first emitter;
    在所述第二沟槽中形成第一隔离层；forming a first isolation layer in the second trench;
    形成第二多晶硅层，所述第二多晶硅层覆盖所述第二沟槽并填满所述第二沟槽；forming a second polysilicon layer, the second polysilicon layer covering the second trench and filling the second trench;
    刻蚀所述第二多晶硅层，以形成栅极和另一部分的第一发射极。Etching the second polysilicon layer to form the gate and another part of the first emitter.
  14. 如权利要求9所述的IEGT结构的制作方法，其特征在于，在所述第一沟槽的一侧的所述体区上形成所述有源区后，形成第二隔离层，所述第二隔离层覆盖所述有源区、所述第一沟槽和所述体区。The method for manufacturing an IEGT structure according to claim 9, wherein after forming the active region on the body region on one side of the first trench, a second isolation layer is formed, and the first Two isolation layers cover the active region, the first trench and the body region.
  15. 如权利要求14所述的IEGT结构的制作方法，其特征在于，在形成第二发射极之前，刻蚀所述第二隔离层和所述有源区以形成接触孔。The method for fabricating an IEGT structure according to claim 14, wherein, before forming the second emitter, etching the second isolation layer and the active region to form a contact hole.
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