CN116632059B

CN116632059B - IGBT chip with emitter extending into substrate groove

Info

Publication number: CN116632059B
Application number: CN202310870552.7A
Authority: CN
Inventors: 杨鑫; 徐思维
Original assignee: Hunan University
Current assignee: Hunan University
Priority date: 2023-07-17
Filing date: 2023-07-17
Publication date: 2024-04-12
Anticipated expiration: 2043-07-17
Also published as: CN116632059A

Abstract

The invention provides an IGBT chip with an emitter extending into a substrate groove, which comprises a cell with an N-type substrate and an emitter metal structure; the N-type substrates of the cells are connected with each other to form an integrated structure, and the emitter metal structures of the cells are connected with each other to form an emitter of the IGBT chip; the first structure of the cell is provided with a first groove arranged on the N-type substrate, the joint of the two first structures is provided with a second groove arranged on the N-type substrate, and the first groove and the second groove extend downwards into the N-type substrate along the height direction of the IGBT chip; the first structure comprises a first grid electrode and a first active region; at least part of the first grid electrode stretches into the first groove; the first active region is arranged between the first groove and the second groove; at least part of the emitter metal structure extends into the second groove; the bottom end of at least part of the emitter metal structure is located at a lower height than the bottom end of at least part of the first gate.

Description

IGBT chip with emitter extending into substrate groove

Technical Field

The invention relates to the technical field of semiconductor devices, in particular to an IGBT chip with an emitter extending into a substrate groove.

Background

Low on-voltage drop, low switching loss, low EMI, and high reliability are the current trends of IGBT technology.

Fig. 1 is a test circuit of an IGBT chip in the prior art, where a collector of the IGBT chip is connected to an emitter through a parasitic inductance Ls, an external load R1, a dc power supply Vcc, and a parasitic inductance Le in sequence. When the external load R1 cannot perform voltage division due to short circuit caused by faults (i.e., short circuit faults or short circuit working conditions), the parasitic inductances Le and Ls do not block direct current, so that the voltage of the direct current power supply Vcc is directly applied to two ends of the IGBT chip, which results in an increase in the voltage born by the IGBT chip and a consequent increase in current, i.e., the IGBT chip bears a larger voltage and a larger current (the current value during short circuit is about 4-5 times that under normal working conditions) during short circuit faults, thereby resulting in failure of the IGBT short circuit.

The traditional IGBT with the planar gate structure has the advantages of simple manufacturing process and good voltage resistance, but the conductivity modulation effect is weaker and the conduction voltage drop is higher due to the fact that the channel region is arranged on the surface and the channel density is limited. The groove gate structure can eliminate JFET effect, improve channel density and reduce on-voltage drop, but the increase of the number of cells leads to overlarge saturation current of a chip and poor short-circuit fault resistance (or short-circuit working condition), meanwhile, the enhancement of the electric conduction modulation effect also increases turn-off time and loss, the electric field at the bottom of the groove gate is higher, and the device is easy to break down near the bottom of the groove gate. In order to improve the performance of the planar gate structure, a planar gate structure (TP-IGBT) with a trench is proposed, a shallow trench is introduced on the basis of the planar gate, the advantages of the planar gate and the trench gate can be combined, a carrier accumulation layer is formed on the side wall of the trench, the conductivity modulation effect is enhanced, the on-state loss of the device is reduced on the premise of not reducing the breakdown voltage, however, the introduction of the trench increases the capacitance between the gate and the emitter, and the switching time and the switching loss are increased.

In order to achieve low loss, some new composite gate structures have been proposed in recent years. Single channel structures as proposed in patent application CN104051509B, varying gate types, trench sides are used for carrier accumulation to reduce the on-voltage drop, but only one channel. In addition, there are applications for fusing a planar gate and a trench gate structure chip, so that the advantages of the trench gate and the planar gate are integrated, but the gate capacitance is increased, the switching loss is increased, and the electric field concentration is easily formed at the bottom of the trench, especially, the problem that the temperature of the trench gate is easily increased when a short circuit fault (namely, the external load R1 is short-circuited) is caused, and further, the IGBT chip is easily failed quickly.

Disclosure of Invention

The invention aims to solve the problems that an IGBT chip with a trench gate structure in the prior art is easy to form electric field concentration at the bottom of a trench, so that the temperature near the bottom of the trench gate is easy to rise and the IGBT chip is easy to fail when an external resistor is in short circuit fault, and provides the IGBT chip with an emitter extending into a substrate groove.

In order to solve the technical problems, the invention adopts the following technical scheme: an IGBT chip with an emitter extending into a substrate groove comprises a cell with an N-type substrate and an emitter metal structure, wherein the cell is formed by two first structures which are symmetrically arranged and connected with each other; the N-type substrates of the cells are connected with each other to form an integrated structure, and the emitter metal structures of the cells are connected with each other to form an emitter of the IGBT chip; the first structure is provided with a first grid electrode, a first active region and a first groove formed on the N-type substrate; the first groove extends downwards into the N-type substrate along the height direction of the IGBT chip; at least part of the first grid electrode stretches into the first groove.

The joint of the two first structures of the cell is provided with a second groove formed on the N-type substrate, and a first active area corresponding to the first structure is arranged between the second groove and the first groove corresponding to the first structure; and the second groove extends downwards into the N-type substrate along the height direction of the IGBT chip.

At least part of the emitter metal structure extends into the second groove; the bottom end of at least part of the emitter metal structure is located at a height position lower than that of at least part of the first grid electrode.

According to the arrangement, at least part of the first grid electrode stretches into the first groove so as to form the groove grid electrode, and the second groove is arranged between the two groove grid electrodes of one unit cell, and at least part of the emitter electrode metal structure stretches into the second groove, so that an electric field at the bottom of the groove can be weakened, the blocking characteristic of the device is enhanced, and the static avalanche robustness of the device is improved.

In the above technical scheme, the first active region includes a first n+ doped region, a first P-well region, and a first N-well region, which are sequentially disposed from top to bottom in the height direction of the IGBT chip.

And a side wall surface of the first N+ doped region, a side wall surface of the first P well region and a side wall surface of the first N well region form the first groove wall surface.

The second groove wall surface is formed by the other side wall surface of the first N+ doped region, the other side wall surface of the first P well region and the other side wall surface of the first N well region.

In the above technical solution, the bottom end of the first N-well region is at a height position not lower than the height position of at least part of the bottom end of the first gate.

According to the arrangement, the depth of the N well region does not exceed the depth of the bottom end of the first grid electrode in the groove, so that the risk of premature breakdown can be reduced.

In the above technical scheme, the emitter metal structure comprises a first extension section located on the N-type substrate, a second extension section extending downwards into the second groove along the height direction of the IGBT chip, and a first connection section connecting the first extension section and the second extension section.

The extending direction of the first extending section and the extending direction of the second extending section are mutually perpendicular.

The first connecting section is arranged on the upper surfaces of the two first P well regions corresponding to the two first structures of the cell respectively, and the first connecting section is arranged between the two first N+ doped regions corresponding to the two first structures of the cell respectively.

According to the arrangement, the width of the first N+ doped region is smaller than that of the first P well region, so that latch-up effect is avoided as much as possible.

In the above technical scheme, the thickness of the oxide layer arranged between the emitter metal structure and the inner wall of the second groove is greater than the thickness of the oxide layer arranged between the first grid and the inner wall of the first groove.

According to the above arrangement, the risk of premature breakdown can be reduced.

In the technical scheme, in the height direction of the IGBT chip, the height difference between the bottom end of at least part of the emitter metal structure and the upper end surface of the N-type substrate is 8 mu m-14 mu m.

According to the arrangement, the bottoms of the grooves (the first groove and the second groove) can bear a large electric field, the electric field concentration phenomenon at the bottoms of the grid grooves (namely the first groove) is relieved, the electric field at the bottoms of the first groove is weakened in a short-circuit working condition (external resistor short-circuit fault), the temperature rise of a device in the short-circuit working condition is weakened, particularly, the situation that the temperature near the grid of the groove is too high is avoided, the failure time of an IGBT chip is delayed, and the short-circuit fault resistance of the device is enhanced.

In the above technical scheme, a second P-well region and a second N-well region are arranged on one side of the first groove away from the second groove; the second P well region and the second N well region are formed in the N type substrate, and the second P well region is located on the second N well region.

In the above technical solution, the first structure further includes a second gate and a second active region that are correspondingly disposed; the second grid electrode is positioned on the N-type substrate, and the second active region is arranged on one side of the first groove far away from the second groove; the first grid electrode and the second grid electrode are separated by an oxide layer, or the first grid electrode and the second grid electrode are connected with each other to form an integrated structure.

According to the arrangement, when the first grid electrode and the second grid electrode are separated by the oxide layer, namely the first grid electrode and the second grid electrode are arranged at intervals, two independent driving grid electrodes (namely the first grid electrode and the second grid electrode) can be arranged on one IGBT chip, double independent channels in the longitudinal and transverse directions are formed, the chip can be driven by applying a plurality of voltages at the same time, the voltage driving capability of the chip is greatly enhanced, the switching delay increased by introducing grooves is reduced, the switching speed of the chip is improved, and the switching loss is greatly reduced. The two gate drive signals act simultaneously, so that the switching loss of the device can be reduced.

In the above technical solution, the second active region includes a second n+ doped region and a metal layer that are adjacently disposed; the metal layer is positioned on one side of the second N+ doped region, which is far away from the first grid electrode.

The second active region further comprises a second P well region and a second N well region.

The second N well region and the second P well region are both formed in the N-type substrate, the second P well region is located on the second N well region, the second N+ doped region and the metal layer are located on the second P well region, the second P well region is wound on the outer sides of the second N+ doped region and the metal layer, and the second N well region is wound on the outer side of the second P well region.

The upper end face of the second N+ doped region, the upper end face of the second P well region and the upper end face of the second N well region are all arranged towards the second grid electrode.

The emitter metal structure comprises the metal layer, and the metal layer and at least part of the emitter metal structure are connected with each other, so that a structure covering the second grid electrode is formed.

Based on the technical scheme, the IGBT chip with the emitter extending into the substrate groove has the following beneficial effects:

1) According to the IGBT chip structure, the second grooves are arranged between the first grooves, and the emitter metal structure is enabled to extend into the second grooves, so that the electric field at the bottom of the first grooves is weakened, the blocking characteristic of the device is enhanced, and the static avalanche robustness of the device is improved on the basis that the original conducting characteristic of the device is not changed;

2) The IGBT chip structure provided by the invention improves the firmness and reliability of the device, inhibits the temperature rising speed near the first grid electrode in the first groove during the short-circuit fault of the IGBT chip, increases the short-circuit tolerance time of the device, and improves the short-circuit fault resistance capability of the device.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the description of the embodiments will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort to a person skilled in the art.

Fig. 1 is a test circuit of an IGBT chip in the prior art.

Fig. 2 is a cross-sectional view of a cell of an IGBT structure according to embodiment 1 of the invention.

Fig. 3 is an enlarged schematic view of the M structure of fig. 2.

Fig. 4 and 5 are schematic diagrams of absolute values of electric field intensity when the collector voltage is 2000V, respectively corresponding to a conventional composite gate structure and a structure according to embodiment 1 of the present invention.

Fig. 6 is a schematic diagram showing the comparison of electric field intensity curves of the dashed line positions in fig. 4 and 5 according to the depth.

Fig. 7 is a graph showing the effect of the depth of the bottom end of the emitter metal structure on the breakdown voltage of the device in embodiment 1 of the present invention.

Fig. 8 and 9 correspond to temperature distribution diagrams of a conventional composite gate structure and the structure of embodiment 1 of the present invention when the structure lasts for 8 mus under a short-circuit condition, respectively.

Fig. 10 is a graph showing the collector current density as a function of the duration of the short circuit condition for the structure of example 1 of the present invention and the conventional composite gate structure.

Fig. 11 is a cell cross-sectional view of an IGBT chip structure according to embodiment 2 of the invention.

Fig. 12 is a cell cross-sectional view of an IGBT chip structure according to embodiment 3 of the invention.

In the above figures: 1. a first active region; 11. a first n+ doped region; 12. a first P well region; 13. a first N-well region; 2. a second active region; 21. a second n+ doped region; 22. a second P well region; 23. a second N-well region; 3. a first groove; 4. a second groove; 5. an N-type substrate; 6. an N-type buffer region; 7. a P-type collector region; 801. a first oxide layer; 802. a second oxide layer; 803. a third oxide layer; 804. a fourth oxide layer; 805. a fifth oxide layer; 10. a first gate; 20. a second gate; 30. an emitter metal structure; 301. a first extension; 302. a second extension; 303. a first connection section; 304. a metal layer; 305. a second connection section; l1, symmetry line.

Detailed Description

The following description of the embodiments of the present application will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are only some, but not all, of the embodiments of the present application. All other embodiments, which can be made by one of ordinary skill in the art without undue burden from the present disclosure, are within the scope of the present disclosure.

Example 1

As shown in fig. 2 and 3, the present invention provides an IGBT chip with an emitter extending into a substrate recess, which includes a cell having an N-type substrate 5 and an emitter metal structure 30, wherein the cell is formed by two first structures which are symmetrically arranged and connected to each other; the N-type substrates 5 of the individual cells are connected to each other to form an integral structure, and the emitter metal structures 30 of the individual cells are connected to each other to form the emitters of the IGBT chips. In fig. 2, the symmetry line of the two first structures in the cross-sectional view is L1, i.e. two half cells are respectively located on the left and right sides of the symmetry line L1.

The first structure is provided with a first groove 3 formed on an N-type substrate 5, the joint of the two first structures of the cell is provided with a second groove 4 formed on the N-type substrate 5, and the first groove 3 and the second groove 4 extend into the N-type substrate 5 downwards along the height direction of the IGBT chip.

The first structure comprises a first gate 10 and a first active region 1; at least part of the first gate 10 extends into the first recess 3; the first active region 1 is arranged between the first groove 3 and the second groove 4.

At least part of the emitter metal structure 30 extends into the second recess 4; the bottom end of at least part of the emitter metal structure 30 is located at a lower height than the bottom end of at least part of the first gate 10.

By setting the height position of the bottom end of at least part of the emitter metal structure 30 lower than the height position of the bottom end of at least part of the first gate 10, the voltage born by the bottom of the first gate (i.e. the bottom of the first groove) is reduced, the electric field is weakened, and therefore the temperature near the bottom of the first gate is reduced, so that the short-circuit tolerance time is increased (i.e. the IGBT failure time is delayed when the external load R1 is shorted), and the firmness and reliability of the device are improved. Conversely, if the bottom end of at least part of the emitter metal structure 30 is located at a higher level than the bottom end of at least part of the first gate 10, the function of weakening the electric field at the bottom of the first gate (i.e. at the bottom of the first recess) cannot be performed, and the short-circuit tolerance time cannot be improved.

The first active region 1 comprises a first N+ doped region 11, a first P well region 12 and a first N well region 13 which are sequentially arranged from top to bottom in the height direction of the IGBT chip; a side wall surface of the first n+ doped region 11, a side wall surface of the first P-well region 12 and a side wall surface of the first N-well region 13 form a wall surface of the first groove 3; the other side wall surface of the first n+ doped region 11, the other side wall surface of the first P-well region 12, and the other side wall surface of the first N-well region 13 form the wall surface of the second groove 4.

The bottom end of the first N-well region 13 is at a height not lower than that of at least a portion of the bottom end of the first gate 10.

The emitter metal structure 30 comprises a first extension section 301 positioned on the N-type substrate 5, a second extension section 302 extending downwards into the second groove 4 along the height direction of the IGBT chip, and a first connection section 303 connecting the first extension section 301 and the second extension section 302; the extending direction of the first extending section 301 and the extending direction of the second extending section 302 are perpendicular to each other; the first connection section 303 is disposed on the upper surfaces of the two first P-well regions 12 corresponding to the two first structures of the cell, and the first connection section 303 is disposed between the two first n+ doped regions 11 corresponding to the two first structures of the cell.

The thickness of the oxide layer arranged between the emitter metal structure 30 and the inner wall of the second recess 4 is greater than the thickness of the oxide layer arranged between the first gate 10 and the inner wall of the first recess 3.

In the height direction of the IGBT chip, the height difference between the bottom end of at least part of the emitter metal structure 30 and the upper end surface of the N type substrate 5 is 8 μm-14 μm.

The first structure further comprises a second grid electrode 20 and a second active region 2 which are correspondingly arranged; the second gate 20 is located above the N-type substrate 5. The extending direction of the second gate 20 is perpendicular to the height direction of the IGBT chip. The second active region 2 is arranged on one side of the first groove 3 far away from the second groove 4; the first gate 10 and the second gate 20 are separated by an oxide layer, or the first gate 10 and the second gate 20 are connected to each other to form an integral structure.

The second active region 2 comprises a second n+ doped region 21 and a metal layer 304 which are adjacently arranged; the metal layer 304 is located at a side of the second n+ doped region 21 away from the first gate 10; the second active region 2 further comprises a second P-well region 22 and a second N-well region 23; the second N-well region 23 is formed in the N-type substrate 5, the second P-well region 22 is located on the second N-well region 23, the second n+ doped region 21 and the metal layer 304 are located on the second P-well region 22, the second P-well region 22 is wound around the outside of the second n+ doped region 21 and the metal layer 304, and the second N-well region 23 is wound around the outside of the second P-well region 22. The bottom ends of the metal layers 304 are located at the same height as the bottom ends of the first connecting sections 303.

The upper end surface of the second n+ doped region 21, the upper end surface of the second P-well region 22, and the upper end surface of the second N-well region 23 are all disposed towards the second gate 20. The upper end surface of the second n+ doped region 21, the upper end surface of the second P-well region 22, and the upper end surface of the second N-well region 23 may be flush with the upper end surface of the N-type substrate 5. The emitter metal structure 30 includes the metal layer 304, and the metal layer 304 is connected with at least a portion of the emitter metal structure 30, that is, the metal layer 304 is sequentially connected with the second extension segment 302 through the second connection segment 305, the first extension segment 301, and the first connection segment 303, so as to form a structure covering the second gate 20.

The thickness of the portion of the first oxide layer 801 between the first gate electrode 10 and the bottom of the first recess 3 is greater than the thickness of the portion of the first oxide layer 801 between the first gate electrode 10 and the sidewall of the first recess 3.

A second oxide layer 802 is disposed between the second gate 20 and the N-type substrate 5. The thickness of the portion of the first oxide layer between the first gate 10 and the sidewall of the first recess 3 may be equal to the thickness of the portion of the second oxide layer under the second gate.

In this embodiment, the first gate 10 may have an L-shaped structure, i.e. the L-shaped structure is formed by connecting horizontal extending sections and vertical extending sections extending into the grooves.

The following describes the present invention in further detail in example 1.

The invention provides a high-firmness composite gate IGBT structure with an emitter metal structure, which optimizes the electric field at the bottom of a groove (namely a first groove) of the composite gate IGBT structure under the condition of not affecting on-state characteristics, and simultaneously optimizes the temperature distribution during short circuit, improves the short circuit capacity and blocking voltage, and enhances the firmness of a device.

The invention comprises an N-type substrate and a plurality of parallel cell units formed on the front surface of the substrate, wherein the structure of each cell unit is shown in figure 2. The single cell structure includes: a P-type collector region 7 is implanted over the N-type substrate, an N-type buffer region 6 is located over the collector region, and an N-drift region (i.e., N-type substrate 5) is located over the N-type buffer region. The drift region is provided with a polysilicon gate and a first oxide layer 801, an emitter metal structure and an emitter oxide layer (i.e., a third oxide layer 803), and a channel doped region. The channel doped region is sequentially provided with an N+ doped region, a P well region and an N well region from top to bottom.

The portion of the second oxide layer 802 under the planar gate (i.e., the second gate) is the same thickness as the first oxide layer 801 on the trench gate (i.e., the first gate) sidewall. The thickness of the part of the first oxide layer at the bottom of the first gate is greater than that of the oxide layer on the side wall of the first gate. The first gate 10 and the second gate 20 may be polysilicon gates.

In this embodiment, the thickness of the third oxide layer 803 is greater than the thickness of the first oxide layer 801. In particular, the depth of the emitter metal structure bottom end (i.e., the second extension 302 bottom end) can withstand a maximum breakdown voltage at 12 μm.

In this embodiment, the second n+ doped region 21, the second P-well region 22 and the second N-well region 23 are located under the second gate 20 and are in contact with each other. Specifically, the second n+ doped region 21 is directly under the second gate 20 and forms an ohmic contact with the metal layer 304 in the emitter metal structure 30. The second P-well region 22 contacts the second oxide layer 802 under the second gate 20 and wraps the second n+ doped region 21, and the second N-well region 23 contacts the second oxide layer 802 under the second gate 20 and wraps the second P-well region 22. The channel doped region of the first gate 10 is sequentially downward distributed with the first n+ doped region 11, the first P-well region 12, and the first N-well region 13, and both end at the sidewall of the first recess 3 (i.e., at least part of the sidewall of the first recess 3 is formed by the first P-well region 12 and the first N-well region 13), and both contact with the third oxide layer 803. Wherein the depth of the bottom end of the second N-well region 23 does not exceed the depth of the first gate 10 to reduce the risk of premature breakdown.

The technical solution of the present invention is to add the second recess 4 and the oxide layer structure (i.e. the third oxide layer 803) surrounding the emitter metal structure in the second recess, compared to the already proposed composite gate structure. Wherein the thickness of the third oxide layer 803 is greater than the thickness of the first oxide layer 801. In the application, under the condition that the conduction voltage drop of the device is not changed, the bottom of the emitter metal structure bears a large electric field, the electric field concentration phenomenon of the bottom of the first groove for accommodating the first grid is relieved, the temperature rise condition of the groove side under the short-circuit working condition is weakened, and the short-circuit capability of the device is enhanced.

In this embodiment, simulation is performed under the condition that the voltage of the collector-emitter power supply (i.e., the dc power supply Vcc) is 2000V and the depth of the bottom end of the emitter metal structure is 11 μm, so as to obtain the electric field distribution at the bottom of the first groove in the existing composite gate structure, and the absolute value distribution of the electric field intensity at the bottom of the first groove in the structure of embodiment 1 of the present invention is shown in fig. 4 and 5. In fig. 4, the x1 axis of the abscissa indicates the coordinates of the half cell in the width direction (the width direction is equivalent to the transverse direction in fig. 2), the position of the x1 axis of the half cell having a coordinate of 30 μm indicates the position of one edge of the half cell in the width direction (i.e., the position of the boundary between two cells, refer to L1 in fig. 2), the position of the x1 axis of the half cell having a coordinate of 0 indicates the position of the other edge of the half cell in the width direction (i.e., the edge of the half cell far from the boundary between two cells in the width direction), the y1 axis of the ordinate indicates the coordinates of the IGBT chip in the height direction (i.e., the emitter bottom end is the 0 point coordinate on the y axis, the coordinate on the y1 axis indicates the distance between the position below the emitter bottom end and the emitter bottom end in the height direction of the IGBT chip), and the position of the emitter 30A in the conventional composite gate structure can refer to fig. 8. In fig. 4, the third gate 10A is a gate extending in the height direction of the IGBT chip and extending into the recess in the conventional composite gate structure. In fig. 5, the x-axis of the abscissa indicates the coordinates in the width direction of the half cell (width direction, i.e., the lateral direction in fig. 2), the position of 30 μm on the x-axis indicates the position of one edge of the half cell on the left side in the width direction (i.e., the position of L1 in fig. 2), the position of 0 on the x-axis indicates the position of the other edge of the half cell in the width direction (i.e., the left edge of the half cell on the left side in the width direction), the y-axis indicates the coordinates in the height direction of the IGBT chip (i.e., the position of the bottom end of the metal layer 304 is the 0-point coordinates on the y-axis), and the y-axis indicates the distance between the height direction of the IGBT chip and the position of the bottom end of the metal layer 304.

As can be seen from comparing the electric field intensity distribution in fig. 4 and fig. 5, in the embodiment of the present invention, the electric field at the bottom of the first groove is significantly weakened, and the peak value of the corresponding electric field is also significantly reduced.

In fig. 6, the dashed line curve is a schematic diagram of the electric field intensity of the dashed line position of fig. 4 with respect to the depth, and the solid line curve is a schematic diagram of the electric field intensity of the dashed line position of fig. 5 with respect to the depth. The coordinates of the position of the broken line on the x1 axis in fig. 4 are identical to the coordinates of the position of the broken line on the x axis in fig. 5. Since the y 1-axis coordinates in fig. 4 and the y-axis coordinates in fig. 5 coincide, the y 2-axis coordinates in fig. 6 are indicated by indicating the y 1-axis coordinates and the y-axis coordinates on the same coordinate axis. As shown in fig. 6, the peak value of the electric field at the bottom of the first recess is reduced by 2.59×10 compared with the composite gate structure where no second recess has been proposed ⁵ V/cm (0.259 MV/cm), blocking characteristics are also obviously improved, and compared with the proposed composite gate structure without the second groove, the breakdown voltage of the composite gate structure is increased by more than 400V.

In this embodiment, further, the depth of the bottom end of the emitter metal structure (i.e. the bottom end of the second extension section) is 8 μm-14 μm.

Fig. 7 is a graph showing the effect of the depth of the bottom end of the emitter metal structure (i.e., the distance between the bottom end of the second extension 302 and the upper end surface of the N-type substrate 5) on the breakdown voltage of the device. The applicant found during research that the larger the depth of the bottom end of the emitter metal structure is, the larger the breakdown voltage that the structure proposed in the scheme can withstand, specifically, when the height difference between the bottom end of the second extension section 302 and the upper end surface of the N-type substrate 5 is 12 μm, the maximum value of the breakdown voltage that can withstand is reached, and after the maximum depth is exceeded, the breakdown voltage decreases with the increase of the depth of the bottom end of the emitter metal structure. In contrast, when the second groove is not provided, the breakdown voltage that the IGBT chip can withstand is 6360V.

In this embodiment, the temperature distribution of the existing composite gate structure and the structure of embodiment 1 of the present invention when the voltage of the collector-emitter power supply (i.e., the dc power supply Vcc) is 2000V and the gate driving voltage Vgg is ±15v are obtained by simulation, and the temperature distribution is shown in fig. 8 and 9, respectively, under the short-circuit condition, when the temperature continues for 8 mus. The structure shown in fig. 8 corresponds to the structure shown in fig. 4 and has the same structure. The structures shown in fig. 9 and 5 are identical and correspond to the half-cell structure on the left side of L1 in fig. 2. In fig. 8, the fourth gate 20A is a gate located on the N-type substrate, and the third n+ doped region 11A is disposed corresponding to the third gate 10A. The third gate 10A and the fourth gate 20A form an integral structure. The third gate 10A and the fourth gate 20A in fig. 8 correspond to the first gate 10 and the second gate 20 in fig. 9, respectively. In contrast to the structure of fig. 9 of the present embodiment, in the prior art structure of fig. 8, no second recess is provided, i.e. the emitter does not protrude into the substrate recess.

As shown in fig. 8 and fig. 9, it is obvious that, under the same condition and the same short-circuit time, the temperature of the embodiment of the present invention is smaller, and compared with the temperature near the third gate 10A, the temperature near (especially below) the first gate 10 is greatly reduced, specifically, in a steady state condition, joule heat generated by the interaction of the current electric field in the device and the heat released by the carrier recombination cause a sharp rise of the temperature during the short-circuit. In this embodiment, the large electric field and the large current do not exist in the same region at the same time, and the short circuit lattice temperature of the corresponding region is also reduced.

In this embodiment, a test circuit as shown in fig. 1 is built. According to the test circuit, under the short-circuit working condition of the same collector-emitter power supply (namely, direct current power supply Vcc) voltage and driving voltage, compared with the composite gate structure in the prior art, as shown in FIG. 10, the embodiment of the invention has longer short-circuit tolerance time and enhances the short-circuit resistance of the device.

According to the high-firmness composite gate IGBT structure with the emitter metal structure, the emitter metal structure can be embedded into the composite gate structure under the condition that the cell size and the conduction voltage drop of a device are not changed, so that the bottom of the emitter metal structure bears a large electric field, and the phenomenon of electric field concentration at the bottom of a gate groove is relieved; the blocking characteristic of the device is enhanced, and the static avalanche robustness of the device is improved; the temperature rise of the groove side under the short-circuit working condition is weakened, and the short-circuit capability of the device is enhanced.

Example 2

Fig. 11 is a cross-sectional view of a cell of an IGBT structure according to embodiment 2 of the invention.

This embodiment 2 differs from embodiment 1 in that: the first gate 10 and the second gate 20 are independently disposed and separated by a fourth oxide layer 804. The fourth oxide layer 804 forms an integral structure with the oxide layer around the first gate 10 and the oxide layer around the second gate 20.

Example 3

Fig. 12 is a cell cross-sectional view of an IGBT structure according to embodiment 3 of the invention.

This embodiment 3 differs from embodiment 1 in that: only the first gate electrode 10 is provided, and the second gate electrode located above the N-type substrate 5 is not provided. Wherein, a second P-well region 22 and a second N-well region 23 are disposed on the side of the first groove 3 away from the second groove 4 (i.e., the side of the first gate 10 away from the second groove 4); the second P-well region 22, the second N-well region 23 are formed in the N-type substrate 5, and the second P-well region 22 is located on the second N-well region 23. In this embodiment, the first gate 10 may be a structure extending in the height direction of the IGBT chip.

A fifth oxide layer 805 is disposed under the first extension 301. The fifth oxide layer 805 is located between the first extension 301 and the second P-well region 22, and is located between the first extension 301 and the first n+ doped region 11.

It should be noted that, in the present specification, each embodiment is described in a progressive manner, and each embodiment is mainly described as different from other embodiments, and identical and similar parts between the embodiments are all enough to be referred to each other.

The foregoing describes the embodiments of the present invention in detail, but the description is only a preferred embodiment of the present invention and should not be construed as limiting the scope of the invention. All equivalent changes and modifications within the scope of the present invention are intended to be covered by the present invention. Modifications of the invention, which are various equivalents to the invention, will occur to those skilled in the art upon reading the invention, and are intended to be within the scope of the claims appended hereto. Embodiments of the invention and features of the embodiments may be combined with each other without conflict.

Claims

1. An IGBT chip with an emitter extending into a substrate groove comprises a cell with an N-type substrate (5) and an emitter metal structure (30), wherein the cell is formed by two first structures which are symmetrically arranged and connected with each other; the N-type substrates (5) of the cells are connected with each other to form an integral structure, and the emitter metal structures (30) of the cells are connected with each other to form the emitter of the IGBT chip; the first structure is provided with a first grid electrode (10), a first active region (1) and a first groove (3) formed on an N-type substrate (5); the first groove (3) extends downwards into the N-type substrate (5) along the height direction of the IGBT chip; at least part of the first grid electrode (10) extends into the first groove (3);

the method is characterized in that a second groove (4) formed on an N-type substrate (5) is formed at the joint of two first structures of the cell, and a first active area (1) corresponding to the first structure is arranged between the second groove (4) and a first groove (3) corresponding to the first structure; the second groove (4) extends downwards into the N-type substrate (5) along the height direction of the IGBT chip;

at least part of the emitter metal structure (30) extends into the second recess (4); -the bottom end of at least part of the emitter metal structure (30) is located at a lower height than the bottom end of at least part of the first gate (10); the height difference between the bottom end of at least part of the emitter metal structure (30) and the upper end surface of the N-type substrate (5) is 12 mu m;

the first active region (1) comprises a first N+ doped region (11), a first P well region (12) and a first N well region (13) which are sequentially arranged from top to bottom in the height direction of the IGBT chip;

a first groove (3) wall is formed on one side wall surface of the first N+ doped region (11), one side wall surface of the first P well region (12) and one side wall surface of the first N well region (13);

the other side wall surface of the first N+ doped region (11), the other side wall surface of the first P well region (12) and the other side wall surface of the first N well region (13) form the wall surface of the second groove (4);

the emitter metal structure (30) comprises a first extension section (301) positioned on the N-type substrate (5), a second extension section (302) downwards extending into the second groove (4) along the height direction of the IGBT chip, and a first connection section (303) connecting the first extension section (301) and the second extension section (302);

the extending direction of the first extending section (301) and the extending direction of the second extending section (302) are mutually perpendicular;

the first connection section (303) is arranged on the upper surfaces of the two first P well regions (12) corresponding to the two first structures of the cell respectively, and the first connection section (303) is arranged between the two first N+ doped regions (11) corresponding to the two first structures of the cell respectively.

2. The IGBT chip of claim 1, wherein the bottom end of the first N well region (13) is located at a height position not lower than the height position of at least part of the bottom end of the first gate (10).

3. The IGBT chip according to claim 1, characterized in that the thickness of the oxide layer arranged between the emitter metal structure (30) and the inner wall of the second recess (4) is larger than the thickness of the oxide layer arranged between the first gate (10) and the inner wall of the first recess (3).

4. An IGBT chip according to any one of claims 1-3, characterized in that the side of the first recess (3) remote from the second recess (4) is provided with a second P-well region (22), a second N-well region (23); the second P well region (22) and the second N well region (23) are formed in the N type substrate (5), and the second P well region (22) is located on the second N well region (23).

5. An IGBT chip according to any of claims 1-3, characterized in that the first structure further comprises a correspondingly arranged second gate (20), second active region (2);

the second grid electrode (20) is positioned on the N-type substrate (5), and the second active region (2) is arranged on one side of the first groove (3) far away from the second groove (4);

the first grid electrode (10) and the second grid electrode (20) are separated through an oxide layer, or the first grid electrode (10) and the second grid electrode (20) are connected with each other to form an integrated structure.

6. The IGBT chip according to claim 5, characterized in that the second active region (2) comprises a second n+ doped region (21), a metal layer (304) arranged adjacently; the metal layer (304) is positioned on one side of the second N+ doped region (21) away from the first grid electrode (10);

the second active region (2) further comprises a second P well region (22) and a second N well region (23);

the second N well region (23) and the second P well region (22) are formed in the N-type substrate (5), the second P well region (22) is positioned on the second N well region (23), the second N+ doped region (21) and the metal layer (304) are positioned on the second P well region (22), the second P well region (22) is wound outside the second N+ doped region (21) and the metal layer (304), and the second N well region (23) is wound outside the second P well region (22);

the upper end face of the second N+ doped region (21), the upper end face of the second P well region (22) and the upper end face of the second N well region (23) are all arranged towards the second grid electrode (20);

the emitter metal structure (30) comprises the metal layer (304), and the metal layer (304) is interconnected with at least a portion of the emitter metal structure (30) to form a structure covering the second gate (20).