CN108321192B - Bidirectional trench gate charge storage type IGBT and manufacturing method thereof - Google Patents
Bidirectional trench gate charge storage type IGBT and manufacturing method thereof Download PDFInfo
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- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
Abstract
A bidirectional trench gate charge storage type IGBT and a manufacturing method thereof belong to the technical field of power semiconductor devices. The depth of an emitter region extending along the top layer of a base region in a traditional bidirectional trench gate charge storage type IGBT structure is reduced, and a split trench gate structure is introduced, wherein the split trench gate structure comprises a gate electrode, gate dielectric layers on the periphery of the gate electrode, a split electrode which is located at the bottom of the gate electrode and connected through the gate dielectric layers, and split electrode dielectric layers on the periphery of the split electrode, and the split electrode and emitter metal are equipotential. The device structure provided by the invention improves the comprehensive performance of the device while realizing symmetrical forward/reverse conduction and turn-off characteristics, can avoid the limitation of doping concentration and thickness of a charge storage layer on the voltage resistance of the device, improves the compromise relationship between a short-circuit safe working area, temperature characteristics and forward conduction voltage drop Vceon and turn-off loss Eoff of the device, avoids the problems of current, voltage oscillation and EMI in the dynamic process of turning on the device, and improves the reliability of the device.
Description
Technical Field
The invention belongs to the technical field of power semiconductor devices, relates to an Insulated Gate Bipolar Transistor (IGBT), and particularly relates to a bidirectional trench gate charge storage type insulated gate bipolar transistor (Bi-directional CSTBT).
Background
An Insulated Gate Bipolar Transistor (IGBT) is a novel power electronic device that has been researched on the basis of the development of a power MOSFET and a power Bipolar Junction Transistor (BJT), and is equivalent to a MOSFET driven by a Bipolar Junction Transistor (BJT). IGBTs combine the advantages of power MOSFET structures and Bipolar Junction Transistor (BJT) structures: the power MOSFET has the advantages of easy driving, low input impedance and high switching speed, and also has the advantages of high on-state current density, low conduction voltage, low loss and good stability of a Bipolar Junction Transistor (BJT). Based on these excellent device characteristics, in recent years, IGBTs have become mainstream power devices widely used in medium and high voltage fields, such as electric vehicles, motor drives, grid-connected technologies, energy storage power stations, AC/DA conversion, variable frequency speed control, and the like.
Since the invention of the IGBT, people have been working on improving the comprehensive performance of the IGBT, and after thirty years of development, seven generations of IGBT structures are proposed in the industry to continuously improve the performance of the device. The first NPT type IGBT structure is also referred to as a symmetrical type IGBT structure, and both the forward blocking state and the reverse blocking state are mainly withstand voltage by the lightly doped N type drift region and thus have equal forward breakdown voltage and reverse breakdown voltage, but in order to ensure withstand voltage, the N type drift region needs to be low in doping concentration and large in thickness, which results in an increase in forward on voltage, deterioration in switching characteristics, and deterioration in the trade-off characteristics between forward on voltage and off loss. Later, the IGBT develops a structure with an FS layer, the doping concentration of the N-type FS layer is higher than that of the N-type drift region, the FS-IGBT structure has the thickness of the thinner drift region under the same withstand voltage capability, and the FS layer can bear partial blocking voltage after the drift region penetrates through, so that the conduction voltage drop of a device is reduced, and the switching speed of the device is improved; however, when the FS-IGBT structure is reverse voltage-resistant, the reverse voltage is mainly borne by the PN junction formed by the P-type collector region and the N-type FS layer, the reverse breakdown voltage is low, the performance of the device is reduced when reverse blocking is applied, and in an application occasion where the IGBT is required to have reverse resistance capability, a high-voltage diode has to be connected in series to realize the reverse voltage resistance, which increases the cost and reduces the performance and reliability of the system. A seventh generation IGBT structure, namely a trench gate charge storage type insulated gate bipolar transistor (CSTBT), is characterized in that a hole potential barrier is introduced below a P type base region by introducing an N type charge storage layer with higher doping concentration and certain thickness below the P type base region, so that the hole concentration of a device close to an emitter terminal is greatly improved, the electron concentration of the device is greatly increased according to the electric neutral requirement, the carrier concentration distribution of the whole N type drift region is improved, the conductivity modulation effect of the N type drift region is enhanced, and the IGBT obtains lower forward conduction voltage drop and better compromise relationship between the forward conduction voltage drop and turn-off loss. The higher the doping concentration of the N-type charge storage layer is, the greater the CSTBT conductivity modulation effect is improved, and the better the forward conduction characteristic of the device is.
Power conversion is a basic step in many power electronic applications and is one of the basic functions of power devices, which can perform AC-to-DC (AC-DC), DC-to-AC (DC-AC), DC-to-DC (DC-DC) and AC-to-AC (AC-AC) conversions depending on the load requirements. The conversion of AC-AC can adopt an indirect conversion mode, namely an AC-DC-AC mode, and also can adopt a direct conversion mode, namely an AC-AC mode. In a traditional AC-DC-AC indirect conversion system, a connection capacitor with a large capacitance value (voltage type conversion) or a connection inductor with a large inductance value (current type conversion) is needed to connect two relatively independent conversion systems, and the system is large in size and high in cost. In addition, the service life of the capacitor and the inductor is far lower than that of a power device, which seriously influences the reliability and the service life of the system. AC-AC direct conversion systems avoid the use of connecting capacitors or inductors in conventional AC-DC-AC systems, but require bidirectional switching capability of the power switch. Therefore, development of a bidirectional switch has been a research focus of an ac power converter, and a thyristor equipped with an external forced commutation circuit is used as an early bidirectional switch. The most widely used semiconductor device for the bidirectional switch is the IGBT at present. However, because the conventional IGBT has only the functions of unidirectional conduction and unidirectional blocking, in order to have the bidirectional conduction and bidirectional blocking function, the prior art has been developed to obtain an IGBT bidirectional switch, and the IGBT bidirectional switch has the following structural modes: diode bridge, common collector, and common emitter. With the advent of reverse blocking type IGBTs (RB-IGBTs), the bi-directional switch can be simplified to a simple anti-parallel structure, eliminating two fast recovery diodes, due to the greater ability of such devices to withstand reverse voltage. However, the above switch schemes all belong to combined switches, a large number of power chips are needed, the system cost is increased, in addition, a large number of wires are needed among the chips in the system, and the parasitic effect in the system is enhanced by a complex combination mode, so that the system reliability is influenced.
Under the background, in order to solve the above problems and achieve integration of products, bi-directional IGBT chips are developed by using a bonding technique or a double-sided photolithography method. With the development of silicon-silicon bonding technology, in recent years, two identical trench MOS structures are bonded back to successfully realize a bidirectional IGBT device on a single chip. The generation of the bidirectional IGBT greatly reduces the cost of the device and reduces the stray parameters of the circuit. Compared with the traditional unidirectional IGBT, the bidirectional IGBT can realize the symmetrical turn-on and turn-off characteristics of the forward IGBT and the reverse IGBT by controlling the forward gate voltage and the back gate voltage. As shown in fig. 1, a schematic structural diagram of a bidirectional CSTBT (Bi-directional CSTBT) is shown, in the structure, a front N-type charge storage layer 6 and a back N-type charge storage layer 26 with a doping concentration higher than that of an N-type drift region 9 are symmetrically adopted between a front P-type base region 5 and the N-type drift region 9 and between a back P-type base region 25 and the N-type drift region 9, so that compared with an NPT-type bidirectional IGBT structure, on one hand, the thickness of the N-type drift region is reduced due to the introduction of the structure, the resistance of the drift region is reduced, the forward conduction voltage drop is reduced, the switching speed is increased, and on the other hand, no matter whether the structure works in the forward direction or the reverse direction, the structure has a charge storage layer and an electric field; in addition, the structure adopts a trench gate IGBT structure to eliminate JFET area resistance of a planar gate IGBT structure, so that higher MOS channel density is obtained, and the characteristics of the device are obviously improved. For the structure shown in fig. 1, when the forward or reverse IGBT works, the front N-type charge storage layer 6 and the back N-type charge storage layer 26, which have higher doping concentration and a certain thickness and are used as carrier storage layers, greatly improve the carrier concentration distribution of the IGBT device near the emitter terminal, improve the conductivity modulation of the N-type drift region, improve the carrier concentration distribution of the whole N-type drift region, and make the IGBT obtain low forward conduction voltage drop and improved compromise of forward conduction voltage drop and turn-off loss. However, as the doping concentration and thickness of the front N-type charge storage layer 6 and the back N-type charge storage layer 26 are increased, the device breakdown voltage is significantly reduced during forward or reverse operation for the bidirectional CSTBT structure, which limits the doping concentration and thickness of the charge storage layer. In the prior art, in order to effectively shield the adverse effect of the above N-type charge storage layer and further obtain higher device withstand voltage, the following two methods are mainly adopted:
(1) deepening the depth of the trench gate, wherein the depth of the trench gate is generally larger than the junction depth of the N-type charge storage layer;
(2) and the width of the unit cell is reduced, namely the channel density of the MOS structure is improved to obtain the smallest trench gate spacing as possible.
However, the implementation of the above-mentioned means still has significant drawbacks: the implementation of the method (1) increases the gate-emitter capacitance and the gate-collector capacitance, and the switching process of the IGBT is essentially a process of charging/discharging the gate capacitance, so that the increase of the gate capacitance increases the charging/discharging time, and further decreases the switching speed. Therefore, the deep trench gate will reduce the switching speed of the device, increase the switching loss of the device, and affect the compromise characteristic of the conduction voltage drop and the switching loss of the device. On one hand, the implementation of the mode (2) can increase the grid capacitance of the device, so that the switching speed of the device is reduced, the switching loss is increased, and the compromise characteristic of the conduction voltage drop and the switching loss of the device is influenced; on the other hand, too high channel density will also result in increased saturation current density of the device, thus degrading the short-circuit safe operating area (SCSOA) of the device. In addition, the gate oxide layer used in the trench gate structure is usually formed in the trench by a thermal oxidation, which requires a smaller thickness of the entire gate oxide layer in order to ensure a certain threshold voltage. However, the size of the MOS capacitor in the device is inversely proportional to the thickness of the gate oxide layer, which results in a significant increase in the gate capacitance of the conventional CSTBT device, and in addition, the electric field concentration effect at the bottom of the trench also reduces the breakdown voltage of the device, resulting in poor reliability of the device.
Disclosure of Invention
In view of the above, the present invention aims to: aiming at the defects in the prior art, the invention provides a bidirectional trench gate charge storage type IGBT and a manufacturing method thereof, wherein the limitation of the doping concentration and thickness of a charge storage layer on the voltage resistance of a device is avoided by reducing the extending depth of an emission region along the top layer of the device and introducing a split trench gate structure, the short-circuit safe working region of the device is improved, the temperature characteristic is improved, the compromise relation between the forward conduction voltage drop Vceon and the turn-off loss Eoff of the device is improved, the problems of current, voltage oscillation and EMI in the dynamic turn-on process of the device are avoided, and the reliability of the device is improved.
In order to achieve the purpose, the invention adopts the following technical scheme:
in one aspect, the present invention provides a bidirectional trench gate charge storage type IGBT, of which half cells include MOS structures respectively disposed on the front and back sides of a first conductivity type semiconductor drift region 9; the method is characterized in that: the front MOS structure comprises a front emitter metal 1, a front isolation dielectric layer 2, a front split trench gate structure, a front first conduction type semiconductor emitter region 3, a front second conduction type semiconductor body contact region 4, a front second conduction type semiconductor base region 5 and a front first conduction type semiconductor charge storage layer 6; the back MOS structure comprises a back emitter metal 21, a back isolation dielectric layer 22, a back split trench gate structure, a back first conductive type semiconductor emitter region 23, a back second conductive type semiconductor body contact region 24, a back second conductive type semiconductor base region 25 and a back first conductive type semiconductor charge storage layer 26;
in the front-side MOS structure, a front-side first conduction type semiconductor charge storage layer 6 is positioned on the top layer of the front-side first conduction type semiconductor drift region 9; the front second conductive type semiconductor base region 5 is positioned on the top layer of the front first conductive type semiconductor charge storage layer 6; the front-surface second-conductivity-type semiconductor body contact region 4 and the front-surface first-conductivity-type semiconductor emitter region 3 are mutually independent and are arranged on the top layer of the front-surface second-conductivity-type semiconductor base region 5 in parallel; the top layer of the first conductive type semiconductor drift region 9 is also provided with a front split trench gate structure, and the front split trench gate structure comprises a front gate electrode 71, a front gate dielectric layer 72 on the periphery of the front gate electrode, a front split electrode 81 and a front split electrode dielectric layer 82 on the periphery of the front split electrode; the depth of the downward penetration of the front-side gate electrode 71 from the top layer of the device is less than the junction depth of the front-side first conduction type semiconductor charge storage layer 6, the extending directions of the front-side split electrode 81 and the front-side gate electrode 71 in the device are the same, the front-side split electrode 81 is positioned at the bottom of the front-side gate electrode 71, the front-side split electrode 81 is connected with the front-side gate electrode 71 through the front-side gate dielectric layer 72, and the depth of the downward penetration of the front-side split electrode 81 is greater than the junction depth of the front-side first conduction; the front-surface gate electrode 71 is connected with the front-surface first conduction type semiconductor emitter region 3, the front-surface second conduction type semiconductor base region 5 and the front-surface first conduction type semiconductor charge storage layer 6 through a front-surface gate dielectric layer 72; the front split electrode 81 is at least connected between the front first conduction type semiconductor charge storage layer 6 and the front first conduction type semiconductor drift region 9 through a front split electrode dielectric layer 82; the upper surfaces of the front gate electrode 71 and the front gate dielectric layer 72 on the peripheral side thereof are provided with a front isolation dielectric layer 2; the upper surfaces of the front side isolation dielectric layer 2, the front side first conduction type semiconductor emitting region 4 and the front side first conduction type semiconductor emitting region 3 are connected with the front side emitter metal 1; the back side MOS structure is the same as the front side MOS structure.
Further, the front side MOS structure and the back side MOS structure may be mirror-symmetric along the lateral centerline of the first conductivity type semiconductor drift region 9, or may be cross-symmetric along the lateral centerline of the first conductivity type semiconductor drift region 9, that is, the front side MOS structure and the back side MOS structure are centrosymmetric about the device center point.
Further, the split electrodes 81, 281 are equipotential with the emitter metals 1, 21.
Further, the split electrode 8, 281 extends along the top layer of the second conductivity type semiconductor drift region 9 to a depth greater than the depth of the gate electrode 71, 271 so that the split electrode 81, 281 is disposed half-way around the gate electrode 71, 271 and the gate dielectric layer 72, 272 on the peripheral side thereof, and the split electrode 81, 281 is connected to the gate electrode 71, 271 through the gate dielectric layer 72, 272, and at this time, the split electrode 81, 281 is connected to the first conductivity type semiconductor body contact region 4, 24 and the first conductivity type semiconductor base region 5, 25 through the split electrode dielectric layer 82, 282.
Further, the gate electrode 71, 271 extends along the top layer of the second conductivity type semiconductor drift region 9 to a depth equal to the extension depth of the split electrode 81, 281, and a part of the split electrode 81, 281 is located below the gate electrode 71, 271, and another part of the split electrode is located on the top layer of the device and connected to the gate electrode 71, 271 through the gate dielectric layer 72, 272, and the width of the gate electrode 71, 271 extending along the top layer of the device is smaller than the width of the split electrode 81, 281; at this time, the split electrodes 81, 281 are connected to the first conductivity type semiconductor body contact regions 4, 24 and the first conductivity type semiconductor base regions 5, 25 through the split electrode dielectric layers 82, 282; in one embodiment, the thickness of the split electrode dielectric layer 82, 282 is greater than the thickness of the gate dielectric layer 72, 272.
Further, the second conductivity type semiconductor emitter regions 3, 23 and the first conductivity type semiconductor body contact regions 4, 24 are located at the center of the top layer of the first conductivity type semiconductor base region 5, 25, the split electrodes 81, 281 are located below the gate electrodes 71, 271, and the thickness of the gate electrodes 71, 271 connected to the second conductivity type semiconductor emitter regions 3, 23 through the gate dielectric layers 72, 272 is larger than the thickness of the gate electrodes 71, 271 not connected to the second conductivity type semiconductor emitter regions 3, 23, i.e., the thickness of the gate dielectric layers 72, 272 in the middle portion of the top layer of the device is smaller than the thickness of the end portions thereof. Because the threshold voltage of the MOS structure is inversely proportional to the thickness of the oxide layer, under the same gate voltage condition, the central parts of the surfaces of the first conductive type semiconductor base regions 5 and 25 connected with the gate electrodes 71 and 271 through the gate dielectric layers 72 and 272 along the z-axis direction form inversion layers, and at the moment, the two end parts of the surfaces of the first conductive type semiconductor base regions 5 and 25 along the z-axis direction do not form the inversion layers, so that the channel density of the device is not increased, and the short-circuit safe working area characteristic of the device is not influenced.
Further, a front second conductive type semiconductor layer one 10 is arranged below the front split trench gate structure, and a back second conductive type semiconductor layer one 210 is arranged above the back split trench gate structure.
Preferably, the front second conductivity type semiconductor layer 10 or the back second conductivity type semiconductor layer 210 extends laterally into the first conductivity type semiconductor drift region 9 below the front first conductivity type semiconductor charge storage layer 6 or above the back first conductivity type semiconductor charge storage layer 26.
Further, the semiconductor material used by the device is any one or more of Si, SiC, GaAs and GaN, and the structures can adopt the same semiconductor material or different semiconductor materials.
Further, the gate electrode in the trench is any one or more of polysilicon, SiC, GaAs and GaN, and each portion can be made of the same material or different materials.
In all the above technical solutions, the first conductivity type semiconductor is a P-type semiconductor, and the second conductivity type semiconductor is an N-type semiconductor; or the first conductive type semiconductor is an N-type semiconductor and the second conductive type semiconductor is a P-type semiconductor.
On the other hand, the invention provides a preparation method of a bidirectional trench gate charge storage type IGBT, which is characterized by comprising the following steps:
the method comprises the following steps: manufacturing two identical first conduction type semiconductor drift regions 9;
step two: respectively manufacturing a first conductive type semiconductor charge storage layer 6 and a second conductive type semiconductor base region 5 positioned on the top layer of the first conductive type semiconductor charge storage layer 6 on the front surfaces of the two first conductive type semiconductor drift regions 9 by adopting the same pre-oxidation, photoetching, etching, ion implantation and high-temperature annealing processes;
step three: respectively etching two first conductive type semiconductor charge storage layers 6 to form first grooves by adopting the same photoetching, etching, thermal oxidation and deposition processes, wherein the depth of each first groove is greater than the junction depth of the first conductive type semiconductor charge storage layers 6; forming a split electrode dielectric layer 82 on the inner wall of the first groove, and then depositing an electrode material in the groove to form a split electrode 81;
step four: respectively etching two first conduction type semiconductor drift regions 9 to form second grooves by adopting the same photoetching, etching, thermal oxidation and deposition processes, wherein the depth of each second groove is less than the junction depth of the first conduction type semiconductor charge storage layer 6, and the first grooves and the second grooves are consistent along the extending direction of the top layer of the device; forming a gate dielectric layer 72 on the inner wall of the second trench, then depositing an electrode material in the second trench to form a gate electrode 71, wherein the gate electrode 71 and the gate dielectric layer 72 on the peripheral side thereof, the split electrode 81 and the split electrode dielectric layer 82 on the peripheral side thereof form a split trench gate structure;
step five: respectively manufacturing a second conductive type semiconductor body contact region 4 and a first conductive type semiconductor emitter region 3 which are mutually independent and arranged in parallel on the top layers of two second conductive type semiconductor base regions 5 by adopting the same photoetching, etching, ion implantation and high-temperature annealing processes; the extension depth of the first conductive type semiconductor emitter region 3 on the top layer of the second conductive type semiconductor base region 5 is smaller than the extension depth of the second conductive type semiconductor base region 5 on the top layer of the first conductive type semiconductor charge storage layer 6, and the first conductive type semiconductor emitter region 3 is arranged close to the gate electrode 71 and is connected with the gate electrode 71 through the gate dielectric layer 72;
step six: forming an isolation dielectric layer 2 on the upper surfaces of the gate electrode 71 and the gate dielectric layer 72 by adopting the same photoetching, etching and deposition processes;
step seven: depositing metal on the surface, and respectively forming emitter metal 1 on the isolation dielectric layer 2, the second conductive type semiconductor body contact area 4 and the upper surface of the first conductive type semiconductor emitter area 3 by adopting the same photoetching and etching processes;
step eight: and turning over the semiconductor device, thinning the thickness of the semiconductor by adopting the same process, and then forming the bidirectional trench gate charge storage type IGBT device by back-to-back bonding the two completely same semiconductor wafers by adopting a bonding process, thereby completing the preparation of the device.
Further, the order of the step of forming the first trench and the steps of forming the first conductivity type semiconductor charge storage layer 6 and the second conductivity type semiconductor base region 5 may be interchanged.
Further, the second conductivity type semiconductor body contact region 4 formed in the fifth step may be formed together or in two steps at the time of forming the second conductivity type semiconductor base region 5 in the second step.
Further, a structure is formed in which the first trench is disposed to semi-surround the second trench by controlling the depth to which the second trench extends along the top layer of the device to be less than the depth to which the first trench extends in the device.
Further, by controlling the groove depth of the second trench extending along the top layer of the device, the extension depth of the gate electrode 71 along the top layer of the device is formed to be equal to the extension depth of the split electrode 81, the extension width of the gate electrode 71 at two ends of the top layer of the device is smaller than the extension width of the split electrode 81, meanwhile, a part of the split electrode dielectric layer 82 and a part of the split electrode 81 structure are remained at the top layer of the device, and metal is deposited on the upper surface of the split electrode 81 in the following step seven.
Further, by controlling the width of the second trench extending along the top layer of the device, so that there is no split electrode 81 and split electrode dielectric layer 82 structure on the top layer of the device, the split electrode 81 and the split electrode dielectric layer 82 are located at the bottom of the gate electrode 71; and the thickness of the gate electrode 71 connected to the first conductive type semiconductor emitter region 3 through the gate dielectric layer 72 is greater than the thickness of the gate electrode 71 not connected to the first conductive type semiconductor emitter region 3.
The device structure provided by the invention can realize symmetrical forward/reverse conduction and turn-off characteristics, simultaneously improves the comprehensive performance of the device and the reliability of the device, and the principle of the device design is elaborated in the following:
the invention achieves the purpose of reducing the channel density of an MOS structure by reducing the extension depth of an emitter region along the top layer of a base region, along with the reduction of the extension depth of the emitter region along the top layer of the base region, the depth of a gate electrode which is connected with the emitter region through a gate dielectric layer and extends in the same direction can be reduced, thereby not only reducing the saturation current density and improving the SCSOA of a safe working region of a device, but also improving the uniformity of conduction current, further improving the reliability of the device and improving the temperature characteristic of the device, and the reduction of the extension depth of the gate electrode along the top layer of a drift region and along the vertical direction of the device is also beneficial to the reduction of gate capacitance, particularly the gate-collector capacitance, thereby improving the switching speed of the device, reducing the switching loss of the device and the requirements on the capability of a gate driving circuit, and improving the forward conduction voltageoffA compromise relationship between; meanwhile, the split trench gate structure is adopted, the introduced split electrodes can play an effective charge compensation role on the charge storage layer, an electric field of the charge storage layer is effectively shielded, the limit of doping concentration and thickness of the charge storage layer on the withstand voltage of the device is avoided, and then the carrier concentration distribution of the drift region of the device is obviously improved, so that the forward conduction voltage drop Vceon and the turn-off loss E of the device are improvedoffThe compromise relationship between the two enables the device to obtain a wider short circuit safe working area SCSOA; in addition, the introduced split electrode and the emitting electrode are equipotential, so that an accumulation layer or an inversion layer cannot be formed on the surface of a semiconductor connected with the split electrode through a split electrode dielectric layer in the dynamic starting process of the device, the negative differential capacitance effect of the device in the dynamic starting process is avoided, the problems of current, voltage oscillation and EMI (electro-magnetic interference) in the dynamic starting process of the device are avoided, and the reliability of the device is improved. The device manufacturing method provided by the invention does not need to add extra process steps and is compatible with the traditional bidirectional trench gate charge storage type IGBT manufacturing method.
The invention has the beneficial effects that:
the invention reduces the channel density of the MOS structure, improves the uniformity of the conduction current of the device, reduces the saturation current density of the device and improves the short-circuit safe working area of the device while realizing the symmetrical forward/reverse conduction and turn-off characteristics of the device; the electric field of the N-type charge storage layer is shielded, the limitation of the doping concentration and thickness of the N-type charge storage layer on the voltage resistance of the device is avoided, and the carrier concentration distribution of the drift region of the device and the compromise relationship between the forward conduction voltage drop Vceon and the turn-off loss Eoff of the device are improved; the switching speed of the device is improved, and the switching loss of the device and the requirement on the capacity of a gate driving circuit are reduced; the problems of negative differential capacitance effect of the device in the dynamic starting process and current, voltage oscillation and EMI in the dynamic starting process of the device are avoided; the electric field concentration effect at the bottom of the groove is improved, and the breakdown voltage of the device is improved. The manufacturing method provided by the invention does not need to add extra process steps and is compatible with the manufacturing method of the traditional bidirectional trench gate charge storage type IGBT.
Drawings
FIG. 1 is a schematic diagram of a half-cell structure of a conventional bidirectional trench gate charge storage type IGBT device;
FIG. 2 is a schematic diagram of a half cellular structure before forming an isolation dielectric layer and an emitter metal in a conventional bidirectional trench gate charge storage type IGBT device;
FIG. 3 is a schematic cross-sectional view of a half-cell structure of a conventional bi-directional trench gate charge storage type IGBT device along line AB;
fig. 4 is a schematic structural diagram of a half cell of a bidirectional trench gate charge storage type IGBT device according to embodiment 1 of the present invention;
fig. 5 is a schematic structural diagram of a half cell of a bidirectional trench gate charge storage type IGBT device provided in embodiment 1 of the present invention before an isolation dielectric layer and an emitter metal are not formed;
fig. 6 is a schematic cross-sectional view of a half cell structure of a bidirectional trench gate charge storage type IGBT device according to embodiment 1 of the present invention along line AB;
fig. 7 is a schematic cross-sectional view of a half cell structure of a bidirectional trench gate charge storage type IGBT device according to embodiment 1 of the present invention, along the CD line;
fig. 8 is a schematic structural diagram of a half cell of a bidirectional trench gate charge storage type IGBT device according to embodiment 2 of the present invention;
fig. 9 is a schematic structural diagram of a half cell of a bidirectional trench gate charge storage type IGBT device provided in embodiment 2 of the present invention before forming an isolation dielectric layer and an emitter metal;
fig. 10 is a schematic cross-sectional view of a half cell structure of a bidirectional trench gate charge storage type IGBT device according to embodiment 2 of the present invention along line AB;
fig. 11 is a schematic cross-sectional view of a half cell structure of a bidirectional trench gate charge storage type IGBT device according to embodiment 2 of the present invention, along the CD line;
fig. 12 is a schematic cross-sectional view of a half cell structure of a bidirectional trench gate charge storage type IGBT device according to embodiment 2 of the present invention along the EF line;
fig. 13 is a schematic cross-sectional view of a half cell structure of a bidirectional trench gate charge storage type IGBT device according to embodiment 2 of the present invention, along a GH line;
fig. 14 is a schematic structural diagram of a half cell of a bidirectional trench gate charge storage type IGBT device according to embodiment 3 of the present invention;
fig. 15 is a schematic structural diagram of a half cell before forming an isolation dielectric layer and an emitter metal in a bidirectional trench gate charge storage type IGBT device according to embodiment 3 of the present invention;
fig. 16 is a schematic cross-sectional view of a half cell structure of a bidirectional trench gate charge storage type IGBT device according to embodiment 3 of the present invention along line AB;
fig. 17 is a schematic cross-sectional view of a half cell structure of a bidirectional trench gate charge storage type IGBT device according to embodiment 3 of the present invention, taken along the CD line;
fig. 18 is a schematic cross-sectional view of a half cell structure of a bidirectional trench gate charge storage type IGBT device according to embodiment 3 of the present invention along the EF line;
fig. 19 is a schematic cross-sectional view of a half cell structure of a bidirectional trench gate charge storage type IGBT device according to embodiment 3 of the present invention, along a GH line;
fig. 20 is a schematic structural diagram of a half cell of a bidirectional trench gate charge storage type IGBT device according to embodiment 4 of the present invention;
fig. 21 is a schematic structural diagram of a half cell of a bidirectional trench gate charge storage type IGBT device provided in embodiment 4 of the present invention before forming an isolation dielectric layer and an emitter metal;
fig. 22 is a schematic cross-sectional view of a half cell structure of a bidirectional trench gate charge storage type IGBT device according to embodiment 4 of the present invention along line AB;
fig. 23 is a schematic cross-sectional view of a half cell structure of a bidirectional trench gate charge storage type IGBT device according to embodiment 4 of the present invention, taken along the CD line;
fig. 24 is a schematic cross-sectional view of a half cell structure of a bidirectional trench gate charge storage type IGBT device according to embodiment 4 of the present invention along the EF line;
fig. 25 is a schematic cross-sectional view of a half cell structure of a bidirectional trench gate charge storage type IGBT device according to embodiment 4 of the present invention, along a GH line;
fig. 26 is a schematic structural view of a half cell after a first trench is formed in the manufacturing method according to embodiment 1 of the present invention;
FIG. 27 is a schematic diagram showing a half cell structure after a split electrode dielectric layer is formed in the manufacturing method of embodiment 1 of the present invention;
FIG. 28 is a schematic view showing a structure of a half cell after formation of split electrodes in the manufacturing method of example 1 of the present invention;
fig. 29 is a schematic structural view of a half cell after forming a second trench in the manufacturing method according to embodiment 1 of the present invention;
fig. 30 is a schematic structural view of a half cell after a gate dielectric layer is formed in the manufacturing method of embodiment 1 of the invention;
fig. 31 is a schematic view of a half cell structure after formation of a gate electrode in the manufacturing method of embodiment 1 of the invention;
fig. 32 is a schematic structural diagram of a half cell after forming an N + emitter region and a P + body contact region in the manufacturing method of embodiment 1 of the invention;
FIG. 33 is a schematic diagram of a half-cell structure after forming an isolation dielectric layer in the manufacturing method of embodiment 1 of the present invention;
fig. 34 is a schematic view of a half cell structure after emitter metal is formed in the manufacturing method according to embodiment 1 of the present invention;
FIG. 35 is a schematic view showing a half cell structure after all steps are completed in the manufacturing method of example 1 of the present invention;
fig. 36 is a schematic structural view of a half cell after forming a second gate trench in the manufacturing method according to embodiment 2 of the present invention;
fig. 37 is a schematic view of a half cell structure after forming a second gate electrode in the manufacturing method of embodiment 2 of the invention;
fig. 38 is a schematic view of a half cell structure after forming an N + emitter region and a P + body contact region in the manufacturing method of embodiment 2 of the invention;
FIG. 39 is a schematic diagram of a half-cell structure after forming an isolation dielectric layer in the manufacturing method of embodiment 2 of the present invention;
in the figure: 1 is a front emitter metal, 2 is a front isolation dielectric layer, 3 is a front N + emitter region, 4 is a front P + body contact region, 5 is a front P-type base region, 6 is a front N-type charge storage layer, 71 is a front gate electrode, 72 is a front gate dielectric layer, 81 is a front split electrode, 82 is a front split electrode dielectric layer, 9 is an N-type drift region, 10 is a front P-type layer, 21 is a back emitter metal, 22 is a back isolation dielectric layer, 23 is a back N + emitter region, 24 is a back P + body contact region, 25 is a back P-type base region, 26 is a back N-type charge storage layer, 271 is a back gate electrode, 272 is a back gate dielectric layer, 281 is a back split electrode, 282 is a back split electrode dielectric layer, and 210 is a back P-type layer.
Detailed Description
The principles and features of the present invention are explained in detail below in conjunction with the drawings and the detailed description of the invention:
in the drawings, the same reference numerals denote the same or similar components or elements. The bidirectional trench gate charge storage type IGBT device provided by the invention can be an N-channel device and also can be a P-channel device, the N-channel device is taken as an example for explanation, and the structure and the working principle of the P-channel device can be clear to the skilled person on the basis of disclosing the N-channel device.
Example 1:
a two-way trench gate charge storage type IGBT is characterized in that a half cell of the IGBT is shown in figure 4, the cross section of the IGBT along an AB line and a CD line is shown in figures 6 and 7, a three-dimensional coordinate system is established by taking any inflection point of the half cell as an origin, two sides of the bottom surface of a quarter cell, which intersect at the inflection point, are respectively taken as an x axis and a z axis, a straight line passing through the inflection point and perpendicular to the bottom surface is taken as a y axis, and the directions of the x axis, the y axis and the z axis are shown in figure 4;
the half cells comprise MOS structures which are respectively arranged on the front surface and the back surface of the N-type drift region 9; the method is characterized in that: the front MOS structure comprises a front emitter metal 1, a front isolation dielectric layer 2, a front split trench gate structure, a front first conduction type semiconductor emitter region 3, a front second conduction type semiconductor body contact region 4, a front second conduction type semiconductor base region 5 and a front first conduction type semiconductor charge storage layer 6; the back MOS structure comprises a back emitter metal 21, a back isolation dielectric layer 22, a back split trench gate structure, a back first conductive type semiconductor emitter region 23, a back second conductive type semiconductor body contact region 24, a back second conductive type semiconductor base region 25 and a back first conductive type semiconductor charge storage layer 26;
in the positive MOS structure, positive N type charge storage layer 6 is located the top layer of N type drift region 9, positive P type base region 5 is located the top layer of positive N type charge storage layer 6, positive P + body contact region 4 and positive N + emitter region 3 are independent each other and are located the top layer of positive P type base region 5 side by side, its characterized in that: the extension depth of the front surface N + emitter region 3 on the top layer of the front surface P type base region 5 is smaller than that of the front surface P type base region 5 on the top layer of the front surface N type charge storage layer 6; the top layer of the P-type drift region 9 further has a front split trench gate structure, and the front split trench gate structure includes a front gate electrode 71, a front gate dielectric layer 72 around the front gate electrode, a front split electrode 81, and a front split electrode dielectric layer 82 around the front split electrode; the depth of the front-side gate electrode 71 penetrating downwards from the top layer of the device is less than the junction depth of the front-side N-type charge storage layer 6, the extension directions of the front-side split electrode 81 and the front-side gate electrode 71 in the top layer of the N-type drift region 9 are the same and both extend along the z-axis direction in fig. 3, the front-side split electrode 81 is located at the bottom of the front-side gate electrode 71, the front-side split electrode 81 is connected with the front-side gate electrode 71 through the front-side gate dielectric layer 72, the extension depth of the front-side split electrode 81 is greater than that of the front-side gate electrode 71, so that the front-side split electrode 81 is arranged by half surrounding the front-side gate electrode 71 and the gate dielectric layer 72 on; the front gate electrode 71 is connected with the front N + emitter region 3, the front P-type base region 5 and the front N-type charge storage layer 6 through a front gate dielectric layer 72; the front split electrode 81 is connected with the P + body contact region 4, the P-type base region 5, the front N-type charge storage layer 6 and the N-type drift region 9 through a front split electrode dielectric layer 82; the upper surfaces of the front gate electrode 71 and the front gate dielectric layer 72 on the peripheral side thereof are provided with a front isolation dielectric layer 2; the upper surfaces of the front split electrode 81, the front isolation dielectric layer 2, the front P + body contact region 4 and the front N + emitter region 3 are connected with the front emitter metal 1; the back MOS structure is the same as the front MOS structure, and the front MOS structure and the back MOS structure are mirror-symmetric along the lateral centerline of the N-type drift region 9.
In this embodiment, the dimension of the P + body contact regions 4 and 24 along the z-axis direction is 1 to 5 μm, and the dimension along the y-axis direction, i.e., the junction depth, is 0.1 to 0.3 μm; the size of the P- type base regions 5 and 25 along the x-axis direction is 2-10 mu m, and the size along the y-axis, namely the junction depth, is 0.3-1 mu m; the size of the N-type charge storage layers 6 and 26 along the y axis, namely the junction depth, is 0.5-1 mu m; the depth of the gate electrodes 71 and 271 along the y axis is 0.6-1.6 um; the groove depth of the split groove gate structure is 4-8 mu m.
Example 2:
a two-way trench gate charge storage type IGBT, one half cell of which is shown in fig. 8, and cross sections along an AB line, a CD line, an EF line, and a GH line are shown in fig. 10 to 13, and a coordinate system is established in the same manner as in the embodiment, specifically, see fig. 8;
this embodiment is different from embodiment 1 in that: the extension depth of the front gate electrode 71 on the top layer of the N-type drift region 9 is equal to the extension depth of the front split electrode 81, the extension width of the front gate electrode 71 on the top layer of the device is smaller than the extension width of the front split electrode 81, and meanwhile, a part of the front split electrode dielectric layer 82 and a part of the front split electrode 81 structure are remained on the top layer of the device; the thickness of the front split electrode dielectric layer 82 is greater than that of the front gate dielectric layer 72; the back MOS structure is the same as the front MOS structure and is mirror-symmetric along the lateral centerline of the N-type drift region 9, and the rest of the structure is the same as that of embodiment 1.
In the embodiment, by reserving a part of the split electrodes 81 and 281 and the split electrode dielectric layers 82 and 282 on the top layer of the device, the change of the channel density of the device is avoided, the characteristics of the short-circuit safe working area are not affected, the extension depth of the gate electrodes 71 and 271 along the top layer of the N-type drift area 9 is changed, and the gate electrodes 71 and 271 penetrate through the N-type drift area 9 along the z-axis direction, so that a better electrode leading-out mode is formed, the process is more favorably realized, the parasitic effect is reduced, and the reliability of the device is improved.
Example 3:
a two-way trench gate charge storage type IGBT, one half cell of which is shown in fig. 14, and cross sections along an AB line, a CD line, an EF line, and a GH line are shown in fig. 16 to 19, and a coordinate system is established in the same manner as in the embodiment, specifically, see fig. 14;
this embodiment is different from embodiment 2 in that: in the embodiment, a front surface split electrode 81 and split electrode dielectric layer 82 structure is not arranged on the top layer of the front surface MOS structure of the device, the front surface split electrode 81 and the front surface split electrode dielectric layer 82 are located at the bottom of the front surface gate electrode 71, the depths of the front surface N + emitter region 3 and the front surface P + body contact region 4 along the z-axis direction are equal and smaller than the depth of the front surface P-type base region 5 along the z-axis direction, and meanwhile, the thickness of the front surface gate electrode 71 connected with the front surface N + emitter region 3 through the front surface gate dielectric layer 72 is larger than the thickness of the front surface gate electrode 71 not connected with the front surface; the back MOS structure is the same as the front MOS structure and is mirror symmetric along the lateral centerline of the N-type drift region 9.
In the embodiment, by changing the widths of the gate electrodes 71 and 271, when the inversion layers are formed on the surfaces of the P- type base regions 5 and 25 connected with the gate electrodes 71 and 271 through the gate dielectric layers 72 and 272 along the z-axis direction at the middle part of the surfaces, the inversion layers are not formed at the two end parts, so that the channel density of the device is not increased, the short-circuit safe working area characteristic of the device is not affected, and meanwhile, a better electrode leading-out mode is formed by the gate electrodes penetrating through the N-drift region 9 along the z-axis direction, so that the process is more favorably realized, the parasitic effect is reduced, and the reliability of the device is improved.
Example 4:
a two-way trench gate charge storage type IGBT, one half cell of which is shown in fig. 20, and cross sections along an AB line, a CD line, an EF line, and a GH line are shown in fig. 22 to 25, and a coordinate system is established in the same manner as in the embodiment, specifically, see fig. 20;
the present embodiment is different from embodiment 3 in that: introducing a P-type layer 10 into the bottom of a split trench gate structure in a front MOS structure, connecting the P-type layer 10 with a split electrode 81 through a split electrode dielectric layer 82, wherein the junction depth of the P-type layer 10 and the P-type layer 210 is 0.5-1 mu m, and the P-type layer 10 transversely extends to the side edge into an N-type drift region 9 below an N-type charge storage layer 6 as an optimal mode; the improvement of the back MOS structure is the same as the improvement of the front MOS structure, and the back MOS structure is the same as the front MOS structure and is mirror-symmetric along the lateral centerline of the N-type drift region 9, and the rest of the structures are the same as those in embodiment 2.
The embodiment shields the influence of negative charges in the N-type charge storage layer by the structure, reduces the capacitance of the grid electrode, improves the electric field concentration at the bottom of the groove, and improves the breakdown voltage and the reliability of the device.
Example 5:
a two-way trench gate charge storage IGBT whose half cell structure differs from that of embodiment 1 in that: the back MOS structure and the front MOS structure are cross-symmetric along the lateral centerline of the N-type drift region 9, and the rest of the structure is the same as that of embodiment 1.
The structure is the same as that of embodiment 1 except that the front/back N-channel MOS structure is symmetrical about the center of the lateral centerline of the N-type drift region 9, and the device performance is also the same as that of embodiment 1.
Example 6:
in this embodiment, a bidirectional trench gate charge storage IGBT with a 1200V voltage level is taken as an example for explanation, and devices with different performance parameters can be prepared according to actual requirements based on common knowledge in the art.
A manufacturing method of a bidirectional trench gate charge storage type IGBT is characterized by comprising the following steps:
step 1: two same N-type lightly doped monocrystalline silicon wafers are used as an N-type drift region 9 of the device, the thickness of the selected silicon wafers is 300-600 mu m, and the doping concentration is 1013～1014Per cm3；
Step 2: respectively growing a layer of field oxide layer on the surfaces of two silicon wafers by the same process, photoetching to obtain an active region, growing a layer of pre-oxide layer, and implanting N-type impurities by ions to obtain an N-type charge storage layer, wherein the ion implantation energy is 200-500 keV, and the implantation dosage is 1013～1014Per cm2(ii) a And then injecting P-type impurities above the N-type charge storage layer through ions, and annealing to obtain a P-type base region, wherein the energy of ion injection is 60-120 keV, and the injection dosage is 1013～1014Per cm2Annealing at 1100-1150 ℃ for 10-30 minutes, implanting P-type impurities into the top layer of the P-type base region by ions, and annealing to obtain a P + body contact region, wherein the energy of the implanted P-type impurities is 60-80 keV, and the implantation dose is 10 keV15～1016Per cm2Annealing at 900 ℃ for 20-30 minutes;
and step 3: respectively depositing TEOS protective layers with the thickness of 700-1000 nm on the surfaces of two silicon wafers by adopting the same process, photoetching a window to perform groove silicon etching, and further etching an N-type drift region 9 to form a first groove, wherein as shown in figure 26, the first groove extends from the front end of a device to the rear end of the device, and the depth of the first groove is greater than the junction depth of an N-type charge storage layer;
and 4, step 4: o at 1050-1150 deg.C2Under the atmosphere, respectively forming dielectric layers on the inner walls of the first grooves by the same process to serve as split electrode dielectric layers, as shown in fig. 27; depositing an electrode material in the first trench at 750-950 ℃ to form a split electrode, wherein a polysilicon material is used as the split electrode material in this embodiment, as shown in fig. 28;
and 5: respectively depositing TEOS protective layers with the thickness of 700-1000 nm on the surfaces of two silicon wafers by adopting the same process, photoetching a window to perform groove silicon etching, and etching to remove part of split electrodes formed in the previous step and split electrode dielectric layers on the peripheral sides of the split electrodes so as to form a second groove, wherein the second groove is consistent with the first groove in the extension direction of the top layer of the device, and the depth of the second groove is smaller than the junction depth of the N-type charge storage layer, as shown in figure 29;
step 6: o at 1050-1150 deg.C2Under the atmosphere, respectively forming dielectric layers on the inner walls of the second trenches by the same process to serve as gate dielectric layers, as shown in fig. 30; then, at 750-950 ℃, depositing an electrode material in the second trench as a gate electrode, wherein the embodiment adopts a polysilicon material as the gate electrode material; the split electrode in the first trench and the split electrode dielectric layer on the peripheral side thereof, and the gate electrode and the gate dielectric layer in the second trench form a split trench gate structure, and the split trench gate structure is shown in fig. 31;
and 7: injecting N-type impurities into the top layer of the P-type base region by adopting the same photoetching and ion injection processes, wherein the energy of the N-type impurities injected by ions is 30-60 keV, and the injection dosage is 1015～1016Per cm2An N + emitter region which is arranged in parallel with the P + body contact region and is connected with the gate electrode through a gate dielectric layer is prepared, the extension depth of the N + emitter region on the top layer of the P-type base region is smaller than that of the P-type base region on the top layer of the N-type charge storage layer, and the extension depth of the N + emitter region on the top layer of the P-type base region is the same as that of the gate electrode on the N-type drift region 9; as shown in fig. 32;
and 8: as shown in fig. 33, dielectric layers are respectively deposited on the surfaces of the devices by the same process; forming an isolation dielectric layer 2 on the upper surfaces of the gate electrode and the gate dielectric layer by adopting photoetching and etching processes;
and step 9: as shown in fig. 34, the same process is used to deposit metal on the device surfaces; emitter metal is formed on the isolation dielectric layer 2, the N + emitter region, the P + body contact region, the split electrode and the upper surface of the split electrode dielectric layer by adopting photoetching and etching processes; and turning over the silicon wafers, thinning the thicknesses of the two silicon wafers by adopting the same process, and then forming the bidirectional trench gate charge storage type IGBT device by back-to-back bonding the two identical semiconductor wafers by adopting a bonding process, as shown in the attached figure 35, so as to finish the preparation of the device.
It should be noted that, in the manufacturing method provided in this embodiment, the lateral position of the device surface corresponds to the x-axis direction of the coordinate system shown in the drawings of the specification, and the longitudinal position of the device surface corresponds to the z-axis direction of the coordinate system shown in the drawings of the specification, which is not described in detail below.
Further, step 3 may be to form the P-type base region and the P + body contact region in two steps, respectively; or the P + body contact region 4 may be formed again at step 8;
further, a trench may be formed first and then an N-type charge storage layer, a P-type base region, and a P + body contact region may be formed by ion implantation, that is, the sequence of step 3 and step 4 may be exchanged;
further, the extension depth of the gate electrode 71 on the top layer of the N-type drift region 9 is equal to the extension depth of the split electrode 81, the extension width of the gate electrode 71 on the top layer of the device is smaller than the extension width of the split electrode 81, meanwhile, a part of the split electrode dielectric layer 82 and a part of the split electrode 81 structure are remained on the top layer of the device, and the thickness of the split electrode dielectric layer 82 is larger than that of the gate dielectric layer 72, so that the structure shown in fig. 8 can be obtained.
Further, as shown in fig. 36 to 39, the N + emitter region and the P + body contact region are juxtaposed in the middle of the top layer of the P-type base region along the z-axis direction, at this time, the gate electrode penetrates through the N-type drift region along the z-axis direction, and the width of the portion of the gate electrode connected to the N + emitter region through the gate dielectric layer along the z-axis direction along the x-axis direction is greater than the width of the portion of the gate electrode not connected to the N + emitter region, that is, the portion of the gate electrode connected to the P-type base region along the x-axis direction, that is, the shape of the gate electrode on the xoz plane is "convex", and the.
Further, step 3 may add an ion implantation step to form a P-type layer at the bottom of the split trench gate structure, so as to obtain the structure shown in fig. 20.
Furthermore, the materials of the isolation dielectric layer, the gate dielectric layer and the split electrode dielectric layer can be the same material or different materials.
Further, the device structure and the manufacturing method are described by taking an N-channel IGBT device as an example, but the present invention is also applicable to the manufacturing of a P-channel IGBT device, and details are not described herein.
The above is a preferred embodiment of the present invention, and various changes and modifications can be made by those skilled in the art without departing from the technical spirit of the present invention from the above description. Therefore, the technical scope of the present invention is not limited to the content of the specification, and all equivalent changes and modifications made in the claims of the present invention should be covered by the present invention.
Claims (12)
1. A kind of two-way ditch groove gate charge storage type IGBT, its half cell includes setting up in the MOS structure of the front and back of the first conductivity type semiconductor drift region (9) separately; the method is characterized in that: the front MOS structure comprises a front emitter metal (1), a front isolation dielectric layer (2), a front split trench gate structure, a front first conduction type semiconductor emitter region (3), a front second conduction type semiconductor body contact region (4), a front second conduction type semiconductor base region (5) and a front first conduction type semiconductor charge storage layer (6); the back MOS structure comprises a back emitter metal (21), a back isolation dielectric layer (22), a back split trench gate structure, a back first conductive type semiconductor emitter region (23), a back second conductive type semiconductor body contact region (24), a back second conductive type semiconductor base region (25) and a back first conductive type semiconductor charge storage layer (26);
in the front-side MOS structure, a front-side first conduction type semiconductor charge storage layer (6) is positioned at the top layer of the first conduction type semiconductor drift region (9); the front second conductive type semiconductor base region (5) is positioned on the top layer of the front first conductive type semiconductor charge storage layer (6); the front-surface second-conductivity-type semiconductor body contact region (4) and the front-surface first-conductivity-type semiconductor emitter region (3) are mutually independent and are arranged on the top layer of the front-surface second-conductivity-type semiconductor base region (5) in parallel; the top layer of the first conduction type semiconductor drift region (9) is also provided with a front split trench gate structure, and the front split trench gate structure comprises a front gate electrode (71), a front gate dielectric layer (72) on the periphery of the front gate electrode, a front split electrode (81) and a front split electrode dielectric layer (82) on the periphery of the front split electrode; the depth of the front-surface gate electrode (71) penetrating downwards from the top layer of the device is smaller than the junction depth of the front-surface first conduction type semiconductor charge storage layer (6), the extension directions of the front-surface split electrode (81) and the front-surface gate electrode (71) in the device are consistent, the front-surface split electrode (81) is positioned at the bottom of the front-surface gate electrode (71), the front-surface split electrode (81) is connected with the front-surface gate electrode (71) through a front-surface gate dielectric layer (72), and the depth of the front-surface split electrode (81) penetrating downwards is larger than the junction depth of the front-surface first conduction type semiconductor charge storage layer (6); the front-surface gate electrode (71) is connected with the front-surface first conduction type semiconductor emitter region (3), the front-surface second conduction type semiconductor base region (5) and the front-surface first conduction type semiconductor charge storage layer (6) through a front-surface gate dielectric layer (72); the front split electrode (81) is at least connected with the front first conduction type semiconductor charge storage layer (6) and the front first conduction type semiconductor drift region (9) through a front split electrode dielectric layer (82); the upper surfaces of the front gate electrode (71) and the front gate dielectric layer (72) on the peripheral side of the front gate electrode are provided with front isolation dielectric layers (2); the upper surfaces of the front side isolation dielectric layer (2), the front side second conduction type semiconductor body contact region (4) and the front side first conduction type semiconductor emitting region (3) are connected with the front side emitter metal (1); the back MOS structure is the same as the front MOS structure;
the split electrode (81, 281) extends along the top layer of the second conduction type semiconductor drift region (9) to a depth which is larger than the extension depth of the gate electrode (71, 271), so that the split electrode (81, 281) is arranged to surround the gate electrode (71, 271) and the gate dielectric layer (72, 272) on the peripheral side of the gate electrode, the split electrode (81, 281) is connected with the gate electrode (71, 271) through the gate dielectric layer (72, 272), the split electrode (81, 281) is connected with the first conduction type semiconductor body contact region (4, 24) and the first conduction type semiconductor base region (5, 25) through the split electrode dielectric layer (82, 282), and the split electrode (81, 281) is connected with the emitter metal (1, 21).
2. A kind of two-way ditch groove gate charge storage type IGBT, its half cell includes setting up in the MOS structure of the front and back of the first conductivity type semiconductor drift region (9) separately; the method is characterized in that: the front MOS structure comprises a front emitter metal (1), a front isolation dielectric layer (2), a front split trench gate structure, a front first conduction type semiconductor emitter region (3), a front second conduction type semiconductor body contact region (4), a front second conduction type semiconductor base region (5) and a front first conduction type semiconductor charge storage layer (6); the back MOS structure comprises a back emitter metal (21), a back isolation dielectric layer (22), a back split trench gate structure, a back first conductive type semiconductor emitter region (23), a back second conductive type semiconductor body contact region (24), a back second conductive type semiconductor base region (25) and a back first conductive type semiconductor charge storage layer (26);
in the front-side MOS structure, a front-side first conduction type semiconductor charge storage layer (6) is positioned at the top layer of the first conduction type semiconductor drift region (9); the front second conductive type semiconductor base region (5) is positioned on the top layer of the front first conductive type semiconductor charge storage layer (6); the front-surface second-conductivity-type semiconductor body contact region (4) and the front-surface first-conductivity-type semiconductor emitter region (3) are mutually independent and are arranged on the top layer of the front-surface second-conductivity-type semiconductor base region (5) in parallel; the top layer of the first conduction type semiconductor drift region (9) is also provided with a front split trench gate structure, and the front split trench gate structure comprises a front gate electrode (71), a front gate dielectric layer (72) on the periphery of the front gate electrode, a front split electrode (81) and a front split electrode dielectric layer (82) on the periphery of the front split electrode; the depth of the front-surface gate electrode (71) penetrating downwards from the top layer of the device is smaller than the junction depth of the front-surface first conduction type semiconductor charge storage layer (6), the extension directions of the front-surface split electrode (81) and the front-surface gate electrode (71) in the device are consistent, the front-surface split electrode (81) is positioned at the bottom of the front-surface gate electrode (71), the front-surface split electrode (81) is connected with the front-surface gate electrode (71) through a front-surface gate dielectric layer (72), and the depth of the front-surface split electrode (81) penetrating downwards is larger than the junction depth of the front-surface first conduction type semiconductor charge storage layer (6); the front-surface gate electrode (71) is connected with the front-surface first conduction type semiconductor emitter region (3), the front-surface second conduction type semiconductor base region (5) and the front-surface first conduction type semiconductor charge storage layer (6) through a front-surface gate dielectric layer (72); the front split electrode (81) is at least connected with the front first conduction type semiconductor charge storage layer (6) and the front first conduction type semiconductor drift region (9) through a front split electrode dielectric layer (82); the upper surfaces of the front gate electrode (71) and the front gate dielectric layer (72) on the peripheral side of the front gate electrode are provided with front isolation dielectric layers (2); the upper surfaces of the front side isolation dielectric layer (2), the front side second conduction type semiconductor body contact region (4) and the front side first conduction type semiconductor emitting region (3) are connected with the front side emitter metal (1); the back MOS structure is the same as the front MOS structure;
the depth of the gate electrode (71, 271) extending along the top layer of the second conduction type semiconductor drift region (9) is equal to the depth of the split electrode (81, 281) extending, one part of the front split electrode (81) is positioned below the front gate electrode (71), one part of the back split electrode (281) is positioned above the back gate electrode (271), the other part of the front split electrode (81) is positioned on the top layer of the device and is connected with the front gate electrode (71) through a front gate dielectric layer (72), the other part of the back split electrode (281) is positioned on the bottom layer of the device and is connected with the back gate electrode (271) through a back gate dielectric layer (272), and the width of the gate electrode (71, 271) extending along the top layer of the device is smaller than the width of the split electrode (81, 281) extending; at this time, the split electrode (81, 281) is connected between the first conductivity type semiconductor body contact region (4, 24) and the first conductivity type semiconductor base region (5, 25) through the split electrode dielectric layer (82, 282), and the split electrode (81, 281) is connected to the emitter metal (1, 21).
3. A kind of two-way ditch groove gate charge storage type IGBT, its half cell includes setting up in the MOS structure of the front and back of the first conductivity type semiconductor drift region (9) separately; the method is characterized in that: the front MOS structure comprises a front emitter metal (1), a front isolation dielectric layer (2), a front split trench gate structure, a front first conduction type semiconductor emitter region (3), a front second conduction type semiconductor body contact region (4), a front second conduction type semiconductor base region (5) and a front first conduction type semiconductor charge storage layer (6); the back MOS structure comprises a back emitter metal (21), a back isolation dielectric layer (22), a back split trench gate structure, a back first conductive type semiconductor emitter region (23), a back second conductive type semiconductor body contact region (24), a back second conductive type semiconductor base region (25) and a back first conductive type semiconductor charge storage layer (26);
in the front-side MOS structure, a front-side first conduction type semiconductor charge storage layer (6) is positioned at the top layer of the first conduction type semiconductor drift region (9); the front second conductive type semiconductor base region (5) is positioned on the top layer of the front first conductive type semiconductor charge storage layer (6); the front-surface second-conductivity-type semiconductor body contact region (4) and the front-surface first-conductivity-type semiconductor emitter region (3) are mutually independent and are arranged on the top layer of the front-surface second-conductivity-type semiconductor base region (5) in parallel; the top layer of the first conduction type semiconductor drift region (9) is also provided with a front split trench gate structure, and the front split trench gate structure comprises a front gate electrode (71), a front gate dielectric layer (72) on the periphery of the front gate electrode, a front split electrode (81) and a front split electrode dielectric layer (82) on the periphery of the front split electrode; the depth of the front-surface gate electrode (71) penetrating downwards from the top layer of the device is smaller than the junction depth of the front-surface first conduction type semiconductor charge storage layer (6), the extension directions of the front-surface split electrode (81) and the front-surface gate electrode (71) in the device are consistent, the front-surface split electrode (81) is positioned at the bottom of the front-surface gate electrode (71), the front-surface split electrode (81) is connected with the front-surface gate electrode (71) through a front-surface gate dielectric layer (72), and the depth of the front-surface split electrode (81) penetrating downwards is larger than the junction depth of the front-surface first conduction type semiconductor charge storage layer (6); the front-surface gate electrode (71) is connected with the front-surface first conduction type semiconductor emitter region (3), the front-surface second conduction type semiconductor base region (5) and the front-surface first conduction type semiconductor charge storage layer (6) through a front-surface gate dielectric layer (72); the front split electrode (81) is at least connected with the front first conduction type semiconductor charge storage layer (6) and the front first conduction type semiconductor drift region (9) through a front split electrode dielectric layer (82); the upper surfaces of the front gate electrode (71) and the front gate dielectric layer (72) on the peripheral side of the front gate electrode are provided with front isolation dielectric layers (2); the upper surfaces of the front side isolation dielectric layer (2), the front side second conduction type semiconductor body contact region (4) and the front side first conduction type semiconductor emitting region (3) are connected with the front side emitter metal (1); the back MOS structure is the same as the front MOS structure;
the front first conduction type semiconductor emitter region (3) and the front second conduction type semiconductor body contact region (4) are located in the center of the top layer of the front second conduction type semiconductor base region (5), the back first conduction type semiconductor emitter region (23) and the back second conduction type semiconductor body contact region (24) are located in the center of the bottom layer of the back second conduction type semiconductor base region (25), the front split electrode (81) is located below the front gate electrode (71), the back split electrode (281) is located above the back gate electrode (271), and the second conduction type semiconductor base regions (5 and 25) are connected with the gate electrodes (71 and 271) through gate dielectric layers (72 and 272).
4. A kind of two-way ditch groove gate charge storage type IGBT, its half cell includes setting up in the MOS structure of the front and back of the first conductivity type semiconductor drift region (9) separately; the method is characterized in that: the front MOS structure comprises a front emitter metal (1), a front isolation dielectric layer (2), a front split trench gate structure, a front first conduction type semiconductor emitter region (3), a front second conduction type semiconductor body contact region (4), a front second conduction type semiconductor base region (5) and a front first conduction type semiconductor charge storage layer (6); the back MOS structure comprises a back emitter metal (21), a back isolation dielectric layer (22), a back split trench gate structure, a back first conductive type semiconductor emitter region (23), a back second conductive type semiconductor body contact region (24), a back second conductive type semiconductor base region (25) and a back first conductive type semiconductor charge storage layer (26);
in the front-side MOS structure, a front-side first conduction type semiconductor charge storage layer (6) is positioned at the top layer of the first conduction type semiconductor drift region (9); the front second conductive type semiconductor base region (5) is positioned on the top layer of the front first conductive type semiconductor charge storage layer (6); the front-surface second-conductivity-type semiconductor body contact region (4) and the front-surface first-conductivity-type semiconductor emitter region (3) are mutually independent and are arranged on the top layer of the front-surface second-conductivity-type semiconductor base region (5) in parallel; the top layer of the first conduction type semiconductor drift region (9) is also provided with a front split trench gate structure, and the front split trench gate structure comprises a front gate electrode (71), a front gate dielectric layer (72) on the periphery of the front gate electrode, a front split electrode (81) and a front split electrode dielectric layer (82) on the periphery of the front split electrode; the depth of the front-surface gate electrode (71) penetrating downwards from the top layer of the device is smaller than the junction depth of the front-surface first conduction type semiconductor charge storage layer (6), the extension directions of the front-surface split electrode (81) and the front-surface gate electrode (71) in the device are consistent, the front-surface split electrode (81) is positioned at the bottom of the front-surface gate electrode (71), the front-surface split electrode (81) is connected with the front-surface gate electrode (71) through a front-surface gate dielectric layer (72), and the depth of the front-surface split electrode (81) penetrating downwards is larger than the junction depth of the front-surface first conduction type semiconductor charge storage layer (6); the front-surface gate electrode (71) is connected with the front-surface first conduction type semiconductor emitter region (3), the front-surface second conduction type semiconductor base region (5) and the front-surface first conduction type semiconductor charge storage layer (6) through a front-surface gate dielectric layer (72); the front split electrode (81) is at least connected with the front first conduction type semiconductor charge storage layer (6) and the front first conduction type semiconductor drift region (9) through a front split electrode dielectric layer (82); the upper surfaces of the front gate electrode (71) and the front gate dielectric layer (72) on the peripheral side of the front gate electrode are provided with front isolation dielectric layers (2); the upper surfaces of the front side isolation dielectric layer (2), the front side second conduction type semiconductor body contact region (4) and the front side first conduction type semiconductor emitting region (3) are connected with the front side emitter metal (1); the back MOS structure is the same as the front MOS structure;
the thickness of the gate electrode (71, 271) connected to the first conductivity type semiconductor emitter region (3, 23) through the gate dielectric layer (72, 272) is greater than the thickness of the gate electrode (71, 271) not connected to the first conductivity type semiconductor emitter region (3, 23).
5. The bidirectional trench gate charge storage IGBT of any one of claims 1 to 4, wherein: the semiconductor charge storage structure is characterized in that a front-surface second conduction type semiconductor layer (10) is arranged below the front-surface split groove gate structure, a back-surface second conduction type semiconductor layer (210) is arranged above the back-surface split groove gate structure, and the front-surface second conduction type semiconductor layer (10) or the back-surface second conduction type semiconductor layer (210) extends transversely into a first conduction type semiconductor drift region (9) below the front-surface first conduction type semiconductor charge storage layer (6) or above the back-surface first conduction type semiconductor charge storage layer (26).
6. The bidirectional trench gate charge storage IGBT of any one of claims 1 to 4, wherein: the split electrodes (81, 281) are equipotential with the emitter metals (1, 21).
7. The bidirectional trench gate charge storage IGBT of any one of claims 1 to 4, wherein: the first conductive type semiconductor is a P-type semiconductor, and the second conductive type semiconductor is an N-type semiconductor; or the first conductive type semiconductor is an N-type semiconductor and the second conductive type semiconductor is a P-type semiconductor.
8. A preparation method of a bidirectional trench gate charge storage type IGBT is characterized by comprising the following steps:
the method comprises the following steps: manufacturing two identical first-conductivity-type semiconductor drift regions (9);
step two: respectively manufacturing a first conductive type semiconductor charge storage layer and a second conductive type semiconductor base region positioned on the top layer of the first conductive type semiconductor charge storage layer on the front surfaces of the two first conductive type semiconductor drift regions (9) by adopting the same pre-oxidation, photoetching, etching, ion implantation and high-temperature annealing processes;
step three: respectively etching two first conductive type semiconductor charge storage layers to form first grooves by adopting the same photoetching, etching, thermal oxidation and deposition processes, wherein the depth of each first groove is greater than the junction depth of the first conductive type semiconductor charge storage layers; forming a split electrode dielectric layer on the inner wall of the first groove, and then depositing an electrode material in the groove to form a split electrode;
step four: respectively etching two first conduction type semiconductor drift regions (9) to form second grooves by adopting the same photoetching, etching, thermal oxidation and deposition processes, wherein the depth of each second groove is less than the junction depth of the first conduction type semiconductor charge storage layer, and the first grooves and the second grooves are consistent in the extending direction of the top layer of the device; forming a gate dielectric layer on the inner wall of the second groove, depositing an electrode material in the second groove to form a gate electrode, forming a split groove gate structure by the gate electrode and the gate dielectric layer on the peripheral side of the gate electrode, the split electrode and the split electrode dielectric layer on the peripheral side of the split electrode,
the split electrode (81, 281) extends along the top layer of the second conduction type semiconductor drift region (9) to a depth which is larger than the extension depth of the gate electrode (71, 271), so that the split electrode (81, 281) is arranged to surround the gate electrode (71, 271) and the gate dielectric layer (72, 272) on the peripheral side of the gate electrode, the split electrode (81, 281) is connected with the gate electrode (71, 271) through the gate dielectric layer (72, 272), the split electrode (81, 281) is connected with the first conduction type semiconductor body contact region (4, 24) and the first conduction type semiconductor base region (5, 25) through the split electrode dielectric layer (82, 282), and the split electrode (81, 281) is connected with the emitter metal (1, 21);
step five: respectively manufacturing a second conductive type semiconductor body contact region and a first conductive type semiconductor emitter region which are mutually independent and arranged in parallel on the top layers of the two second conductive type semiconductor base regions by adopting the same photoetching, etching, ion implantation and high-temperature annealing processes; the extension depth of the first conductive type semiconductor emitter region on the top layer of the second conductive type semiconductor base region is smaller than that of the second conductive type semiconductor base region on the top layer of the first conductive type semiconductor charge storage layer, and the first conductive type semiconductor emitter region is arranged close to the gate electrode and is connected with the gate electrode through the gate dielectric layer;
step six: forming an isolation dielectric layer on the upper surfaces of the gate electrode and the gate dielectric layer by adopting the same photoetching, etching and deposition processes;
step seven: depositing metal on the surface, and respectively forming emitter metal on the isolation dielectric layer, the second conductive type semiconductor body contact area and the upper surface of the first conductive type semiconductor emitter area by adopting the same photoetching and etching processes;
step eight: and turning over the semiconductor device, thinning the thickness of the first conduction type semiconductor drift region (9) by adopting the same process, and then forming the two completely same semiconductor devices back to back by adopting a bonding process to form the bidirectional trench gate charge storage type IGBT device, thereby completing the preparation of the device.
9. A preparation method of a bidirectional trench gate charge storage type IGBT is characterized by comprising the following steps:
the method comprises the following steps: manufacturing two identical first-conductivity-type semiconductor drift regions (9);
step two: respectively manufacturing a first conductive type semiconductor charge storage layer and a second conductive type semiconductor base region positioned on the top layer of the first conductive type semiconductor charge storage layer on the front surfaces of the two first conductive type semiconductor drift regions (9) by adopting the same pre-oxidation, photoetching, etching, ion implantation and high-temperature annealing processes;
step three: respectively etching two first conductive type semiconductor charge storage layers to form first grooves by adopting the same photoetching, etching, thermal oxidation and deposition processes, wherein the depth of each first groove is greater than the junction depth of the first conductive type semiconductor charge storage layers; forming a split electrode dielectric layer on the inner wall of the first groove, and then depositing an electrode material in the groove to form a split electrode;
step four: respectively etching two first conduction type semiconductor drift regions (9) to form second grooves by adopting the same photoetching, etching, thermal oxidation and deposition processes, wherein the depth of each second groove is less than the junction depth of the first conduction type semiconductor charge storage layer, and the first grooves and the second grooves are consistent in the extending direction of the top layer of the device; forming a gate dielectric layer on the inner wall of the second groove, depositing an electrode material in the second groove to form a gate electrode, forming a split groove gate structure by the gate electrode and the gate dielectric layer on the peripheral side of the gate electrode, the split electrode and the split electrode dielectric layer on the peripheral side of the split electrode,
the depth of the gate electrode (71, 271) extending along the top layer of the second conduction type semiconductor drift region 9 is equal to the depth of the extension of the split electrode (81, 281), one part of the split electrode (81, 281) is positioned below the gate electrode (71, 271), the other part of the split electrode is positioned on the top layer of the device and is connected with the gate electrode (71, 271) through a gate dielectric layer (72, 272), and the width of the gate electrode (71, 271) extending along the top layer of the device is smaller than the width of the extension of the split electrode (81, 281); the split electrodes (81, 281) are connected with the first conduction type semiconductor body contact areas (4, 24) and the first conduction type semiconductor base areas (5, 25) through split electrode dielectric layers (82, 282), and the split electrodes (81, 281) are connected with emitter metals (1, 21);
step five: respectively manufacturing a second conductive type semiconductor body contact region and a first conductive type semiconductor emitter region which are mutually independent and arranged in parallel on the top layers of the two second conductive type semiconductor base regions by adopting the same photoetching, etching, ion implantation and high-temperature annealing processes; the extension depth of the first conductive type semiconductor emitter region on the top layer of the second conductive type semiconductor base region is smaller than that of the second conductive type semiconductor base region on the top layer of the first conductive type semiconductor charge storage layer, and the first conductive type semiconductor emitter region is arranged close to the gate electrode and is connected with the gate electrode through the gate dielectric layer;
step six: forming an isolation dielectric layer on the upper surfaces of the gate electrode and the gate dielectric layer by adopting the same photoetching, etching and deposition processes;
step seven: depositing metal on the surface, and respectively forming emitter metal on the isolation dielectric layer, the second conductive type semiconductor body contact area and the upper surface of the first conductive type semiconductor emitter area by adopting the same photoetching and etching processes;
step eight: and turning over the semiconductor device, thinning the thickness of the first conduction type semiconductor drift region (9) by adopting the same process, and then forming the two completely same semiconductor devices back to back by adopting a bonding process to form the bidirectional trench gate charge storage type IGBT device, thereby completing the preparation of the device.
10. A preparation method of a bidirectional trench gate charge storage type IGBT is characterized by comprising the following steps:
the method comprises the following steps: manufacturing two identical first-conductivity-type semiconductor drift regions (9);
step two: respectively manufacturing a first conductive type semiconductor charge storage layer and a second conductive type semiconductor base region positioned on the top layer of the first conductive type semiconductor charge storage layer on the front surfaces of the two first conductive type semiconductor drift regions (9) by adopting the same pre-oxidation, photoetching, etching, ion implantation and high-temperature annealing processes;
step three: respectively etching two first conductive type semiconductor charge storage layers to form first grooves by adopting the same photoetching, etching, thermal oxidation and deposition processes, wherein the depth of each first groove is greater than the junction depth of the first conductive type semiconductor charge storage layers; forming a split electrode dielectric layer on the inner wall of the first groove, and then depositing an electrode material in the groove to form a split electrode;
step four: respectively etching two first conduction type semiconductor drift regions (9) to form second grooves by adopting the same photoetching, etching, thermal oxidation and deposition processes, wherein the depth of each second groove is less than the junction depth of the first conduction type semiconductor charge storage layer, and the first grooves and the second grooves are consistent in the extending direction of the top layer of the device; forming a gate dielectric layer on the inner wall of the second groove, depositing an electrode material in the second groove to form a gate electrode, wherein the gate electrode, the gate dielectric layer on the peripheral side of the gate electrode, the split electrode and the split electrode dielectric layer on the peripheral side of the split electrode form a split groove gate structure;
step five: respectively manufacturing a second conductive type semiconductor body contact region and a first conductive type semiconductor emitter region which are mutually independent and arranged in parallel on the top layers of the two second conductive type semiconductor base regions by adopting the same photoetching, etching, ion implantation and high-temperature annealing processes; the extension depth of the first conductive type semiconductor emitter region on the top layer of the second conductive type semiconductor base region is smaller than the extension depth of the second conductive type semiconductor base region on the top layer of the first conductive type semiconductor charge storage layer, the first conductive type semiconductor emitter region is arranged close to the gate electrode and is connected with the gate electrode through the gate dielectric layer,
the first conductivity type semiconductor emitter region (3, 23) and the second conductivity type semiconductor body contact region (4, 24) are positioned in the center of the top layer of the second conductivity type semiconductor base region (5, 25), a part of the split electrode (81, 281) is positioned below the gate electrode (71, 271), and the second conductivity type semiconductor base region (5, 25) is connected with the gate electrode (71, 271) through a gate dielectric layer (72, 272);
step six: forming an isolation dielectric layer on the upper surfaces of the gate electrode and the gate dielectric layer by adopting the same photoetching, etching and deposition processes;
step seven: depositing metal on the surface, and respectively forming emitter metal on the isolation dielectric layer, the second conductive type semiconductor body contact area and the upper surface of the first conductive type semiconductor emitter area by adopting the same photoetching and etching processes;
step eight: and turning over the semiconductor device, thinning the thickness of the first conduction type semiconductor drift region (9) by adopting the same process, and then forming the two completely same semiconductor devices back to back by adopting a bonding process to form the bidirectional trench gate charge storage type IGBT device, thereby completing the preparation of the device.
11. A preparation method of a bidirectional trench gate charge storage type IGBT is characterized by comprising the following steps:
the method comprises the following steps: manufacturing two identical first-conductivity-type semiconductor drift regions (9);
step two: respectively manufacturing a first conductive type semiconductor charge storage layer and a second conductive type semiconductor base region positioned on the top layer of the first conductive type semiconductor charge storage layer on the front surfaces of the two first conductive type semiconductor drift regions (9) by adopting the same pre-oxidation, photoetching, etching, ion implantation and high-temperature annealing processes;
step three: respectively etching two first conductive type semiconductor charge storage layers to form first grooves by adopting the same photoetching, etching, thermal oxidation and deposition processes, wherein the depth of each first groove is greater than the junction depth of the first conductive type semiconductor charge storage layers; forming a split electrode dielectric layer on the inner wall of the first groove, and then depositing an electrode material in the groove to form a split electrode;
step four: respectively etching two first conduction type semiconductor drift regions (9) to form second grooves by adopting the same photoetching, etching, thermal oxidation and deposition processes, wherein the depth of each second groove is less than the junction depth of the first conduction type semiconductor charge storage layer, and the first grooves and the second grooves are consistent in the extending direction of the top layer of the device; forming a gate dielectric layer on the inner wall of the second groove, depositing an electrode material in the second groove to form a gate electrode, wherein the gate electrode, the gate dielectric layer on the peripheral side of the gate electrode, the split electrode and the split electrode dielectric layer on the peripheral side of the split electrode form a split groove gate structure;
step five: respectively manufacturing a second conductive type semiconductor body contact region and a first conductive type semiconductor emitter region which are mutually independent and arranged in parallel on the top layers of the two second conductive type semiconductor base regions by adopting the same photoetching, etching, ion implantation and high-temperature annealing processes; the extension depth of the first conductive type semiconductor emitter region on the top layer of the second conductive type semiconductor base region is smaller than the extension depth of the second conductive type semiconductor base region on the top layer of the first conductive type semiconductor charge storage layer, the first conductive type semiconductor emitter region is arranged close to the gate electrode and is connected with the gate electrode through the gate dielectric layer,
the thickness of the gate electrode (71, 271) connected with the first conductivity type semiconductor emitter region (3, 23) through the gate dielectric layer (72, 272) is larger than the thickness of the gate electrode (71, 271) not connected with the first conductivity type semiconductor emitter region (3, 23);
step six: forming an isolation dielectric layer on the upper surfaces of the gate electrode and the gate dielectric layer by adopting the same photoetching, etching and deposition processes;
step seven: depositing metal on the surface, and respectively forming emitter metal on the isolation dielectric layer, the second conductive type semiconductor body contact area and the upper surface of the first conductive type semiconductor emitter area by adopting the same photoetching and etching processes;
step eight: and turning over the semiconductor device, thinning the thickness of the first conduction type semiconductor drift region (9) by adopting the same process, and then forming the two completely same semiconductor devices back to back by adopting a bonding process to form the bidirectional trench gate charge storage type IGBT device, thereby completing the preparation of the device.
12. The method for manufacturing a bidirectional trench gate charge storage type IGBT according to any one of claims 8 to 11, wherein: the first conductive type semiconductor is a P-type semiconductor, and the second conductive type semiconductor is an N-type semiconductor; or the first conductive type semiconductor is an N-type semiconductor and the second conductive type semiconductor is a P-type semiconductor.
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| CN103794647A (en) * | 2014-02-28 | 2014-05-14 | 电子科技大学 | Bidirectional IGBT device and manufacturing method thereof |
| CN105789289A (en) * | 2016-04-26 | 2016-07-20 | 电子科技大学 | Bidirectional insulated gate bipolar transistor (IGBT) device and manufacturing method thereof |
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| CN102306657A (en) * | 2011-10-13 | 2012-01-04 | 电子科技大学 | Insulated gate bipolar transistor with floating buried layer |
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