CN105870178A - Bi-directional insulated gate bipolar transistor (IGBT) device and fabrication method thereof - Google Patents
Bi-directional insulated gate bipolar transistor (IGBT) device and fabrication method thereof Download PDFInfo
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- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
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- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
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Abstract
The invention relates to a bi-directional insulated gate bipolar transistor (IGBT) device and a fabrication method thereof, belonging to the technical field of a power semiconductor device. A double-split electrode and a dielectric layer between the double-split electrode and gate electrodes are introduced to be arranged at the bottom and on the side surface of gate electrodes in trenches in the front surface and the back surface of the device, thus, the symmetric positive and negative characteristics are achieved on the condition that the threshold voltage of the IGBT device is not affected and the IGBT device is switched on, the positive and negative switching speeds of the bi-directional IGBT device are increased, and the switching loss of the device is reduced; the carrier concentration distribution of the whole N-type drift region is improved, and the positive conduction voltage drop and the average switching loss are improved; and the saturated current density of the device is reduced, the short-circuit safety working region of the device is improved, the concentration of an electric field at the bottom of the trench is improved, the breakdown voltage of the device is increased, and the reliability of the device is further improved. According to the fabrication method of the bi-directional IGBT, provided by the invention, no extra process step is needed, and the fabrication method is compatible with the fabrication method of a traditional bi-directional IGBT.
Description
Technical field
The invention belongs to power semiconductor device technology field, relate to insulated gate bipolar transistor (IGBT), be specifically related to two-way
Trench gate insulated gate bipolar transistor (Bi-directional trench IGBT).
Background technology
Insulated gate bipolar transistor (IGBT) is the novel electric power electric device that a kind of MOS field effect and bipolar transistor are compound
Part.Its existing MOSFET is prone to drive, and controls simple advantage, has again power transistor turns pressure drop low, and on state current is big,
Little advantage is lost, it has also become one of core electron components and parts in modern power electronic circuit, be widely used in such as communication,
The every field of the national economy such as the energy, traffic, industry, medical science, household electrical appliance and Aero-Space.The application of IGBT is to electric power
The lifting of electronic system performance serves particularly important effect.
Transformation of electrical energy is one of basic function of electric device, and according to the difference of load request, electric device can complete exchange and arrive
Direct current (AC-DC), direct current is to exchange (DC-AC), DC-to-DC (DC-DC) and the conversion of AC to AC (AC-AC).
The conversion of AC-AC can be to use indirect conversion i.e. AC-DC-AC mode, it would however also be possible to employ the directly conversion i.e. mode of AC-AC.?
In traditional AC-DC-AC indirect conversion system, it is desirable to have the connection electric capacity (voltage-type conversion) of big capacitance or the connection of big inductance value
Transformation system relatively independent for two parts is connected by inductance (current mode conversion), and this kind of system bulk is big, and cost is high.Additionally,
The service life of electric capacity and inductance is far below power device, this reliability having had a strong impact on system and service life.AC-AC is straight
Connect converting system to avoid in tradition AC-DC-AC system and connect use inductively or capacitively, but require that power switch has two-way opened
Pass ability.Owing to tradition IGBT only has one-way conduction and the function of unidirectional blocking-up, there is two-way admittance two-way blocking-up function
IGBT two-way switch is that the cascaded structure of the IGBT by two groups of reverse parallel connections and fast recovery diode combines and realizes.This side
Case needs a large amount of power chips, adds system cost.Additionally, each chip chamber of internal system needs a large amount of lines, enhance and be
Ghost effect within Tong, affects system reliability.
In order to solve this problem, it is achieved product integrated, industry is by using bonding techniques by two identical groove MOSs
Back-to-back being bonded together of structure successfully achieves the two-way IGBT with two-way admittance and two-way blocking-up function in one chip
(Bi-directional IGBT), as shown in Figure 1.Compared to traditional unidirectional IGBT, by controlling front and back gate voltage,
This two-way IGBT can realize forward and reverse IGBT conducting and the turn-off characteristic of symmetry.Although this structure achieves the merit of two-way switch
Can, but this structure is a kind of non-punch two-way IGBT structure.For non-punch through IGBT structure, in order to avoid device blocks
Time punch-through breakdown, it has to using thicker drift region length, this has had a strong impact on the performance of device.Ask to solve this
Topic, industry further provides two-way IGBT structure as shown in Figure 2, this structure in drift region 10, p-type base 7 and N-it
Between and drift region 10, p-type base 27 and N-between symmetrical have employed one layer of N-type higher than N-drift region 10 doping content
Layer 8 and 28, when either direction works, this two-way IGBT is and has carrier storage layer and the IGBT structure of electric field trapping layer,
Significantly improve the performance of device.For the structure shown in Fig. 2, when IGBT forward or backwards works, due to as carrier
The higher-doped concentration of storage layer and the existence of certain thickness N-type layer 8 or 28 make IGBT device near the current-carrying of emitter terminal
The distribution of sub-concentration is greatly improved, and improves the conductance modulation of N-type drift region, improves the load of whole N-type drift region
Flow the distribution of sub-concentration, make IGBT obtain low forward conduction voltage drop and the forward conduction voltage drop of improvement and the compromise of turn-off power loss.
But, for this two-way IGBT structure, when IGBT forward or backwards works due to the higher-doped as carrier storage layer
Concentration and the existence of certain thickness N-type layer 8 or 28, the breakdown voltage of device significantly reduces, in order to effectively shield as current-carrying
It is pressure that the adverse effect of the N-type layer of son storage layer obtains certain device, needs to use: 1) the deep trench gate degree of depth, make groove
The degree of depth of grid more than the junction depth of N-type layer 8 or 28, but the trench gate degree of depth deep when either direction works not only increase grid-
Emitter capacity, also increases grid-collector capacitance, thus, reducing the switching speed of device, the switch increasing device damages
Consumption, have impact on the conduction voltage drop of device and the compromise characteristic of switching loss；2) little cellular width, makes the spacing between trench gate
Reduce as far as possible, but, when either direction works, highdensity trench MOS structure not only increases the grid capacitance of device,
Reduce the switching speed of device, increase the switching loss of device, have impact on the conduction voltage drop of device and the compromise of switching loss
Characteristic, and, highdensity trench MOS structure adds the saturation current density of device, makes the short-circuit safety operation area of device
It is deteriorated.Additionally, for two-way IGBT structure as illustrated in fig. 1 and 2, gate oxide is by a thermal oxide shape in the trench
Become, the least in order to ensure the thickness of the whole gate oxide of certain threshold voltage, due to the thickness of mos capacitance size Yu oxide layer
Degree is inversely proportional to, and the medium and small gate oxide thickness of traditional two-way IGBT structure greatly increases the grid capacitance of device.It addition, it is little
Gate oxide thickness make the electric field of channel bottom concentrate, the reliability making device is poor.
Summary of the invention
The present invention is directed to the above-mentioned technical problem that existing two-way IGBT device exists, in order at certain device trench depth and groove
In the case of MOS structure density, when two-way IGBT device either direction works, reduce the grid capacitance of device, particularly grid
Pole-collector capacitance, improves the switching speed of device, reduces switching loss, and the saturation current density simultaneously reducing device improves device
The breakdown voltage of device is also improved, and improve the carrier enhancement effect of device emitter terminal further in the short-circuit safety operation area of part,
Improve the carrier concentration profile of whole N-type drift region, improve the compromise of forward conduction voltage drop and switching loss further, passing
On the basis of two-way IGBT device structure of uniting (as illustrated in fig. 1 and 2), the present invention provides a kind of two-way IGBT device (such as Fig. 3
Shown in) and preparation method thereof.In order to simplify description, the most only illustrate as a example by the two-way IGBT device of n-channel, but the present invention
It is equally applicable to the two-way IGBT device of p-channel.
The technical scheme is that a kind of two-way IGBT device, structure cell is as it is shown on figure 3, include that two are symmetricly set in
N-type drift region 10 double-edged N-channel MOS structure；Described front MOS structure includes that front metal electrode 1, front are situated between
Matter layer 2, N+ launch site, front 5, P+ launch site, front 6, p-type base, front 71, front N-type layer 8 and front trench gate
Structure；Described back side MOS structure includes back metal electrode 21, back side first medium layer 22, N+ launch site, the back side 25, the back of the body
P+ launch site, face 26, p-type base, the back side 271, back side N-type layer 28 and backside trench grid structure；It is characterized in that, described
Front trench gate structure runs through front N-type layer 8 along device vertical direction；P-type base, described front 71 is positioned at front trench gate knot
Front N-type layer 8 upper surface of structure side, N+ launch site, front 5 and P+ launch site, front 6 are positioned at p-type base, front side by side
71 upper surfaces, wherein front N+ launch site 5 is connected with front trench gate structure；N+ launch site, front 5 and P+ launch site, front
The upper surface of 6 is connected with front metal electrode 1；Described front trench gate structure includes Split Electrode 31 bottom front, front grid
Electrode 32, face side Split Electrode 33, front gate dielectric layer 41, front second dielectric layer 42, front the 3rd dielectric layer 43,
Front the 4th dielectric layer 44, front the 5th dielectric layer 45；Lead between described positive gate electrode 32 and side, front Split Electrode 33
Cross front the 3rd dielectric layer 43 to connect；Described positive gate electrode 32 by front gate dielectric layer 41 and N+ launch site, front 5 and
P-type base, front 71 connects；Described front MOS structure also has floating p-type base, front 72, described front floating P
Type base 72 is positioned at front N-type layer 8 upper surface of front trench gate structure opposite side；Face side Split Electrode 33 passes through front
Second dielectric layer 42 is connected with floating p-type base, front 72；Bottom described front, Split Electrode 31 is positioned at positive gate electrode 32
With the lower section of face side Split Electrode 33, and bottom front the upper surface degree of depth of Split Electrode 31 less than the knot of front N-type layer 8
Deeply, bottom front, the lower surface degree of depth of Split Electrode 31 is more than the junction depth of front N-type layer 8；Split Electrode bottom described front
The upper surface of 31 and positive gate electrode 32, face side Split Electrode 33 lower surface between be connected by front the 4th dielectric layer 44；
By front the between lower surface and side and N-type drift region 10 and the front N-type layer 8 of Split Electrode 31 bottom described front
Five dielectric layers 45 connect；Floating p-type base, described front 72, front second dielectric layer 42, face side Split Electrode 33, just
The upper surface of face the 3rd dielectric layer 43, positive gate electrode 32 and front gate dielectric layer 41 is connected with front first medium layer 2；Institute
State Split Electrode 31 bottom front, face side Split Electrode 33 and front metal electrode 1 isoelectric level；Described backside trench grid are tied
Structure include back bottom Split Electrode 231, back side gate electrode 232, rear side Split Electrode 233, back side gate dielectric layer 241,
Back side second dielectric layer 242, the back side the 3rd dielectric layer 243, the back side the 4th dielectric layer 244, the back side the 5th dielectric layer 245；Institute
State and back side MOS structure also has floating p-type base, the back side 272；Described back side MOS structure and front MOS structure are along device N
The upper and lower specular of transversal centerline of type drift region 10 is arranged.
Further, as shown in Figure 4, bottom described front the width of Split Electrode 31 more than front second dielectric layer 42, just
Side, face Split Electrode 33, front the 3rd dielectric layer 43, positive gate electrode 32 and the width sum of front gate dielectric layer 41, just make
Face trench gate structure is inverted " t " font；Described back side MOS structure has with front MOS structure along N-type drift region 10 center line
The connection of upper and lower specular and setting.
Further, as it is shown in figure 5, the both sides of described front trench gate structure also have front N+ layer 9, described front N+ layer
The side of 9 is connected with front N-type layer 8, and opposite side and the bottom of front N+ layer 9 are connected with front trench gate structure, front ditch
The upper surface of the front N+ layer 9 of slot grid structure side is connected with the lower surface of floating p-type base, front 72, and front trench gate is tied
The upper surface of the N+ layer 9 of structure opposite side is connected with the lower surface of p-type base, front 71；The both sides of described backside trench grid structure
Also having back side N+ layer 29, described back side MOS structure has with front MOS structure along the N-type drift region 10 upper and lower mirror image of center line
Symmetrical connection and setting.
Further, the N+ layer 9 of described front trench gate structure is only in the side of p-type base, front 71；Described backside trench
The side of the N+ layer 29 of grid structure p-type base 271 the most overleaf.
Further, as shown in Figure 6, the bottom of described face side Split Electrode 33 extend to front bottom Split Electrode 31
Upper surface connect；Described back side MOS structure has with front MOS structure along the N-type drift region 10 upper and lower specular of center line
Connect and arrange.
Further, as it is shown in fig. 7, described N-type layer 8 exists only in the bottom of p-type base 71, and described floating p-type
The junction depth of base 72 is deeper than the degree of depth of the 5th dielectric layer 45, and extends laterally to the bottom of the 5th dielectric layer 45；The described back side
MOS structure has with front MOS structure along the connection of the N-type drift region 10 upper and lower specular of center line and setting.
Further, as shown in Figure 8, described back side MOS structure has with front MOS structure along the rotation of N-type drift region 10 center
Turn symmetrical connection and setting.
Further, described front the 3rd dielectric layer 43, the thickness of the 4th dielectric layer 44 and the 5th dielectric layer 45 is situated between more than grid
Matter layer 41 and the thickness of second dielectric layer 42；The described back side the 3rd dielectric layer 243, the 4th dielectric layer 244 and the 5th medium
The thickness of layer 245 is more than gate dielectric layer 241 and the thickness of second dielectric layer 242.
The manufacture method of a kind of two-way IGBT device, it is characterised in that comprise the following steps:
The first step: choose the two panels parameter N-type identical with specification and monocrystalline silicon piece N-type drift region 10 as device is lightly doped, choosing
The silicon wafer thickness taken is 300～600um, and doping content is 1013～1014Individual/cm3；Use same process respectively at two panels silicon chip surface
By pre-oxidation, photoetching, etching, ion implanting and high-temperature annealing process, at the terminal structure of front side of silicon wafer making devices；
Second step: use same process to grow one layer of field oxygen at two panels silicon chip surface respectively, make active area, regrowth one layer by lithography
First passing through the N-type layer 8/28 of ion implanting N-type impurity making devices after pre-oxygen, the energy of ion implanting is 200～500keV, note
Entering dosage is 1013～1014Individual/cm2；Then by ion implanting p type impurity p-type base 71/271 He of making devices of annealing
Floating p-type base 72/272, described p-type base 71/271 and floating p-type base 72/272 lay respectively at the N of groove both sides
Type charge storage layer 8/28 upper surface；The energy of ion implanting is 60～120keV, and implantation dosage is 1013～1014Individual/cm2, moves back
Fire temperature is 1100-1150 DEG C, and annealing time is 10～30 minutes；
3rd step: using same process to deposit one layer of TEOS at two panels silicon chip surface respectively, thickness is 700～1000nm, makes by lithography
After window, carrying out groove silicon etching, etch groove, the degree of depth of groove exceedes the junction depth of N-type layer 8/28；Etching groove completes
After, by HF solution by the TEOS rinsed clean on surface；
4th step: at 1050 DEG C～1150 DEG C, uses same process to be formed around the groove of two panels silicon chip respectively under the atmosphere of O2
Oxide layer；Then at 750 DEG C～950 DEG C, in groove, accumulation fills polysilicon；
5th step: use same process, in two panels silicon chip surface photoetching the oxide layer of formation in groove in etching the 4th step respectively
And polysilicon, make the upper surface of oxide layer and polysilicon be slightly below the junction depth of p-type base 71/271；The 5th is formed at channel bottom
Dielectric layer 45/245 and the bottom Split Electrode 31/231 being positioned in the 5th dielectric layer 45/245；
6th step: use same process, grows thin oxide layer, shape at trench wall at two panels silicon chip surface again by thermal oxide
The oxidated layer thickness become is less than 120nm；Gate dielectric layer 41/241 is formed near side, p-type base 71/271 at trenched side-wall,
Trenched side-wall forms second dielectric layer 42/242 near side, floating p-type base 72/272；
7th step: use same process, at 750 DEG C～950 DEG C, in the groove of two panels silicon chip surface, accumulation fills polysilicon,
The lower surface degree of depth of the polysilicon formed is more than the junction depth in PXing Ti district 71/271；
8th step: use same process, the partial polysilicon filled in groove in two panels silicon chip surface photoetching, etching the 7th step,
Form gate electrode 32/232 and side Split Electrode 33/233；Described gate electrode 32/232 is located close to p-type base 71/271
Side, side Split Electrode 33/233 is located close to the side of floating p-type base 72/272；
9th step: use same process, deposits at two panels silicon chip surface, divides in gate electrode 32/232 and the side of the 8th step formation
Split between electrode 33/233 filled media in groove and form the 3rd dielectric layer 43/243；
Tenth step: use same process, in two panels silicon chip surface photoetching, sent out by the N+ of ion implanting N-type impurity making devices
Penetrating district 5/25, the energy of ion implanting is 30～60keV, and implantation dosage is 1015～1016Individual/cm2；Described N+ launch site 5/25
It is positioned at p-type base 71/271 upper surface and is connected with trench gate；
11st step: use same process, in two panels silicon chip surface photoetching, by ion implanting p type impurity maker of annealing
The P+ launch site 6/26 of part, the energy of ion implanting is 60～80keV, and implantation dosage is 1015～1016Individual/cm2, annealing temperature is
900 DEG C, the time is 20～30 minutes；Described P+ launch site 6/26 is positioned at p-type base 71/271 side by side with N+ launch site 5/25
Upper surface；
12nd step: use same process, in two panels silicon chip surface dielectric layer deposited, and photoetching, etching formation first medium layer
2/22；Described first medium layer 2/22 is positioned at floating p-type base 72/272, second dielectric layer 42/242, side Split Electrode
33/233, the 3rd dielectric layer 43/243, gate electrode 32/232 and the upper surface of gate dielectric layer 41/241；
13rd step: use same process, deposits metal at two panels silicon chip surface, and photoetching, is etched in N+ launch site 5/25
Metal electrode 1/21 is formed with P+ launch site 6/26 upper surface；
14th step: upset two panels silicon chip, uses the thinning silicon wafer thickness of same process, then identical thinning by these two pieces
After silicon chip back side to the back side, use bonding technology that both are bonded the two-way IGBT device of formation.
Further, in described second step, p-type base 71/271 and floating can be formed the most respectively by increasing lithography step
P-type base 72/272.
Further, described 3rd step by the control of etch process parameters, thus can be formed under groove in trench etch process
The groove structure that portion is wider than top.
Further, in described second step in the forming process of N-type layer 8/28, by increasing a step photoetching and ion implanting work
Skill formed high-dopant concentration N+ layer 9/29 or in the 6th step before oxidation technology by the ion implanting N-type impurity of band angle
Form the N+ layer 9/29 of high-dopant concentration；The upper surface of described N+ layer 9/29 and p-type base 71/271 and floating p-type base
The lower surface of 72/272 connects.
Beneficial effects of the present invention is, it is achieved that symmetrical forward and reverse characteristic, improves forward and reverse the opening of two-way IGBT device
Close speed, reduce the switching loss of device；Improve the carrier concentration profile of whole N-type drift region, improve forward conduction
Pressure drop and the compromise of switching loss；Reduce the saturation current density of device, improve the short-circuit safety operation area of device, improve
Reliability；Improve the breakdown voltage of device, improve the concentration of channel bottom electric field, further increase the reliable of device
Property；Two-way IGBT manufacture method proposed by the invention need not increase extra processing step, the system of IGBT two-way with tradition
Make method compatible.
Accompanying drawing explanation
Fig. 1 is traditional groove-shaped two-way IGBT device structure cell schematic diagram 1；
Fig. 2 is traditional groove-shaped two-way IGBT device structure cell schematic diagram 2；
In Fig. 1-2,1/21 is front/back metal electrode, and 2/22 is front/back dielectric layer, and 3/23 is front/back grid
Electrode, 4/24 is front/back gate dielectric layer, and 5/25 is front/back N+ launch site, and 6/26 launches for front/back P+
District, 7/27 is front/back p-type base, and 8/28 is front/back N-type layer, and 10 is N-drift region；
Fig. 3 is the groove-shaped two-way IGBT device structure cell schematic diagram of embodiment 1；
Fig. 4 is the groove-shaped two-way IGBT device structure cell schematic diagram of embodiment 2；
Fig. 5 is the groove-shaped two-way IGBT device structure cell schematic diagram of embodiment 3；
Fig. 6 is the groove-shaped two-way IGBT device structure cell schematic diagram of embodiment 4；
Fig. 7 is the groove-shaped two-way IGBT device structure cell schematic diagram of embodiment 5；
Fig. 8 is the groove-shaped two-way IGBT device structure cell schematic diagram of embodiment 6；
In Fig. 3 to Fig. 8,1/21 is front/back metal electrode, and 2/22 is front/back dielectric layer, 31/231 be front/
Back bottom Split Electrode, 32/232 is front/back gate electrode, and 33/233 is front/back side Split Electrode, 41/241
For front/back gate dielectric layer, 42/242 is front/back dielectric layer, and 43/243 is front/back dielectric layer, and 44/244 is
Front/back dielectric layer, 45/245 is front/back dielectric layer, and 5/25 is front/back N+ launch site, 6/26 be front/
P+ launch site, the back side, 71/271 is front/back p-type base, and 72/272 is front/back floating p-type base, and 8/28 is
Front/back N-type layer, 9/29 is front/back N+ layer, and 10 is N-drift region；
Fig. 9 be the present invention manufacture method in etching form the device architecture schematic diagram after groove；
Figure 10 be the present invention manufacture method in the thick oxide layer in etching groove and the device architecture schematic diagram after polysilicon；
Figure 11 be the present invention manufacture method in form the device architecture schematic diagram after gate electrode and side Split Electrode in the trench；
Figure 12 be the present invention manufacture method in form the device architecture schematic diagram after metal electrode on surface；
Figure 13 is the device architecture schematic diagram ultimately formed after wafer bonding in the manufacture method of the present invention.
Detailed description of the invention
Below in conjunction with the accompanying drawings, technical scheme is described in detail:
Embodiment 1
A kind of two-way IGBT device, structure cell is as it is shown on figure 3, include that two are symmetricly set in N-type drift region 10 positive and negative two
The N-channel MOS structure in face；Described front MOS structure includes that front metal electrode 1, front dielectric layer 2, front N+ launch
District 5, P+ launch site, front 6, p-type base, front 71, front N-type layer 8 and front trench gate structure；Described back side MOS
Structure includes back metal electrode 21, back side first medium layer 22, N+ launch site, the back side 25, P+ launch site, the back side 26, the back side
P-type base 271, back side N-type layer 28 and backside trench grid structure；It is characterized in that, described front trench gate structure is along device
Vertical direction runs through front N-type layer 8；P-type base, described front 71 is positioned at the front N-type layer 8 of trench gate structure side, front
Upper surface, N+ launch site, front 5 and P+ launch site, front 6 are positioned at p-type base 71, front upper surface, wherein front N+ side by side
Launch site 5 is connected with front trench gate structure；The upper surface of N+ launch site, front 5 and P+ launch site, front 6 and front metal electricity
Pole 1 connects；Described front trench gate structure includes Split Electrode 31 bottom front, positive gate electrode 32, face side Split Electrode
33, front gate dielectric layer 41, front second dielectric layer 42, front the 3rd dielectric layer 43, front the 4th dielectric layer 44, front
5th dielectric layer 45；Between described positive gate electrode 32 and side, front Split Electrode 33 by front the 3rd dielectric layer 43 even
Connect；Described positive gate electrode 32 is connected with N+ launch site, front 5 and p-type base, front 71 by front gate dielectric layer 41；
Also having floating p-type base, front 72 in the MOS structure of described front, floating p-type base, described front 72 is positioned at front groove
Front N-type layer 8 upper surface of grid structure opposite side；Face side Split Electrode 33 is by front second dielectric layer 42 and positive edema over the face
Empty p-type base 72 connects；Bottom described front, Split Electrode 31 is positioned at positive gate electrode 32 and face side Split Electrode 33
Bottom lower section, and front, the upper surface degree of depth of Split Electrode 31 is less than the junction depth of front N-type layer 8, Split Electrode bottom front
The lower surface degree of depth of 31 is more than the junction depth of front N-type layer 8；The upper surface of Split Electrode 31 and front grid electricity bottom described front
Pole 32, face side Split Electrode 33 lower surface between connected by front the 4th dielectric layer 44；Division electricity bottom described front
It is connected by front the 5th dielectric layer 45 between lower surface and side with N-type drift region 10 and the front N-type layer 8 of pole 31；Institute
State floating p-type base, front 72, front second dielectric layer 42, face side Split Electrode 33, front the 3rd dielectric layer 43, just
The upper surface of face gate electrode 32 and front gate dielectric layer 41 is connected with front first medium layer 2；Split Electrode bottom described front
31, face side Split Electrode 33 and front metal electrode 1 isoelectric level.The degree of depth of the described front trench gate electrode 32 formed is big
Junction depth 0.1 in p-type base 71～0.2 micron, the thickness of the described N-type layer 8 of formation is 1～2 micron；The described end formed
The degree of depth of portion's Split Electrode 31 upper surface is less than the junction depth 0.5 of N-type layer 8～1.5 microns, and the degree of depth of lower surface is more than N-type layer 8
Junction depth 0.5～1 micron；The thickness of the described dielectric layer 41 and 42 formed is less than 120 nanometers, the described dielectric layer 43 of formation
Width be 0.5～1 micron, the thickness of the described dielectric layer 44 and 45 of formation is 0.2～0.5 micron.Described backside trench grid
Structure include back bottom Split Electrode 231, back side gate electrode 232, rear side Split Electrode 233, back side gate dielectric layer 241,
Back side second dielectric layer 242, the back side the 3rd dielectric layer 243, the back side the 4th dielectric layer 244, the back side the 5th dielectric layer 245；Institute
State and back side MOS structure also has floating p-type base, the back side 272；Described back side MOS structure and front MOS structure are along device N
The upper and lower specular of transversal centerline of type drift region 10 is arranged.
Above-mentioned two-way IGBT device is by controlling the grid of two symmetrical N-channel MOSs, i.e. positive gate electrode 32 and the back side respectively
Gate electrode 232 is operable with the two-way IGBT pattern that characteristic is full symmetric.Therefore, for convenience of description, main to scheme below
The direction that in 3, electric current is flowed to front metal electrode 1 by back metal electrode 21 illustrates, the operation principle of other direction is complete
Identical, it is only necessary to content corresponding in explanation is interchangeable.The raceway groove of back side MOS structure is made by controlling back side gate electrode 232
Cut-off, MOS structure work in such back side is similar to the colelctor electrode of traditional unidirectional IGBT device；And MOS structure work in front is similar
In the emitter stage of traditional unidirectional IGBT device, being switched on and off of IGBT can be realized by controlling positive gate electrode 32.
In the present embodiment: by the bottom of positive gate electrode 32 in device trenches and lateral leadin and front metal electrode 1 (
Emitter-base bandgap grading) thick dielectric layer between equipotential pair of Split Electrode 31 and 33 and double Split Electrode and gate electrode, do not affecting IGBT
Device threshold voltage and in the case of opening: 1) reduce the degree of depth of gate electrode in groove, substantially reduce and include grid-colelctor electrode
Electric capacity, gate-emitter electric capacity are in interior grid capacitance；2) by the shielding action of double Split Electrodes, grid and collection are shielded
The coupling of electrode, is converted to gate-emitter electric capacity by grid-collector capacitance, substantially reduces grid-collector capacitance, with
Time make to change from grid-collector capacitance by the effect of thick dielectric layer 43 and 44 and the gate-emitter electric capacity that increases is the least
In the gate-emitter electric capacity reduced owing to side Split Electrode 33 introduces, thus substantially reduce and include grid-colelctor electrode electricity
Appearance, gate-emitter electric capacity are in interior grid capacitance.Therefore, present configuration substantially reduces the grid capacitance of device, especially
It is grid-collector capacitance, improves the switching speed of device, reduce the switching loss of device.Additionally, at certain groove
The introducing of MOS structure density downside Split Electrode 33 reduces the density of MOS raceway groove, and by making side Split Electrode 33
P-type base 72 floating at place further reduces the extraction area in hole, improves the carrier enhancement effect of emitter terminal, enters
One step improves the carrier concentration profile of whole N-type drift region, improves the compromise of forward conduction voltage drop and switching loss further；
The MOS gully density reduced at the Split Electrode of side, reduces the saturation current density of device, improves the short circuit peace of device
Full working area, improves reliability；Additionally, due to side Split Electrode 33 and bottom Split Electrode 31 and emitter stage isoelectric level,
In dynamic process opened by device, the quasiconductor table contacted with side Split Electrode 33 and bottom Split Electrode 31 by dielectric layer
Face will not form transoid (floating p-type base 72) and electron accumulation (N-type layer 8 and N-type drift region 10), thus without shape
Become negative differential capacity effect, it is to avoid open electric current, voltage oscillation and the EMI problem in dynamic process, improve reliability；
Meanwhile, by the thick dielectric layer around the Split Electrode of bottom in certain device trench depth and the situation of trench MOS structure density
Under further increase the breakdown voltage of device, improve the concentration of channel bottom electric field, further increase the reliability of device.
Meanwhile, the width of gate electrode 32 can make the present invention have little resistance and highly reliable more than the thickness of the 5th dielectric layer 45
In the case of property, the electron screening effect that gate electrode 32 has been had by Split Electrode 31 bottom channel bottom makes.The present invention carries
The Composite Double division groove structure of confession, the degree of depth of trench gate electrode 32 is more than the degree of depth and the trench gate electrode 32 of p-type base 71
The degree of depth less than the degree of depth of N-type layer 8, on the one hand this reduce grid as far as possible not affecting in the case of IGBT device is opened
Electric capacity, particularly grid-collector capacitance, the existence of the most certain thickness high concentration N-type layer 8 compensate for due to send out
The introducing of emitter-base bandgap grading equipotential bottom Split Electrode 31 makes the decline of carrier concentration near the Split Electrode of bottom, it is to avoid due to
The poor device properties that the introducing of bottom Split Electrode 31 makes the forward conduction voltage drop of device be increased dramatically and causes.
Additionally, the present invention may also be operated in bi-directional MOS pattern: make the ditch of back side MOS structure by controlling back side gate electrode 232
Road is opened, and MOS structure work in such back side is similar to the drain electrode of traditional unidirectional MOS device；And MOS structure work in front is similar
In the source electrode of traditional unidirectional MOS device, realize being switched on and off of MOS by controlling positive gate electrode 32.Two-way when working in
During MOS pattern, the present invention also has operation principle when being similar to two-way IGBT mode of operation and beneficial effect.
Embodiment 2
The two-way IGBT device of one of this example, its structure cell as shown in Figure 4, on the basis of embodiment 1 bottom described front
The width of Split Electrode 31 is more than front second dielectric layer 42, face side Split Electrode 33, front the 3rd dielectric layer 43, front
The width sum of gate electrode 32 and front gate dielectric layer 41, making front composite trench grid structure is inverted " t " font, the most described just
The width of the understructure of face composite trench structure is more than the width of superstructure and extends in N-type layer 8；Described back side MOS
Structure has with front MOS structure along the connection of the N-type drift region 10 upper and lower specular of center line and setting.Extend into N-type layer
The width of the composite trench structure bottom structure in 8/28 is about p-type base 71/271 and floating p-type base 72/272 width
1/4-3/4.Extend into the described understructure in N-type layer 8/28 and further reduce the extraction area of minority carrier, enter
One step improves the carrier of emitter terminal and injects enhancement effect, can obtain more preferable device forward conduction voltage drop and switching loss
Compromise, simultaneously shields the N-type layer adverse effect to device electric breakdown strength further, it is thus achieved that higher device electric breakdown strength and
Reliability.Additionally, the described understructure extended in N-type layer 8/28 shields the coupling of grid and colelctor electrode further,
Reduce grid-collector capacitance, can further improve the switching speed of device, reduce the switching loss of device.
Embodiment 3
The two-way IGBT device of one of this example, its structure cell as it is shown in figure 5, on the basis of embodiment 2 described just/back of the body
Subregion between the understructure of face composite trench structure and p-type base 71/271 and floating p-type base 72/272 also has
Having one layer of N+ layer 9/29, the concentration of described N+ layer 9/29 is tied with composite trench more than concentration and its sidewall of N-type layer 8/28
Structure is connected；The side of described N+ layer 9/29 is connected with front N-type layer 8/28, the opposite side of N+ layer 9/29 and bottom and groove
Grid structure connects, and the upper surface of the N+ layer 9/29 of trench gate structure side is connected with the lower surface of floating p-type base 72/272,
The upper surface of the N+ layer 9/29 of trench gate structure opposite side is connected with the lower surface of p-type base 71/271；The described N+ formed
The width of layer 9/29 is less than the width of the composite trench structure bottom structure extended in N-type layer 8/28.The described N+ formed
Layer 9/29 further reduces the resistance in region between described composite trench structure bottom structure and p-type base 71/271, enters one
Step improves the carrier of emitter terminal and injects enhancement effect, can obtain more preferable device forward conduction voltage drop and the folding of switching loss
In.
Embodiment 4
The two-way IGBT device of one of this example, as shown in Figure 6, as different from Example 1, face side divides its structure cell
The bottom of electrode 33 extends directly into the upper surface of bottom Split Electrode 31, makes side Split Electrode 33 and bottom Split Electrode
31 are joined directly together the grid capacitance reducing device further；Described back side MOS structure has drifts about along N-type with front MOS structure
The connection of the district 10 upper and lower specular of center line and setting.
Embodiment 5
The two-way IGBT device of one of this example, its structure cell as it is shown in fig. 7, unlike embodiment 1-4, described front
N-type layer 8 exists only in the bottom of p-type base 71, and the junction depth of described p-type base 72 is deeper than the deep of the 5th dielectric layer 45
Spend, and the bottom extending laterally to the 5th dielectric layer 45 improves the concentration of channel bottom electric field further, improves the breakdown potential of device
Pressure and reliability；Described back side MOS structure has with front MOS structure along the company of the N-type drift region 10 upper and lower specular of center line
Connect and arrange.
Embodiment 6
The two-way IGBT device of one of this example, its structure cell as shown in Figure 8, unlike embodiment 1-5, the described back side
MOS structure has with front MOS structure along the symmetrical connection of N-type drift region 10 central rotation and setting.
The specific embodiments of present invention process manufacture method is illustrated as a example by the two-way IGBT device of 1200V electric pressure,
Concrete technology manufacture method is as follows:
The first step: choose the two panels parameter N-type identical with specification and monocrystalline silicon piece N-type drift region 10 as device is lightly doped, choosing
The silicon wafer thickness taken is 300～600um, and doping content is 7 × 1013Individual/cm3；Use same process respectively at two panels silicon chip surface
By pre-oxidation, photoetching, etching, ion implanting and high-temperature annealing process, at the terminal structure of front side of silicon wafer making devices；
Second step: use same process to grow the field oxygen that a layer thickness is 0.3～0.5 micron, photoetching at two panels silicon chip surface respectively
Go out active area, after one layer～0.05 micron pre-oxygen of regrowth, first pass through the N-type layer 8/28 of ion implanting N-type impurity making devices,
The energy of ion implanting is 500keV, and implantation dosage is 5 × 1013Individual/cm2；Then by ion implanting p type impurity the system of annealing
Make p-type base 71/271 and the floating p-type base 72/272 of device, described p-type base 71/271 and floating p-type base
72/272 N-type charge storage layer 8/28 upper surface laying respectively at groove both sides；The energy of ion implanting is 120keV, injects
Dosage is 1 × 1014Individual/cm2, annealing temperature is 1100-1150 DEG C, and annealing time is 10～30 minutes；The knot of N-type layer 8/28
Deep deeper than the junction depth of p-type base 71/,271 1～2 micron；
3rd step: using same process to deposit one layer of TEOS at two panels silicon chip surface respectively, thickness is 800nm, makes window by lithography
After, carrying out groove (trench) silicon etching, etch groove, the junction depth 0.5～1 that the degree of depth of groove exceedes N-type layer 8/28 is micro-
Rice；After etching groove completes, by HF solution by the TEOS rinsed clean on surface；
4th step: at 1050 DEG C～1150 DEG C, O2Atmosphere under use same process respectively around two panels silicon chip groove formed thickness
It it is the oxide layer of 0.2～0.5 micron；Then at 750 DEG C～950 DEG C, in groove, accumulation fills polysilicon；
5th step: use same process, in two panels silicon chip surface photoetching the oxide layer of formation in groove in etching the 4th step respectively
And polysilicon, make the upper surface of oxide layer and polysilicon less than the upper surface 0.2 of N-type layer 8/28～0.3 micron；
6th step: use same process, grows thin oxide layer, shape at trench wall at two panels silicon chip surface again by thermal oxide
The oxidated layer thickness become is less than 120nm；
7th step: use same process, at 750 DEG C～950 DEG C, in the groove of two panels silicon chip surface, accumulation fills polysilicon,
The lower surface degree of depth of polysilicon formed exceedes the junction depth 0.1 of p-type base 71/271～0.2 micron；
8th step: use same process, the partial polysilicon filled in groove in two panels silicon chip surface photoetching, etching the 7th step,
Form gate electrode 32/232 and side Split Electrode 33/233；
9th step: use same process, deposits at two panels silicon chip surface, divides in gate electrode 32/232 and the side of the 8th step formation
Split between electrode 33/233 filled media in groove and form the 3rd dielectric layer 43/243；
Tenth step: use same process, in two panels silicon chip surface photoetching, sent out by the N+ of ion implanting N-type impurity making devices
Penetrating district 5/25, the energy of ion implanting is 40keV, and implantation dosage is 1 × 1015Individual/cm2；
11st step: use same process, in two panels silicon chip surface photoetching, by ion implanting p type impurity maker of annealing
The P+ launch site 6/26 of part, the energy of ion implanting is 60keV, and implantation dosage is 5 × 1015Individual/cm2, annealing temperature is 900 DEG C,
Time is 30 minutes；
12nd step: use same process, in two panels silicon chip surface dielectric layer deposited, and photoetching, etching formation first medium layer
2/22；
13rd step: use same process, deposits metal, and photoetching, etching formation metal electrode 1/21 at two panels silicon chip surface；
14th step: upset two panels silicon chip, uses the thickness of the thinning silicon wafer thickness of same process to 60～70 microns, then by this
Two pieces identical thinning after silicon chip back side to the back side, use bonding technology that both are bonded the two-way IGBT device of formation.
I.e. it is prepared into two-way IGBT device.
Further, described 3rd step by the control of etch process parameters, thus can be formed under groove in trench etch process
The groove structure that portion is wider than top, i.e. forms device architecture as shown in Figure 4.
Further, in described second step in the forming process of N-type layer 8/28, by increasing a step photoetching and ion implanting work
Skill formed high-dopant concentration N+ layer 9/29 or in the 6th step before oxidation technology by the ion implanting N-type impurity of band angle
Form the N+ layer 9/29 of high-dopant concentration；The upper surface of described N+ layer 9/29 and p-type base 71/271 and floating p-type base
The lower surface of 72/272 connects, and i.e. forms device architecture as shown in Figure 5.
Further, can increase by a step etching technics before the 7th step polysilicon deposit, etching removes side Split Electrode 33/233 time
Oxide layer, i.e. form device architecture as shown in Figure 6.
Further, in described second step, only can form N-type layer 8 71/271 time in p-type base by increasing lithography step,
And form p-type base 71/271 and floating p-type base 72/272 the most respectively by increasing lithography step, i.e. formed such as Fig. 7
Shown device architecture.
Further, described dielectric layer 41/241,42/242,43/243,44/244 and the material of 45/245 can identical also
Can be different.
Fig. 3-Fig. 8 only gives several specific implementations based on core thinking of the present invention, and those skilled in the art are according to ability
Territory common knowledge it should be known that in the two-way IGBT device that the present invention provides, semi-conducting material used by device can use silicon (Si),
Carborundum (SiC), GaAs (GaAs) or gallium nitride (GaN) etc. are achieved, and dielectric material used can use dioxy
SiClx (SiO2), hafnium oxide (HfO2) or silicon nitride (Si3N4) etc. be achieved, manufacturing technology steps also dependent on
It is actually needed and is adjusted.
Claims (7)
1. a two-way IGBT device, is symmetricly set in N-type drift region (10) double-edged N-channel MOS including two
Structure；Described front MOS structure include front metal electrode (1), front dielectric layer (2), N+ launch site, front (5),
P+ launch site, front (6), p-type base, front (71), front N-type layer (8) and front trench gate structure；Described back side MOS
Structure include back metal electrode (21), back side dielectric layer (22), N+ launch site, the back side (25), P+ launch site, the back side (26),
P-type base, the back side (271), back side N-type layer 28 and backside trench grid structure；It is characterized in that, described front trench gate is tied
Structure runs through front N-type layer (8) along device vertical direction；P-type base, described front (71) is just being positioned at trench gate structure side, front
Face N-type layer (8) upper surface, N+ launch site, front (5) and P+ launch site, front (6) are positioned at p-type base, front (71) side by side
Upper surface, wherein front N+ launch site (5) are connected with front trench gate structure；N+ launch site, front (5) and front P+
The upper surface of launch site (6) is connected with front metal electrode (1)；Described front trench gate structure includes division electricity bottom front
Pole (31), positive gate electrode (32), face side Split Electrode (33), front gate dielectric layer (41), front second dielectric layer
(42), front the 3rd dielectric layer (43), front the 4th dielectric layer 44, front the 5th dielectric layer (45)；Described front grid electricity
Connected by front the 3rd dielectric layer (43) between pole (32) and side, front Split Electrode (33)；Described positive gate electrode
(32) it is connected with N+ launch site, front (5) and p-type base, front (71) by front gate dielectric layer (41)；Described front
Also having floating p-type base, front (72) in MOS structure, described floating p-type base, front (72) is positioned at front trench gate
Front N-type layer (8) upper surface of structure opposite side；Face side Split Electrode (33) by front second dielectric layer (42) with just
Edema over the face sky p-type base (72) connects；Bottom described front, Split Electrode (31) is positioned at positive gate electrode (32) and face side
The lower section of Split Electrode (33), and bottom front, the upper surface degree of depth of Split Electrode (31) is less than the junction depth of front N-type layer (8),
Bottom front, the lower surface degree of depth of Split Electrode (31) is more than the junction depth of front N-type layer (8)；Split Electrode (31) bottom described front
Upper surface and positive gate electrode (32), face side Split Electrode (33) lower surface between by front the 4th dielectric layer (44)
Connect；The lower surface of Split Electrode (31) and side and N-type drift region (10) and front N-type layer (8) bottom described front
Between by front the 5th dielectric layer (45) connect；Described floating p-type base, front (72), front second dielectric layer (42),
Face side Split Electrode (33), front the 3rd dielectric layer (43), positive gate electrode (32) and front gate dielectric layer (41)
Upper surface is connected with front first medium layer (2)；Split Electrode (31), face side Split Electrode (33) bottom described front
With front metal electrode (1) isoelectric level；Described backside trench grid structure includes back bottom Split Electrode (231), back side grid electricity
Pole (232), rear side Split Electrode (233), back side gate dielectric layer (241), back side second dielectric layer (242), the back side
Three dielectric layers (243), the back side the 4th dielectric layer (244), the back side the 5th dielectric layer (245)；In the MOS structure of the described back side also
There is floating p-type base, the back side (272)；Described back side MOS structure and front MOS structure are along device N-type drift region (10)
Transversal centerline setting symmetrical above and below.
The two-way IGBT device of one the most according to claim 1, it is characterised in that bottom described front Split Electrode (31)
Width more than front second dielectric layer (42), face side Split Electrode (33), front the 3rd dielectric layer (43), front grid electricity
Pole (32) and the width sum of front gate dielectric layer (41), making front trench gate structure is inverted " t " font；The described back side
MOS structure and front MOS structure are along the transversal centerline setting symmetrical above and below of N-type drift region (10).
The two-way IGBT device of one the most according to claim 2, it is characterised in that the two of described front trench gate structure
Side also has front N+ layer (9), and the side of described front N+ layer (9) is connected with front N-type layer (8), N+ layer (9)
Opposite side and bottom are connected with front trench gate structure, the upper surface of the N+ layer (9) of trench gate structure side, front and floating P
The lower surface of type base (72) connects, the upper surface of the N+ layer (9) of front trench gate structure opposite side and p-type base (71)
Lower surface connect；The both sides of described backside trench grid structure also have back side N+ layer (29), described back side MOS structure with
Front MOS structure is along the transversal centerline setting symmetrical above and below of device N-type drift region (10).
4. according to the two-way IGBT device of one described in claim 1,2 and 3 any one, it is characterised in that described just
Edema over the face sky p-type base (72) extends downward its junction depth along device vertical direction and is deeper than the junction depth in front the 5th dielectric layer (45),
The part that floating p-type base, front (72) downwardly extends covers the front N-type being positioned at lower section, floating p-type base, front (72)
Layer (8), floating p-type base, front (72) exceedes the parts transversely of front the 5th dielectric layer (45) junction depth and extends to front
The bottom of five dielectric layers (45), the floating p-type base, the back side (272) in the MOS structure of the described back side is tied with front MOS
Floating p-type base, front (72) in structure is arranged along the upper and lower specular of transversal centerline of device N-type drift region (10).
The two-way IGBT device of one the most according to claim 4, it is characterised in that described face side Split Electrode (33)
Bottom extend to be connected with the upper surface of Split Electrode bottom front (31)；Described back side MOS structure is tied with front MOS
Structure is along the transversal centerline setting symmetrical above and below of device N-type drift region (10).
6. the manufacture method of a two-way IGBT device, it is characterised in that comprise the following steps:
The first step: choose the two panels parameter N-type identical with specification and monocrystalline silicon piece N-type drift region as device is lightly doped, choose
Silicon wafer thickness be 300～600um, doping content is 1013～1014Individual/cm3；Use same process respectively at two panels silicon chip surface
By pre-oxidation, photoetching, etching, ion implanting and high-temperature annealing process, at the terminal structure of front side of silicon wafer making devices；
Second step: use same process to grow one layer of field oxygen at two panels silicon chip surface respectively, make active area, regrowth one layer by lithography
First passing through the N-type layer of ion implanting N-type impurity making devices after pre-oxygen, the energy of ion implanting is 200～500keV, injects
Dosage is 1013～1014Individual/cm2；Then by ion implanting p type impurity the p-type base of making devices of annealing and floating p-type
Base, described p-type base and floating p-type base lay respectively at the N-type charge storage layer upper surface of groove both sides；Ion implanting
Energy be 60～120keV, implantation dosage is 1013～1014Individual/cm2, annealing temperature is 1100-1150 DEG C, and annealing time is
10～30 minutes；
3rd step: using same process to deposit one layer of TEOS at two panels silicon chip surface respectively, thickness is 700～1000nm, photoetching
After going out window, carrying out groove silicon etching, etch groove, the degree of depth of groove exceedes the junction depth of N-type layer；After etching groove completes,
By HF solution by the TEOS rinsed clean on surface；
4th step: at 1050 DEG C～1150 DEG C, uses same process to be formed around the groove of two panels silicon chip respectively under the atmosphere of O2
Thick oxide layer；Then at 750 DEG C～950 DEG C, in groove, accumulation fills polysilicon；
5th step: use same process, in two panels silicon chip surface photoetching the oxide layer of formation in groove in etching the 4th step respectively
And polysilicon, make the upper surface of oxide layer and polysilicon be slightly below the junction depth of p-type base；The 5th dielectric layer is formed at channel bottom
With the bottom Split Electrode being positioned in the 5th dielectric layer；
6th step: use same process, grows thin oxide layer, shape at trench wall at two panels silicon chip surface again by thermal oxide
The oxidated layer thickness become is less than 120nm；Gate dielectric layer is formed near side, p-type base at trenched side-wall, close at trenched side-wall
Side, floating p-type base forms second dielectric layer；
7th step: use same process, at 750 DEG C～950 DEG C, in the groove of two panels silicon chip surface, accumulation fills polysilicon,
The lower surface degree of depth of the polysilicon formed is more than the junction depth in PXing Ti district；
8th step: use same process, the partial polysilicon filled in groove in two panels silicon chip surface photoetching, etching the 7th step,
Form gate electrode and side Split Electrode；Described gate electrode is located close to the side of p-type base, and side Split Electrode is located close to
The side of floating p-type base；
9th step: use same process, deposits at two panels silicon chip surface, at gate electrode and the side Split Electrode of the 8th step formation
Between in groove filled media form the 3rd dielectric layer；
Tenth step: use same process, in two panels silicon chip surface photoetching, by the N+ of ion implanting N-type impurity making devices
Launch site, the energy of ion implanting is 30～60keV, and implantation dosage is 1015～1016Individual/cm2；Described N+ launch site is positioned at P
Type base upper surface is also connected with trench gate；
11st step: use same process, in two panels silicon chip surface photoetching, by ion implanting p type impurity maker of annealing
The P+ launch site of part, the energy of ion implanting is 60～80keV, and implantation dosage is 1015～1016Individual/cm2, annealing temperature is 900 DEG C,
Time is 20～30 minutes；Described P+ launch site and N+ launch site are positioned at p-type base upper surface side by side；
12nd step: use same process, in two panels silicon chip surface dielectric layer deposited, and photoetching, etching formation first medium layer；
Described first medium is positioned at floating p-type base, second dielectric layer, side Split Electrode, the 3rd dielectric layer, gate electrode and grid and is situated between
The upper surface of matter layer；
13rd step: use same process, deposits metal at two panels silicon chip surface, and photoetching, is etched in N+ launch site and P+
Launch site upper surface forms metal electrode；
14th step: upset two panels silicon chip, uses the thinning silicon wafer thickness of same process, then identical thinning by these two pieces
After silicon chip back side to the back side, use bonding technology that both are bonded the two-way IGBT device of formation.
The manufacture method of a kind of two-way IGBT device the most according to claim 6, it is characterised in that in described 3rd step,
Can pass through in trench etch process by the control of etch process parameters, thus form the groove structure that lower trench is wider than top.
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| CN106206705A (en) * | 2016-09-09 | 2016-12-07 | 电子科技大学 | A kind of RC IGBT with double grid |
| CN107731901A (en) * | 2017-11-20 | 2018-02-23 | 电子科技大学 | A kind of reverse blocking IGBT |
| CN107768435A (en) * | 2017-10-20 | 2018-03-06 | 电子科技大学 | A kind of two-way IGBT and its manufacture method |
| CN108122962A (en) * | 2017-12-04 | 2018-06-05 | 西南交通大学 | A kind of insulated gate bipolar transistor |
| CN112510036A (en) * | 2020-10-27 | 2021-03-16 | 广东美的白色家电技术创新中心有限公司 | IGBT device and intelligent power module |
| CN114388613A (en) * | 2021-12-30 | 2022-04-22 | 电子科技大学 | Bidirectional blocking power MOS device and manufacturing method thereof |
| CN116153991A (en) * | 2023-04-21 | 2023-05-23 | 上海陆芯电子科技有限公司 | Dual-trench-gate RC-IGBT and preparation method thereof |
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| CN114388613B (en) * | 2021-12-30 | 2023-09-01 | 电子科技大学 | Bidirectional blocking power MOS device and manufacturing method thereof |
| CN114388613A (en) * | 2021-12-30 | 2022-04-22 | 电子科技大学 | Bidirectional blocking power MOS device and manufacturing method thereof |
| CN116153991A (en) * | 2023-04-21 | 2023-05-23 | 上海陆芯电子科技有限公司 | Dual-trench-gate RC-IGBT and preparation method thereof |
| CN116153991B (en) * | 2023-04-21 | 2023-06-23 | 上海陆芯电子科技有限公司 | Dual-trench-gate RC-IGBT and preparation method thereof |
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