CN113838917B - Three-dimensional separation gate groove charge storage type IGBT and manufacturing method thereof - Google Patents

Three-dimensional separation gate groove charge storage type IGBT and manufacturing method thereof Download PDF

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CN113838917B
CN113838917B CN202111116191.4A CN202111116191A CN113838917B CN 113838917 B CN113838917 B CN 113838917B CN 202111116191 A CN202111116191 A CN 202111116191A CN 113838917 B CN113838917 B CN 113838917B
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charge storage
gate electrode
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CN113838917A (en
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张金平
朱镕镕
涂元元
李泽宏
张波
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University of Electronic Science and Technology of China
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Abstract

The invention relates to a three-dimensional split gate groove charge storage type IGBT and a manufacturing method thereof, and belongs to the technical field of power semiconductor devices. The invention introduces a P-type buried layer and a separated gate electrode with the same electric potential as the emitter metal on the basis of the traditional CSTBT, effectively eliminates the influence of the doping concentration of an N-type charge storage layer on the breakdown characteristic of a device through charge compensation, and simultaneously can reduce the conduction voltage drop by improving the doping concentration of the N-type charge storage layer. According to the invention, the gate electrode and the separated gate electrode are placed in the same groove, and the gate electrodes are arranged at intervals along the Z-axis direction, so that the density of the groove can be reduced on one hand, and a parasitic PMOS structure can be formed in a cell on the other hand, thereby being beneficial to reducing the saturation current density and improving the short-circuit safe working area; meanwhile, the gate capacitance and the gate charge are reduced, the switching loss of the device is reduced, the compromise relation between the forward conduction voltage drop Vceon and the turn-off loss Eoff is further improved, in addition, the current uniformity is favorably improved, and the reliability of the device is improved.

Description

Three-dimensional split gate groove charge storage type IGBT and manufacturing method thereof
Technical Field
The invention belongs to the technical field of power semiconductor devices, and particularly relates to a three-dimensional split gate groove charge storage type IGBT and a manufacturing method thereof.
Background
Insulated Gate Bipolar Transistors (IGBTs) are one of the fastest growing electronic power devices today. Compared with the traditional transistor and MOSFET, the transistor and MOSFET have the advantages of both the transistor and MOSFET, and have the advantages of high input impedance, small control power, simple driving circuit, high switching speed and small switching loss of MOSFET; the bipolar power transistor has the advantages of large current density, low saturation voltage, strong current processing capability and good stability, and is widely applied to the fields of high voltage, large current and the like.
Since the IGBTs were invented in the late 20 th century, 70 s and early 80 s, efforts have been made to improve the performance of IGBTs, and through development of thirty years, the process level of manufacturing the structure of the IGBT device has been continuously improved. A trench gate charge storage type insulated gate bipolar transistor (CSTBT) is characterized in that a hole potential barrier is introduced below a P-type base region by introducing an N-type charge storage layer with higher doping concentration and certain thickness below the P-type base region, so that the carrier concentration distribution of the whole N-drift region is improved, the conductivity modulation effect of the N-drift region is enhanced, and the IGBT obtains lower forward conduction voltage drop and better compromise between the forward conduction voltage drop and turn-off loss. With the higher doping concentration of the N-type charge storage layer, the higher the CSTBT conductivity modulation effect is improved, and the forward conduction characteristic of the device is better. However, with the increasing doping concentration of the N-type charge storage layer, the breakdown voltage of the CSTBT device is remarkably reduced. In order to effectively shield the adverse effect of the N-type charge storage layer on the breakdown voltage of the device and obtain a high withstand voltage, the following methods are mainly used: (1) The adverse effect of the N-type charge storage layer is shielded by increasing the depth of the trench gate, which is generally greater than the depth of the N-type charge storage layer. However, the deep trench depth increases the coupling area between the gate and the collector and the emitter, increases the gate capacitance, and reduces the switching speed of the device. (2) The distance between the trench gates is reduced, and the cell width is reduced. However, the method can increase the channel density, and on one hand, the increase of the channel density can increase the saturation current and deteriorate the Short Circuit Safe Operating Area (SCSOA) of the device; on the other hand, the gate capacitance is increased, so that the switching speed of the device is reduced, and the switching loss is increased.
Disclosure of Invention
The invention aims to solve the technical problem in the prior art and provides a three-dimensional separated gate groove charge storage type IGBT and a manufacturing method thereof.
In order to solve the above technical problem, an embodiment of the present invention provides a three-dimensional split gate trench charge storage type IGBT, where a three-dimensional rectangular coordinate system defines a three-dimensional direction of a device: defining the transverse direction of the device as the X-axis direction, the vertical direction of the device as the Y-axis direction, and the longitudinal direction of the device, namely the third dimension direction, as the Z-axis direction, wherein the cellular structure comprises: the back collector metal 11, the P-type collector region 10, the N-type field stop layer 9 and the N-drift region 8 are sequentially stacked from bottom to top along the Y-axis direction; the top layer of the N-drift region 8 is provided with P-type buried layers 12 distributed at intervals along the Z-axis direction, the N-drift region 8 is provided with an N-type charge storage layer 6 and a groove structure which are in side contact with each other along the X-axis direction, and the N-type charge storage layer 6 is arranged on the P-type buried layers 12; along the Y-axis direction, the top layer of the N-type charge storage layer 6 is provided with a P-type base region 5; the top layer of the P-type base region 5 is provided with an N + emitter region 3 and a P + emitter region 4, the side surfaces of which are mutually contacted, along the Z-axis direction, and the N + emitter region 3 and the P + emitter region 4 are distributed in an alternating mode;
the depth of the groove structure is greater than the junction depth of the P-type buried layer 12, and the groove structure comprises a gate electrode 71, a gate dielectric layer 72, a separation gate electrode 73 and a separation gate dielectric layer 74; along the Z-axis direction, the gate electrodes 71 are distributed on the top layer of the separation gate electrode 73 in an interval mode, and the depth of the gate electrodes 71 is larger than the junction depth of the P-type base region 5 and smaller than the junction depth of the N-type charge storage layer 6; the gate electrode 71 and the split gate electrode 73 are separated by the gate dielectric layer 72; the gate electrode 71 is connected with the N + emitter region 3, the P-type base region 5 and the N-type charge storage layer 6 through the gate dielectric layer 72; the depth of the lower surface of the separation gate electrode 73 is greater than the junction depth of the P-type buried layer 12; the separation gate electrode 73 is connected with the P + emitter region 4, the P-type base region 5, the N-type charge storage layer 6, the P-type buried layer 12 and the N-drift region 8 through the separation gate dielectric layer 74; the thickness of the separation gate dielectric layer 74 is greater than or equal to the thickness of the gate dielectric layer 72;
the N + emitter region 3 and the P + emitter region 4 further have an emitter metal 1 thereon, and the split gate electrode 73 is equipotential to the emitter metal 1.
To solve the above technical problem, an embodiment of the present invention provides a three-dimensional split-gate trench charge storage IGBT, where a three-dimensional rectangular coordinate system defines a three-dimensional direction of a device: defining the transverse direction of the device as the X-axis direction, the vertical direction of the device as the Y-axis direction, and the longitudinal direction of the device, namely the third dimension direction, as the Z-axis direction, wherein the cellular structure comprises: the back collector metal 11, the P-type collector region 10, the N-type field stop layer 9 and the N-drift region 8 are sequentially stacked from bottom to top along the Y-axis direction, and the top layer of the N-drift region 8 is provided with P-type buried layers 12 distributed at intervals along the Z-axis direction; an N-type charge storage layer 6 and a groove structure with side surfaces mutually contacted are arranged on the N-drift region 8 along the X-axis direction, and the N-type charge storage layer 6 is arranged on the P-type buried layer 12; along the Y-axis direction, the top layer of the N-type charge storage layer 6 is provided with a P-type base region 5; in the Z-axis direction, N + emitter regions 3 distributed at intervals are arranged on the top layer of the P-type base region 5, the P-type base region 5 is arranged between the adjacent N + emitter regions 3, and the upper surfaces of the N + emitter regions 3 and the P-type base regions 5 are flush;
the depth of the groove structure is greater than the junction depth of the P-type buried layer 12, and the groove structure comprises a gate electrode 71, a gate dielectric layer 72, a separation gate electrode 73 and a separation gate dielectric layer 74; along the Z-axis direction, the gate electrodes 71 are distributed on the top layer of the separation gate electrode 73 in an interval mode, and the depth of the gate electrodes 71 is larger than the junction depth of the P-type base region 5 and smaller than the junction depth of the N-type charge storage layer 6; the gate electrode 71 and the split gate electrode 73 are separated by the gate dielectric layer 72; the gate electrode 71 is connected with the N + emitter region 3, the P-type base region 5 and the N-type charge storage layer 6 through the gate dielectric layer 72; the depth of the lower surface of the separation gate electrode 73 is greater than the junction depth of the P-type buried layer 12; the separation gate electrode 73 is separated from the P-type base region 5, the N-type charge storage layer 6, the P-type buried layer 12 and the N-drift region 8 through the separation gate dielectric layer 74; the thickness of the separation gate dielectric layer 74 is greater than or equal to the thickness of the gate dielectric layer 72;
emitter metal 1 is arranged on the N + emitter region 3, schottky contact metal 2 is arranged on the P-type base region 5 between the adjacent N + emitter regions 3, and the split gate electrode 73 and the Schottky contact metal 2 are equipotential with the emitter metal 1.
On the basis of the technical scheme, the invention can be further improved as follows.
Further, the semiconductor device also comprises a floating P-type doped region 13; in the direction of the X axis, the floating P-type doped region 13 is located at one side of the trench structure, and the floating P-type doped region 13 is isolated from the gate electrode 71 by the gate dielectric layer 72 and isolated from the isolated gate electrode 73 by the isolated gate dielectric layer 74.
Further, the depth of the lower surface of the floating P-type doped region 13 is equal to or greater than the depth of the trench structure.
Further, in the X-axis direction, the width of the gate electrode 71 plus the gate dielectric layer 72 is smaller than the width of the trench structure, the separation gate electrode 73 is arranged between the gate dielectric layer 72 and the floating P-type doped region 13, and the separation gate electrode 73 is connected with the floating P-type doped region 13 through the separation gate dielectric layer 74.
Further, the doping concentration of the N-type charge storage layer 6 is gradually changed from a region close to the trench structure to a region far from the trench structure, wherein the doping concentration of the region close to the trench structure is low, and the doping concentration of the region far from the trench structure is high.
Furthermore, a variable doping technology or a partition doping technology is adopted to realize the gradual change of the doping concentration of the N-type charge storage layer 6.
Further, the bottom of the trench structure is also provided with a P-type layer 16.
Further, super junction P column 14 and super junction N column 15 with sides in contact with each other are provided in N-drift region 8; the super-junction P-column 14 and the super-junction N-column 15 satisfy the charge balance requirement, the first portion of the trench structure and the N-type charge storage layer 6 are located on the super-junction N-column 15, and the second portion of the trench structure and the floating P-type doped region 13 are located on the super-junction P-column 14.
Further, the semiconductor material used by the device is Si, siC, gaAs, gaN, ga 2 O 3 Any one or more of AlN and diamond.
Furthermore, the device structure is not only suitable for IGBT devices, but also suitable for MOSFET devices by replacing the P-type collector region 10 on the back of the device with N-type doping.
In order to solve the above technical problem, an embodiment of the present invention provides a method for manufacturing a three-dimensional split-gate trench charge storage type IGBT, where a three-dimensional rectangular coordinate system is used to define a three-dimensional direction of a device: defining the transverse direction of the device as the X-axis direction, the vertical direction of the device as the Y-axis direction and the longitudinal direction of the device, namely the third dimension direction, as the Z-axis direction, and comprising the following steps:
step 1: selecting a lightly doped FZ silicon wafer to form an N-drift region 8 of the device;
step 2: growing a field oxide layer on the surface of the FZ silicon wafer, photoetching to obtain an active region, growing a pre-oxide layer, and forming P-type buried layers 12 distributed at intervals on the upper layer of the N-drift region 8 through masking, photoetching and ion implantation of P-type impurities; an N-type charge storage layer 6 is prepared on the upper surfaces of the N-drift region 8 and the P-type buried layer 12 through ion implantation of N-type impurities; injecting P-type impurities into the upper surface of the N-type charge storage layer 6 through ions and annealing to obtain a P-type base region 5;
and step 3: depositing a protective layer on the surface of the silicon wafer, photoetching a window to perform groove silicon etching, and etching on one side of the top layer of the N-drift region 8 along the X-axis direction to form a separation gate groove, wherein the depth of the separation gate groove is greater than the junction depth of the P-type buried layer 12;
and 4, step 4: forming a separation gate dielectric layer 74 at the bottom and the side wall of the separation gate groove, and depositing polycrystalline silicon on the separation gate dielectric layer 74 to form a separation gate electrode 73;
and 5: depositing a protective layer on the surface of a silicon wafer, photoetching a window, and etching part of the polycrystalline silicon and the separation gate dielectric layer, thereby forming gate grooves distributed at intervals on the top layer of the separation gate groove along the Z-axis direction, wherein separation gate electrodes 73 are arranged between the gate grooves, and the depth of the gate grooves is greater than the junction depth of the P-type base region 5 and less than the junction depth of the N-type charge storage layer 6;
step 6: forming a gate dielectric layer 72 at the bottom and the side wall of the gate trench, depositing polysilicon on the gate dielectric layer 72 to form a gate electrode 71, wherein the gate electrode 71 is isolated from the separation gate electrode 73 through the gate dielectric layer 72, and the thickness of the gate dielectric layer 72 is less than or equal to that of the separation gate dielectric layer 74;
and 7: respectively injecting N-type impurities and P-type impurities into the top layer of the P-type base region 5 through photoetching and ion injection processes, so that N + emitter regions 3 and P + emitter regions 4 which are alternately arranged side by side and are mutually contacted at the side surfaces are formed on the top layer of the P-type base region 5 along the Z-axis direction; along the X-axis direction, one side of the N + emission region 3 is connected with a gate electrode 71 through a gate dielectric layer 72, and one side of the P + emission region 4 is connected with a separation gate electrode 73 through a separation gate dielectric layer 74;
and 8: depositing metal on the surface of the device, and forming emitter metal 1 on the N + emitting region 3 and the P + emitting region 4 by adopting photoetching and etching processes;
and step 9: turning over the silicon wafer, reducing the thickness of the silicon wafer, injecting N-type impurities into the back of the silicon wafer, and manufacturing an N-type field stop layer 9 of the device through multiple times of laser annealing;
step 10: injecting P-type impurities into the back of the N-type field stop layer 9 to form a P-type collector region 10, and performing ion activation through multiple times of laser annealing; and then a metal is deposited on the back surface to form a collector metal 11.
Further, the thickness of the FZ silicon wafer is 200-300 μm, or the thickness of the separation gate dielectric layer 74 is 0.1-0.5 μm, or the thickness of the gate dielectric layer 72 is 0.1-0.3 μm, the thickness of the emitter metal 1 is 1-6 μm, or the thickness of the N-type field stop layer is 1-5 μm, or the thickness of the P-type collector region is 0.5-2 μm, or the thickness of the collector metal 11 is 1-6 μm.
Further, the doping concentration of the N-drift region 8 is 10 14 ～10 15 Per cm 3 Or the doping concentration of the P-type buried layer 12 is 10 16 ～10 18 /cm 3 Or, the doping concentration of the N-type charge storage layer 6 is 10 15 ～10 17 /cm 3 Or the doping concentration of the P-type base region 5 is 10 16 ～10 17 /cm 3 。
Furthermore, the semiconductor material used by the device is Si, siC, gaAs, gaN and Ga 2 O 3 AlN and diamond, each of which may be of the same semiconductor material or a different semiconductor material.
The working principle of the invention is detailed as follows:
in order to solve the contradiction between the breakdown characteristic and the conduction characteristic of the device caused by the improvement of the doping concentration of the N-type charge storage layer and simultaneously reduce the adverse effect of the increase of the gate capacitance and the saturation current of the device caused by the large depth of a trench gate and the large channel density, the invention introduces a separation gate electrode 73 with the same potential as an emitter metal at the bottom and the side wall along the Z-axis direction of a gate electrode 71 on the basis of the traditional CSTBT and simultaneously introduces a P-type buried layer 12 below the N-type charge storage layer.
When the device works in a blocking state, potentials of the separation gate electrode 73 and the emitter metal 1 and the like are connected with a low potential, and meanwhile, negatively charged ionized acceptor fixed charges are provided in a depletion region formed when the PN junction is reversely biased by the P-type buried layer 12, so that charge compensation is formed, the electric field of the charge storage layer is effectively shielded, the limitation of the doping concentration of the charge storage layer on the breakdown characteristic of the device is further improved, and the separation gate dielectric layer 74 positioned at the bottom of the groove can be thickened, so that the electric field concentration effect at the bottom of the groove is favorably relieved, and the breakdown voltage is further improved.
When the device works in a conducting state, just because the charge compensation effect of the separation gate electrode 73 and the P-type buried layer 12 improves the limitation of the charge storage layer 6 on the breakdown characteristic of the device, the device structure provided by the invention can improve the carrier distribution when the device is conducted in the forward direction by improving the doping concentration of the charge storage layer, so that the conductivity modulation capability of the drift region is improved, the forward conducting voltage drop of the device is reduced, and the on-state loss of the device is reduced.
Since the split gate electrode 73 and the gate electrode 71 are located in the same trench, and the gate electrode 71 and the split gate electrode 73 are arranged above the trench at intervals in the Z-axis direction, the channel density of the entire chip is reduced. The introduction of the split gate electrode 73 and the P-type buried layer 12 between two adjacent gate electrodes 71 forms a parasitic PMOS structure in the cell structure, which is composed of the P-type buried layer 12, the N-type charge storage layer 6, the P-type base region 5, the P + emitter region 4, and the split gate electrode 73. In the turn-off process of the device, the PMOS is turned on to accelerate the extraction of holes, so that the compromise relation between the forward conduction voltage drop Vceon and the turn-off loss Eoff of the device is improved. With the increase of forward bias on collector metal, the potentials of the P-type buried layer and the N-type charge storage layer can be increased along with the increase of the voltage of a collector, but when the potential of the P-type buried layer is increased to a certain value, the PMOS is turned on, at the moment, the N-type charge storage layer is equivalently in short circuit with an emitter, the potential is not increased along with the increase of the voltage of the collector any more, partial gate-collector capacitance is converted into gate-emitter capacitance, and the gate-collector capacitance (Miller capacitance) can be effectively reduced. In addition, the depth of the gate electrode 71 is reduced to be smaller than the junction depth of the N-type charge storage layer 6, the gate electrode 71 is surrounded by the separation gate electrode 73, the coupling effect of the gate electrode 71 and the drift region 8 is shielded, the gate capacitance, particularly the gate-collector capacitance, is effectively reduced, the switching speed of the device is improved, and the switching loss is reduced. In addition, grid capacitance is reduced, and meanwhile grid charge can be reduced, so that the device is easy to drive, the requirement of the device on the capacity of a driving circuit is reduced, driving loss is reduced, and the compromise relationship between the voltage reduction rate dv/dt and the conduction loss Eon in the starting process is optimized. When the device is in a short-circuit working condition, the reduction of the channel density and the clamping of the potential of the N-type charge storage layer enable the device to be saturated in advance, so that the saturation current of the device is reduced, and a wider short-circuit operation safety area (SCSOA) is obtained. Because the separation gate electrode 73 and the gate electrode 71 are positioned in the same groove, a PMOS structure exists in each unit cell, the distance between a parasitic PMOS and an NMOS channel is shortened, the clamping effect of the PMOS is enhanced, the current uniformity in a chip is improved, and the reliability and the Reverse Bias Safe Operating Area (RBSOA) of a device are improved.
The beneficial effects of the invention are as follows:
the invention introduces a separation gate electrode 73 which has the same potential with an emitter metal at the bottom and the side wall along the Z-axis direction of a gate electrode 71 on the basis of the traditional CSTBT, and simultaneously introduces a P-type buried layer 12 below an N-type charge storage layer. The influence of the doping concentration of the N-type charge storage layer 6 on the breakdown characteristic of the device is effectively eliminated through charge compensation, the breakdown voltage and the reliability of the device are improved, and the on-state loss can be reduced by reducing the forward conduction voltage drop through improving the doping concentration of the N-type charge storage layer 6.
According to the invention, the gate electrode 71 and the split gate electrode 73 are placed in the same groove, and the gate electrode and the split gate electrode are arranged above the groove at intervals along the Z-axis direction, so that on one hand, the channel density can be reduced, and on the other hand, the split gate electrode 73 between adjacent gate electrodes 71, the P-type buried layer 12, the N-type charge storage layer 6, the P-type base region 5 and the P + emitter region 4 form a parasitic PMOS structure. In the turn-off process, the PMOS is turned on to improve the hole extraction speed in the turn-off process, so that the compromise relationship between the forward conduction voltage drop Vceon and the turn-off loss Eoff is improved. According to the invention, through clamping the N-type charge storage layer 6 by the PMOS and surrounding the gate electrode by the separated gate electrode, the gate capacitance and the gate charge can be effectively reduced, and the switching loss of the device and the requirement on the capability of a gate drive circuit are reduced. The invention reduces the saturation current density of the device and improves the Short Circuit Safe Operating Area (SCSOA) of the device by reducing the channel density and clamping the potential of the PMOS on the channel. Because the distance between the parasitic PMOS and the NMOS channel is shortened, the clamping effect of the PMOS and the current uniformity inside the chip are effectively improved, and high reliability and a wide reverse bias safe working area (RBSOA) are obtained.
Drawings
Fig. 1 is a schematic diagram of a half-cell structure of a conventional three-dimensional split-gate trench charge storage type IGBT device;
fig. 2 is a schematic structural diagram of a half-cell of a three-dimensional split-gate trench charge storage type IGBT according to embodiment 1 of the present invention;
fig. 3 is a schematic cross-sectional view of a half-cell structure of a three-dimensional split-gate trench charge storage type IGBT according to embodiment 1 of the present invention along line AB;
fig. 4 is a schematic cross-sectional view of a half-cell structure of a three-dimensional split-gate trench charge storage type IGBT according to embodiment 1 of the present invention along the CD line;
fig. 5 is a schematic cross-sectional view of a half-cell structure of a three-dimensional split-gate trench charge storage type IGBT according to embodiment 1 of the present invention along the EF line;
fig. 6 is a schematic cross-sectional view of a half-cell structure of a three-dimensional split-gate trench charge storage type IGBT according to embodiment 1 of the present invention along the GH line;
fig. 7 is a schematic structural diagram of a half-cell of a three-dimensional split-gate trench charge storage type IGBT according to embodiment 2 of the present invention;
fig. 8 is a schematic cross-sectional view of a half-cell structure of a three-dimensional split-gate trench charge storage type IGBT according to embodiment 2 of the present invention along line AB;
fig. 9 is a schematic cross-sectional view of a half-cell structure of a three-dimensional split-gate trench charge storage IGBT according to embodiment 2 of the present invention, taken along a CD line;
fig. 10 is a schematic cross-sectional view of a half-cell structure of a three-dimensional split-gate trench charge storage type IGBT according to embodiment 2 of the present invention along the EF line;
fig. 11 is a schematic cross-sectional view of a half-cell structure of a three-dimensional split-gate trench charge storage IGBT according to embodiment 2 of the present invention, along a GH line;
fig. 12 is a schematic structural diagram of a half-cell of a three-dimensional split-gate trench charge storage IGBT according to embodiment 3 of the present invention;
fig. 13 is a schematic cross-sectional view of a half-cell structure of a three-dimensional split-gate trench charge storage IGBT according to embodiment 3 of the present invention, taken along line AB;
fig. 14 is a schematic cross-sectional view of a half-cell structure of a three-dimensional split-gate trench charge storage IGBT according to embodiment 3 of the present invention, taken along the CD line;
fig. 15 is a schematic cross-sectional view of a half-cell structure of a three-dimensional split-gate trench charge storage type IGBT according to embodiment 3 of the present invention, taken along the EF line;
fig. 16 is a schematic cross-sectional view of a half-cell structure of a three-dimensional split-gate trench charge storage type IGBT according to embodiment 3 of the present invention along the GH line;
fig. 17 is a schematic structural diagram of a half-cell of a three-dimensional split-gate trench charge storage IGBT according to embodiment 4 of the present invention;
fig. 18 is a schematic cross-sectional view of a half-cell structure of a three-dimensional split-gate trench charge storage type IGBT according to embodiment 4 of the present invention, taken along the line AB;
fig. 19 is a schematic cross-sectional view of a half-cell structure of a three-dimensional split-gate trench charge storage IGBT according to embodiment 4 of the present invention, taken along the CD line;
fig. 20 is a schematic cross-sectional view of a half-cell structure of a three-dimensional split-gate trench charge storage IGBT according to embodiment 4 of the present invention, taken along the EF line;
fig. 21 is a schematic cross-sectional view of a half-cell structure of a three-dimensional split-gate trench charge storage IGBT according to embodiment 4 of the present invention, taken along a GH line;
fig. 22 is a schematic structural diagram of a half-cell of a three-dimensional split-gate trench charge storage IGBT according to embodiment 5 of the present invention;
fig. 23 is a schematic cross-sectional view of a half-cell structure of a three-dimensional split-gate trench charge storage IGBT according to embodiment 5 of the present invention, taken along the line AB;
fig. 24 is a schematic cross-sectional view of a half-cell structure of a three-dimensional split-gate trench charge storage IGBT according to embodiment 5 of the present invention, taken along the CD line;
fig. 25 is a schematic structural diagram of a half cell after a split-gate trench is formed in a three-dimensional split-gate trench charge storage IGBT according to embodiment 6 of the present invention;
fig. 26 is a schematic structural diagram of a half cell after a separation gate dielectric layer 74 is formed on a three-dimensional separation gate trench charge storage type IGBT according to embodiment 6 of the present invention;
fig. 27 is a schematic structural view of a half cell after polysilicon is deposited to form a split gate electrode 73 in a three-dimensional split gate trench charge storage type IGBT according to embodiment 6 of the present invention;
fig. 28 is a schematic structural diagram of a half cell after polysilicon and a dielectric layer are etched in a split gate electrode to form a gate trench in the three-dimensional split-gate trench charge storage IGBT according to embodiment 6 of the present invention;
fig. 29 is a schematic structural diagram of a half cell after a gate dielectric layer 72 is formed on a three-dimensional split-gate trench charge storage type IGBT according to embodiment 6 of the present invention;
fig. 30 is a schematic diagram of a half-cell structure of a three-dimensional split-gate trench charge storage IGBT according to embodiment 6 after a gate electrode 71 is formed;
fig. 31 is a schematic structural diagram of a half-cell after an N + emitter region 3 and a P + emitter region 4 are formed in a three-dimensional split-gate trench charge storage IGBT according to embodiment 6 of the present invention;
fig. 32 is a schematic structural diagram of a half cell after emitter metal 1 is formed on the upper surfaces of an N + emitter region 3 and a P + emitter region 4 of the three-dimensional split-gate trench charge storage IGBT according to embodiment 6 of the present invention;
fig. 33 is a schematic diagram of a half-cell structure of a three-dimensional split-gate trench charge storage IGBT according to embodiment 6 after all the processes are completed.
In the drawings, the components represented by the respective reference numerals are listed below:
1 is emitter metal, 2 is Schottky contact metal, 3 is an N + emitter region, 4 is a P + emitter region, 5 is a P-type base region, 6 is an N-type charge storage layer, 71 is a gate electrode, 72 is a gate dielectric layer, 73 is a split gate electrode, 74 is a split gate dielectric layer, 8 is an N-drift region, 9 is an N-type field stop layer, 10 is a P-type collector region, 11 is collector metal, 12 is a P-type buried layer, 13 is a floating P-type doped region, 14 is a super-junction P column, and 15 is a super-junction N column.
Detailed Description
The principles and features of this invention are described below in conjunction with the following drawings, which are set forth to illustrate, but are not to be construed to limit the scope of the invention.
In the three-dimensional split-gate trench charge storage IGBT provided in embodiment 1 of the present invention, the half-cell structure and the cross-sections along the AB line, the CD line, the EF line, and the GH line are shown in fig. 2 to 6,
defining the three-dimensional direction of the device by a three-dimensional rectangular coordinate system: defining the transverse direction of the device as the X-axis direction, the vertical direction of the device as the Y-axis direction, and the longitudinal direction of the device, namely the third dimension direction, as the Z-axis direction, wherein the cellular structure comprises: the back collector metal 11, the P-type collector region 10, the N-type field stop layer 9 and the N-drift region 8 are sequentially stacked from bottom to top along the Y-axis direction; the top layer of the N-drift region 8 is provided with P-type buried layers 12 distributed at intervals along the Z-axis direction, the N-drift region 8 is provided with an N-type charge storage layer 6 and a groove structure which are in side contact with each other along the X-axis direction, and the N-type charge storage layer 6 is arranged on the P-type buried layers 12; along the Y-axis direction, the top layer of the N-type charge storage layer 6 is provided with a P-type base region 5; the top layer of the P-type base region 5 is provided with an N + emitter region 3 and a P + emitter region 4, the side surfaces of which are mutually contacted, along the Z-axis direction, and the N + emitter region 3 and the P + emitter region 4 are distributed in an alternating mode;
the depth of the groove structure is greater than the junction depth of the P-type buried layer 12, and the groove structure comprises a gate electrode 71, a gate dielectric layer 72, a separation gate electrode 73 and a separation gate dielectric layer 74; along the Z-axis direction, the gate electrodes 71 are distributed on the top layer of the separation gate electrode 73 in an interval mode, and the depth of the gate electrodes 71 is larger than the junction depth of the P-type base region 5 and smaller than the junction depth of the N-type charge storage layer 6; the gate electrode 71 and the split gate electrode 73 are separated by the gate dielectric layer 72; the gate electrode 71 is connected with the N + emitter region 3, the P-type base region 5 and the N-type charge storage layer 6 through the gate dielectric layer 72; the depth of the lower surface of the separation gate electrode 73 is greater than the junction depth of the P-type buried layer 12; the separation gate electrode 73 is connected with the P + emitter region 4, the P-type base region 5, the N-type charge storage layer 6, the P-type buried layer 12 and the N-drift region 8 through the separation gate dielectric layer 74; the thickness of the separation gate dielectric layer 74 is greater than or equal to the thickness of the gate dielectric layer 72;
the N + emitter region 3 and the P + emitter region 4 further have an emitter metal 1 thereon, and the split gate electrode 73 is equipotential to the emitter metal 1.
The semiconductor material used in the above embodiments is silicon, and any suitable semiconductor material such as silicon, gallium nitride, etc. may be used in the other embodiments. In the embodiment, the thickness of the metallized electrodes (emitter metal and collector metal) is 1-6 μm; the doping concentration of the N + emitter region 3 is 5X 10 18 cm -3 ～1×10 20 cm -3 The depth is 0.3-0.5 μm; the doping concentration of the P + emitter region 4 is 1X 10 18 cm -3 ～1×10 19 cm -3 The depth is 0.3-0.5 μm; the doping concentration of the P-type base region 5 is 3 multiplied by 10 16 cm -3 ～2×10 17 cm -3 The depth is 1.5-2.5 μm; the doping concentration of the N-type charge storage layer 6 is 1 x 10 16 cm -3 ～5×10 17 cm -3 The depth is 1.5-2.5 μm; the P-type buried layer 12 has a doping concentration of 1 × 10 16 cm -3 ～5×10 18 cm -3 The depth is 0.5-1.5 μm; the doping concentration of the N-type drift region 8 is 2 multiplied by 10 14 cm -3 ～1×10 16 cm -3 (ii) a Separation grid mediumThe thickness of the layer 74 is 0.2 to 3 μm; the thickness of the gate dielectric layer 72 is 200-1000 nm; the depth of the gate electrode is 2 to 3 μm; the depth of the split gate electrode 73 is 5 to 7 μm. The length of the gate electrode 71 in the Z-axis direction is 0.5 to 2 μm; the length of the split gate electrode 73 between the adjacent two gate electrodes 71 in the Z-axis direction is 0.5 to 5 μm.
In this embodiment, the trench structure may sequentially penetrate through the N + emitter region 3, the P + emitter region 4, the P-type base region 5, the N-type charge storage layer 6, and the P-type buried layer 12 from the surface of the device and then extend into the N-drift region 8, and the trench structure may penetrate through the device along the z-axis direction; the gate electrode 71 penetrates through the N + emitter region 3 and the P-type base region 5 downwards to enter the N-type charge storage layer 6, and the separation gate electrode 73 penetrates through the P + emitter region 4, the P-type base region 5, the N-type charge storage layer 6 and the P-type buried layer 12 downwards to enter the N-drift region 8. In addition, in this embodiment, the thickness of the separation gate dielectric layer 74 is greater than or equal to the thickness of the gate dielectric layer 72, so that the device reliability in the blocking state can be improved.
In the three-dimensional split-gate trench charge storage IGBT provided in embodiment 2 of the present invention, a half-cell structure and cross sections along an AB line, a CD line, an EF line, and a GH line are respectively shown in fig. 7 to fig. 11, and a three-dimensional rectangular coordinate system is used to define three-dimensional directions of a device: defining the transverse direction of the device as the X-axis direction, the vertical direction of the device as the Y-axis direction, and the longitudinal direction of the device, namely the third dimension direction, as the Z-axis direction, wherein the cellular structure comprises: the back collector metal 11, the P-type collector region 10, the N-type field stop layer 9 and the N-drift region 8 are sequentially stacked from bottom to top along the Y-axis direction, and the top layer of the N-drift region 8 is provided with P-type buried layers 12 distributed at intervals along the Z-axis direction; an N-type charge storage layer 6 and a groove structure with side surfaces mutually contacted are arranged on the N-drift region 8 along the X-axis direction, and the N-type charge storage layer 6 is arranged on the P-type buried layer 12; along the Y-axis direction, the top layer of the N-type charge storage layer 6 is provided with a P-type base region 5; in the Z-axis direction, N + emitter regions 3 distributed at intervals are arranged on the top layer of the P-type base region 5, the P-type base region 5 is arranged between the adjacent N + emitter regions 3, and the upper surfaces of the N + emitter regions 3 and the P-type base regions 5 are flush;
the depth of the groove structure is greater than the junction depth of the P-type buried layer 12, and the groove structure comprises a gate electrode 71, a gate dielectric layer 72, a separation gate electrode 73 and a separation gate dielectric layer 74; along the Z-axis direction, the gate electrodes 71 are distributed on the top layer of the separation gate electrode 73 in an interval mode, and the depth of the gate electrodes 71 is larger than the junction depth of the P-type base region 5 and smaller than the junction depth of the N-type charge storage layer 6; the gate electrode 71 and the split gate electrode 73 are separated by the gate dielectric layer 72; the gate electrode 71 is connected with the N + emitter region 3, the P-type base region 5 and the N-type charge storage layer 6 through the gate dielectric layer 72; the depth of the lower surface of the separation gate electrode 73 is greater than the junction depth of the P-type buried layer 12; the separation gate electrode 73 is separated from the P-type base region 5, the N-type charge storage layer 6, the P-type buried layer 12 and the N-drift region 8 through the separation gate dielectric layer 74; the thickness of the separation gate dielectric layer 74 is greater than or equal to the thickness of the gate dielectric layer 72;
emitter metal 1 is arranged on the N + emitter region 3, schottky contact metal 2 is arranged on the P-type base region 5 between the adjacent N + emitter regions 3, and the split gate electrode 73 and the Schottky contact metal 2 are equipotential with the emitter metal 1.
The semiconductor material used in the above embodiments is silicon, and any suitable semiconductor material such as silicon carbide and gallium nitride may be used. In the embodiment, the thickness of the metallized electrodes (the emitter metal, the collector metal and the Schottky contact metal) is 1-6 μm; the doping concentration of the N + emitter region 3 is 5X 10 18 cm -3 ～1×10 20 cm -3 The depth is 0.3-0.5 μm; the doping concentration of the P-type base region 5 is 3 multiplied by 10 16 cm -3 ～2×10 17 cm -3 The depth is 1.5-2.5 μm; the doping concentration of the N-type charge storage layer 6 is 1 x 10 16 cm -3 ～5×10 17 cm -3 The depth is 1.5-2.5 μm; the doping concentration of the P-type buried layer 12 is 1 × 10 16 cm -3 ～5×10 18 cm -3 The depth is 0.5-1.5 μm; the doping concentration of the N-type drift region 8 is 2 multiplied by 10 14 cm -3 ～1×10 16 cm -3 (ii) a The thickness of the separation gate dielectric layer 74 is 0.2-3 μm; the thickness of the gate dielectric layer 72 is 200-1000 nm; the depth of the gate electrode is 2 to 3 μm; the depth of the split gate electrode 73 is 5 to 7 μm. Length of gate electrode 71 in Z-axis direction0.5-2 μm; the length of the split gate electrode 73 between two adjacent gate electrodes 71 in the Z-axis direction is 0.5 to 5 μm.
In this embodiment, the trench structure may extend into the N-drift region 8 after sequentially penetrating through the N + emitter region 3, the P-type base region 5, the N-type charge storage layer 6, and the P-type buried layer 12 from the surface of the device, and may penetrate through the device along the z-axis direction; the gate electrode 71 penetrates through the N + emitter region 3 and the P-type base region 5 downwards to enter the N-type charge storage layer 6, and the separation gate electrode 73 penetrates through the P-type base region 5, the N-type charge storage layer 6 and the P-type buried layer 12 downwards to enter the N-drift region 8.
In the embodiment, the Schottky contact metal 2 which has the same potential as the emitter metal 1 is introduced on the upper surface of the P-type base region 5 between the adjacent N + emitter regions 3, and the Schottky contact is formed between the Schottky contact metal 2 and the upper surface of the P-type base region 5, so that the conduction voltage drop of the PMOS can be reduced, the PMOS can be started more quickly, the clamping effect is better when the PMOS is conducted in the forward direction, and the short-circuit working safety area of a device is better improved; when the device is turned off, the switching speed of the device can be further improved, and the switching loss of the device is reduced. In addition, in this embodiment, the thickness of the separation gate dielectric layer 74 is greater than or equal to the thickness of the gate dielectric layer 72, so that the device reliability in the blocking state can be improved.
In the three-dimensional split-gate trench charge storage IGBT provided in embodiment 3 of the present invention, a half-cell structure and cross sections along an AB line, a CD line, an EF line, and a GH line are respectively shown in fig. 12 to 16, and in embodiment 3 of the present invention, a floating P-type doped region 13 is formed by ion implantation on the basis of embodiment 1; in the direction of the X axis, the floating P-type doped region 13 is located at one side of the trench structure, and the floating P-type doped region 13 is isolated from the gate electrode 71 by the gate dielectric layer 72 and isolated from the isolated gate electrode 73 by the isolated gate dielectric layer 74.
In the above embodiment, the floating P-type doped region 13 is introduced to cause holes to be accumulated on the surface when the device is turned on, and due to the principle of charge balance, the accumulated holes induce a corresponding number of electrons, so that the conductivity modulation capability of the device is greatly enhanced, and the conduction voltage drop and conduction loss of the device are reduced.
In the three-dimensional split-gate trench charge storage IGBT provided in embodiment 4 of the present invention, a half-cell structure and cross sections along an AB line, a CD line, an EF line, and a GH line are respectively shown in fig. 17 to fig. 21, and in embodiment 4 of the present invention, on the basis of embodiment 3, along an X-axis direction, a width of the gate electrode 71 and the gate dielectric layer 72 is smaller than a width of the trench structure, so that the split gate electrode 73 is provided between the gate dielectric layer 72 and the floating P-type doped region 13, and the split gate electrode 73 is connected to the floating P-type doped region 13 through the split gate dielectric layer 74.
In this embodiment, during the gate trench etching, the gate electrode 71 is wrapped by the split gate electrode 73 in an "L" shape along the X-axis direction by partially etching the poly and the dielectric layer filled in the separated gate trench.
In this embodiment, the size of the opening of the mask is adjusted during etching by adjusting the process, and the width of the gate electrode 71 in the X-axis direction is changed, thereby changing the shape of the split gate electrode 73. The coupling effect between the gate electrode 71 and the floating P-type doped region 13 is shielded by the split gate electrode 73, so that the negative capacitance effect caused by the displacement current of the floating P-type doped region is reduced, the gate-collector capacitance can be reduced, and the switching speed of the device is increased; and the grid control capability can be improved by reducing the displacement current, and the EMI noise is reduced.
A half-cell structure and cross sections along an AB line and a CD line of the three-dimensional split-gate trench charge storage IGBT provided in embodiment 5 of the present invention are respectively shown in fig. 22 to fig. 24, where in embodiment 5 of the present invention, on the basis of embodiment 4, a super-junction P column 14 and a super-junction N column 15 whose side surfaces are in contact with each other are provided in the N-drift region 8; the super-junction P-column 14 and the super-junction N-column 15 satisfy the charge balance requirement, the first portion of the trench structure and the N-type charge storage layer 6 are located on the super-junction N-column 15, and the second portion of the trench structure and the floating P-type doped region 13 are located on the super-junction P-column 14.
In the above embodiment, the doping concentration of the super junction N column 15 is greater than or equal to the doping concentration of the N-drift region 8, in this embodiment, the super junction P column 14 and the super junction N column 15 are introduced into the N-drift region 8 to change the one-dimensional withstand voltage in the drift region into the two-dimensional withstand voltage, so that the compromise relationship between the conduction voltage drop and the device breakdown voltage is improved, and the performance of the device is improved.
Optionally, the depth of the lower surface of the floating P-type doped region 13 is equal to or greater than the depth of the trench structure.
Optionally, the doping concentration of the N-type charge storage layer 6 is gradually changed from a region close to the trench structure to a region far from the trench structure, wherein the doping concentration of the region close to the trench structure is low, and the doping concentration of the region far from the trench structure is high.
In the embodiment, the doping concentration of the N-type charge storage layer 6 close to the groove region is reduced, the threshold voltage of the PMOS can be reduced, the PMOS can be started more quickly, the clamping effect is better when the PMOS is conducted in the forward direction, and the short-circuit working safety area of the device is better improved; when the device is turned off, the switching speed of the device can be further improved, and the switching loss of the device is reduced. When the device is conducted in the forward direction, the grid electrode is connected with high potential, and an electron accumulation layer is formed at the position of the N-type charge storage layer close to the grid electrode, so that the forward conduction characteristic of the device is not influenced.
Optionally, a doping concentration of the N-type charge storage layer 6 is gradually changed by using a variable doping technique or a divisional doping technique.
Optionally, the bottom of the trench structure also has a P-type layer 16.
In the above embodiment, the junction depth of the P-type layer 16 is 0.5 to 1 μm.
In this embodiment, the P-type layer 16 and the split gate electrode 73 are connected through a split gate dielectric layer. By introducing the P-type layer 16 at the bottom of the trench structure, the electric field concentration at the bottom of the trench is improved, and the breakdown voltage and the reliability of the device are improved.
Optionally, the semiconductor material used for the device is Si, siC, gaAs, gaN, ga 2 O 3 Any one or more of AlN and diamond.
Alternatively, the device structure is not only applicable to IGBT devices, but also to MOSFET devices, by replacing the P-type collector region 10 on the back of the device with N-type doping.
In embodiment 6 of the present invention, a 1200V voltage class IGBT with three-dimensional split gate trench charge storage is taken as an example for explanation, and devices with different performance parameters can be prepared according to actual requirements based on common knowledge in the art.
In the method for manufacturing the three-dimensional split-gate trench charge storage type IGBT provided in embodiment 6 of the present invention, a three-dimensional rectangular coordinate system is used to define the three-dimensional direction of the device: defining the transverse direction of the device as the X-axis direction, the vertical direction of the device as the Y-axis direction and the longitudinal direction of the device, namely the third dimension direction, as the Z-axis direction, and comprising the following steps:
step 1: selecting a lightly doped FZ silicon wafer with the thickness of 200-300 mu m to form an N-drift region 8,N-drift region of the device, wherein the doping concentration of the drift region is 10 14 ～10 15 Per cm 3 ；
Step 2: growing a field oxide layer on the surface of the FZ silicon wafer, photoetching to obtain an active region, growing a pre-oxide layer, forming P-type buried layers 12 distributed at intervals on the upper layer of the N-drift region 8 by masking, photoetching and ion implantation of P-type impurities, wherein the doping concentration of the P-type doping layers 12 is 10 15 ～10 17 /cm 3 (ii) a An N-type charge storage layer 6,N type charge storage layer 6 is prepared by ion implantation of N-type impurities on the upper surfaces of the N-drift region 8 and the P-type buried layer 12, and the doping concentration of the N-type charge storage layer 6,N type charge storage layer 6 is 10 15 ～10 16 /cm 3 (ii) a P-type impurities are implanted into the upper surface of the N-type charge storage layer 6 through ions, and annealing treatment is carried out to obtain a P-type base region 5,P type base region 5 with the doping concentration of 10 16 ～10 17 /cm 3 ；
And step 3: depositing a protective layer on the surface of the silicon wafer, photoetching a window to perform trench silicon etching, and etching on one side of the top layer of the N-drift region 8 along the X-axis direction to form a separation gate trench, wherein the depth of the separation gate trench is greater than the junction depth of the P-type buried layer 12, as shown in FIG. 25;
and 4, step 4: forming a separation gate dielectric layer 74 at the bottom and the side wall of the separation gate trench under the O2 atmosphere at 1050-1150 ℃, as shown in FIG. 26, wherein the thickness of the dielectric layer 74 is 0.1-0.5 μm, depositing polysilicon on the separation gate dielectric layer 74 at 750-950 ℃, and then reversely etching off the redundant polysilicon on the surface to form a separation gate electrode 73, as shown in FIG. 27;
and 5: depositing a protective layer on the surface of a silicon wafer, photoetching a window, and etching part of the polycrystalline silicon and the separation gate dielectric layer, thereby forming gate grooves distributed at intervals on the top layer of the separation gate groove along the Z-axis direction, wherein separation gate electrodes 73 are arranged between the gate grooves, and the depth of the gate grooves is greater than the junction depth of the P-type base region 5 and less than the junction depth of the N-type charge storage layer 6, as shown in FIG. 28;
step 6: forming a gate dielectric layer 72 on the bottom and the side wall of the gate trench, as shown in fig. 29, wherein the thickness of the gate dielectric layer 72 is 0.1-0.3 μm, depositing polysilicon on the gate dielectric layer 72 to form a gate electrode 71, wherein the gate electrode 71 is isolated from the separation gate electrode 73 through the gate dielectric layer 72, and the thickness of the gate dielectric layer 72 is less than or equal to that of the separation gate dielectric layer 74, as shown in fig. 30;
and 7: respectively injecting N-type impurities and P-type impurities into the top layer of the P-type base region 5 through photoetching and ion injection processes, so that N + emitter regions 3 and P + emitter regions 4 which are alternately arranged side by side and are in mutual contact with the side surfaces are formed on the top layer of the P-type base region 5 along the Z-axis direction, as shown in FIG. 31; one side of the N + emission region 3 is connected with a gate electrode 71 through a gate dielectric layer 72 along the X-axis direction, the junction depth of the N + emission region 3 is 0.2-0.5 mu m, and the doping concentration of the N + emission region 3 is 10 18 ～10 19 /cm 3 One side of the P + emitting region 4 is connected with a separation gate electrode 73 through a separation gate dielectric layer 74, the junction depth of the P + emitting region 4 is 0.2-0.5 mu m, and the doping concentration of the P + emitting region 4 is 10 18 ～10 19 /cm 3 ；
And 8: depositing metal on the surface of the device, and forming emitter metal 1 on the N + emitter region 3 and the P + emitter region 4 by adopting photoetching and etching processes, as shown in FIG. 32;
and step 9: turning over the silicon wafer, reducing the thickness of the silicon wafer, implanting N-type impurities into the back of the silicon wafer, and manufacturing an N-type field stop layer 9 of the device through multiple times of laser annealing, wherein the thickness of the formed N-type field stop layer is 1-5 mu m, the energy of ion implantation is 40-1000 KeV, and the implantation dosage is 10 13 ～10 14 Per cm 2 ；
Step 10: injecting P-type impurities into the back of the N-type field stop layer 9 to form a P-type collector region 10, wherein the thickness of the formed P-type collector region is 0.5-2 microns, the ion injection energy is 30 keV-100 keV, and the injection dosage is 10 13 ～10 14 Per cm 2 Performing ion activation through multiple times of laser annealing; then, a metal having a thickness of 1 to 6 μm is deposited on the back surface to form a collector metal 11, as shown in FIG. 33. Thus, the preparation of the three-dimensional separation gate groove charge storage type IGBT is completed.
Optionally, the semiconductor material used by the device is Si, siC, gaAs, gaN, ga 2 O 3 AlN and diamond, each of which may be of the same semiconductor material or a different semiconductor material.
According to the invention, on the basis of the traditional CSTBT, the separated gate electrode with the same potential as the emitter metal is introduced into the bottom of the gate electrode and the side wall in the Z-axis direction, and meanwhile, the P-type buried layer is introduced into the lower part of the N-type charge storage layer, so that the limit of the doping concentration and thickness of the charge storage layer on the voltage resistance of the device is avoided through charge compensation, and the purposes of improving the breakdown voltage of the device and improving the compromise relationship between the forward conduction voltage drop Vceon and the turn-off loss Eoff of the device are further achieved. The separated gate electrode and the gate electrode structure are in the same groove, so that the area of a chip can be saved, and the integration level of the chip is improved. The gate electrodes are arranged at intervals along the Z-axis direction, and a separation gate electrode is arranged between two adjacent gate electrodes, so that the channel density of the whole chip can be reduced. A parasitic PMOS structure is formed by a separation gate electrode between adjacent gate electrodes, the P-type buried layer, the N-type charge storage layer, the P-type base region and the P + emitter region, and PMOS and NMOS channels are connected through the N-type charge storage layer and the P-type base region. The potential of the P-type buried layer and the potential of the N-type charge storage layer can be increased along with the voltage increase of the collector, when the potential of the P-type buried layer is increased to a certain value, the PMOS is started, the N-type charge storage layer is in short circuit with the emitter, the potential is not increased along with the voltage increase of the collector, partial grid-collector capacitance is converted into grid-emitter capacitance, and the grid-collector capacitance can be effectively reduced.
Meanwhile, the depth of the gate electrode is reduced, and the separated gate electrode positioned at the bottom of the gate electrode can shield the coupling effect of the gate electrode and the drift region, so that the gate capacitance, particularly the gate-collector capacitance, is reduced, the switching speed of the device is improved, and the switching loss is reduced. In addition, grid capacitance is reduced, and meanwhile grid charge can be reduced, so that the device is easy to drive, the requirement of the device on the capacity of a driving circuit is reduced, driving loss is reduced, and the compromise relationship between the voltage reduction rate dv/dt and the conduction loss Eon in the starting process is optimized. In the turn-off process of the device, the PMOS can accelerate the extraction of holes, improve the switching speed of the device and further improve the compromise relationship between the forward conduction voltage drop Vceon and the turn-off loss Eoff of the device. When the device is in a short-circuit working condition, the reduction of the channel density and the potential of the N-type charge storage layer are clamped, so that the saturation current density is reduced, and the short-circuit safe working capacity of the device is improved. Because the separated gate electrode and the gate electrode are positioned in the same groove, the PMOS structure exists in each unit cell, the distance between a parasitic PMOS and an NMOS channel is shortened, the clamping effect of the PMOS is favorably enhanced, the current uniformity in a chip is improved, and the reliability and the Reverse Bias Safety Operating Area (RBSOA) of the device are improved.
In the description of the present invention, it is to be understood that the terms "central," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," "circumferential," and the like are used in the orientations and positional relationships indicated in the drawings for convenience in describing the invention and to simplify the description, and are not intended to indicate or imply that the referenced devices or elements must have a particular orientation, be constructed and operated in a particular orientation, and are therefore not to be considered limiting of the invention.
In the present invention, unless otherwise expressly stated or limited, the terms "mounted," "connected," "secured," and the like are to be construed broadly and can, for example, be fixedly connected, detachably connected, or integrally formed; can be mechanically or electrically connected; they may be directly connected or indirectly connected through intervening media, or they may be connected internally or in any other suitable relationship, unless expressly stated otherwise. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.
In the present invention, unless otherwise expressly stated or limited, the first feature "on" or "under" the second feature may be directly contacting the first and second features or indirectly contacting the first and second features through an intermediate. Also, a first feature "on," "over," and "above" a second feature may be directly or diagonally above the second feature, or may simply indicate that the first feature is at a higher level than the second feature. A first feature "under," "beneath," and "under" a second feature may be directly under or obliquely under the second feature, or may simply mean that the first feature is at a lesser elevation than the second feature.
In the description of the specification, reference to the description of "one embodiment," "some embodiments," "an example," "a specific example," or "some examples" or the like means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above are not necessarily intended to refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, various embodiments or examples and features of different embodiments or examples described in this specification can be combined and combined by one skilled in the art without contradiction.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like that fall within the spirit and principle of the present invention are intended to be included therein.

Claims (10)

1. A three-dimensional separation gate groove charge storage type IGBT uses a three-dimensional rectangular coordinate system to define the three-dimensional direction of a device: defining the transverse direction of the device as the X-axis direction, the vertical direction of the device as the Y-axis direction, and the longitudinal direction of the device as the Z-axis direction, wherein the cellular structure comprises: the back collector metal (11), the P-type collector region (10), the N-type field stop layer (9) and the N-drift region (8) are sequentially stacked from bottom to top along the Y-axis direction; the top layer of the N-drift region (8) is provided with P-type buried layers (12) distributed at intervals along the Z-axis direction, the N-drift region (8) is provided with an N-type charge storage layer (6) and a groove structure which are in side contact with each other along the X-axis direction, and the N-type charge storage layer (6) is arranged on the P-type buried layers (12); the top layer of the N-type charge storage layer (6) is provided with a P-type base region (5) along the Y-axis direction; the top layer of the P-type base region (5) is provided with an N + emitter region (3) and a P + emitter region (4) which are contacted with each other at the side surfaces along the Z-axis direction, and the N + emitter region (3) and the P + emitter region (4) are distributed in an alternating mode;
the depth of the groove structure is larger than the junction depth of the P-type buried layer (12), and the groove structure comprises a gate electrode (71), a gate dielectric layer (72), a separation gate electrode (73) and a separation gate dielectric layer (74); the gate electrodes (71) are distributed on the top layer of the separation gate electrode (73) at intervals along the Z-axis direction, and the depth of the gate electrodes (71) is larger than the junction depth of the P-type base region (5) and smaller than the junction depth of the N-type charge storage layer (6); the gate electrode (71) and the split gate electrode (73) are separated by the gate dielectric layer (72); the gate electrode (71) is connected with the N + emitter region (3), the P-type base region (5) and the N-type charge storage layer (6) through the gate dielectric layer (72); the depth of the lower surface of the separation gate electrode (73) is larger than the junction depth of the P-type buried layer (12); the separation gate electrode (73) is connected with the P + emitter region (4), the P-type base region (5), the N-type charge storage layer (6), the P-type buried layer (12) and the N-drift region (8) through the separation gate dielectric layer (74); the thickness of the separation gate dielectric layer (74) is greater than or equal to that of the gate dielectric layer (72);
the N + emitting region (3) and the P + emitting region (4) are also provided with emitter metal (1), and the separation gate electrode (73) is equipotential with the emitter metal (1).
2. A three-dimensional separation gate groove charge storage type IGBT defines the three-dimensional direction of a device by a three-dimensional rectangular coordinate system: defining the transverse direction of the device as the X-axis direction, the vertical direction of the device as the Y-axis direction, and the longitudinal direction of the device as the Z-axis direction, wherein the cellular structure comprises: the back collector metal (11), the P-type collector region (10), the N-type field stop layer (9) and the N-drift region (8) are sequentially stacked from bottom to top along the Y-axis direction; the top layer of the N-drift region (8) is provided with P-type buried layers (12) distributed at intervals along the Z-axis direction, the N-drift region (8) is provided with an N-type charge storage layer (6) and a groove structure which are in side contact with each other along the X-axis direction, and the N-type charge storage layer (6) is arranged on the P-type buried layers (12); the top layer of the N-type charge storage layer (6) is provided with a P-type base region (5) along the Y-axis direction; the top layer of the P-type base region (5) is provided with N + emitter regions (3) distributed at intervals along the Z-axis direction, the P-type base region (5) is arranged between the adjacent N + emitter regions (3), and the N + emitter regions (3) are flush with the upper surface of the P-type base region (5);
the depth of the groove structure is larger than the junction depth of the P-type buried layer (12), and the groove structure comprises a gate electrode (71), a gate dielectric layer (72), a separation gate electrode (73) and a separation gate dielectric layer (74); the gate electrodes (71) are distributed on the top layer of the separation gate electrode (73) at intervals along the Z-axis direction, and the depth of the gate electrodes (71) is larger than the junction depth of the P-type base region (5) and smaller than the junction depth of the N-type charge storage layer (6); the gate electrode (71) and the split gate electrode (73) are separated by the gate dielectric layer (72); the gate electrode (71) is connected with the N + emitter region (3), the P-type base region (5) and the N-type charge storage layer (6) through the gate dielectric layer (72); the depth of the lower surface of the separation gate electrode (73) is larger than the junction depth of the P-type buried layer (12); the separation gate electrode (73) is separated from the P-type base region (5), the N-type charge storage layer (6), the P-type buried layer (12) and the N-drift region (8) through the separation gate dielectric layer (74); the thickness of the separation gate dielectric layer (74) is greater than or equal to that of the gate dielectric layer (72);
emitter metal (1) is arranged on the N + emitter regions (3), schottky contact metal (2) is arranged on the P-type base region (5) between the adjacent N + emitter regions (3), and the separation gate electrode (73) and the Schottky contact metal (2) are equipotential with the emitter metal (1).
3. A three-dimensional split-gate trench charge storage IGBT according to claim 1 or claim 2 further comprising a floating P-type doped region (13); and in the X-axis direction, a floating P-type doped region (13) is positioned on one side of the groove structure, and the floating P-type doped region (13) is separated from the gate electrode (71) through the gate dielectric layer (72) and is separated from the separation gate electrode (73) through the separation gate dielectric layer (74).
4. The three-dimensional split-gate trench charge storage type IGBT as claimed in claim 3, wherein along the X-axis direction, the width of said gate electrode (71) plus said gate dielectric layer (72) is smaller than the width of said trench structure, said split gate electrode (73) is arranged between said gate dielectric layer (72) and said floating P-type doped region (13), and said split gate electrode (73) is connected with said floating P-type doped region (13) through said split gate dielectric layer (74).
5. A three-dimensional split-gate trench charge storage type IGBT according to claim 1 or claim 2, wherein the doping concentration of the N-type charge storage layer (6) is graded from a region near the trench structure to a region far from the trench structure, wherein the doping concentration of the region near the trench structure is low and the doping concentration of the region far from the trench structure is high.
6. A three-dimensional split-gate trench charge storage IGBT according to claim 1 or claim 2, characterized in that the bottom of the trench structure further has a P-type layer (16).
7. The three-dimensional split-gate trench charge storage type IGBT as claimed in claim 4, wherein said N-drift region (8) has therein a super-junction P-pillar (14) and a super-junction N-pillar (15) which are in contact with each other laterally; the super-junction P-column (14) and the super-junction N-column (15) meet charge balance requirements, a first portion of the trench structure and the N-type charge storage layer (6) are located on the super-junction N-column (15), and a second portion of the trench structure and the floating P-type doped region (13) are located on the super-junction P-column (14).
8. The three-dimensional split-gate trench charge storage IGBT of claim 1 or claim 2 wherein the semiconductor material used for the device is Si, siC, gaAs, gaN, ga 2 O 3 Any one or more of AlN and diamond.
9. A manufacturing method of a three-dimensional separation gate groove charge storage type IGBT is characterized in that a three-dimensional rectangular coordinate system is used for defining the three-dimensional direction of a device: defining the transverse direction of the device as the X-axis direction, the vertical direction of the device as the Y-axis direction and the longitudinal direction of the device, namely the third dimension direction, as the Z-axis direction, and being characterized by comprising the following steps:
step 1: selecting a lightly doped FZ silicon wafer to form an N-drift region (8) of the device;
step 2: growing a field oxide layer on the surface of the FZ silicon wafer, photoetching to obtain an active region, growing a pre-oxide layer, and forming P-type buried layers (12) distributed at intervals on the upper layer of the N-drift region (8) by masking, photoetching and ion implantation of P-type impurities; an N-type charge storage layer (6) is manufactured on the upper surfaces of the N-drift region (8) and the P-type buried layer (12) through ion implantation of N-type impurities; implanting P-type impurities into the upper surface of the N-type charge storage layer (6) through ions and annealing to obtain a P-type base region (5);
and step 3: depositing a protective layer on the surface of a silicon wafer, photoetching a window to perform groove silicon etching, and etching on one side of the top layer of the N-drift region (8) along the X-axis direction to form a separation gate groove, wherein the depth of the separation gate groove is greater than the junction depth of the P-type buried layer (12);
and 4, step 4: forming a separation gate dielectric layer (74) at the bottom and the side wall of the separation gate groove, and depositing polycrystalline silicon on the separation gate dielectric layer (74) to form a separation gate electrode (73);
and 5: depositing a protective layer on the surface of a silicon wafer, photoetching a window, and etching part of the polycrystalline silicon and the separation gate dielectric layer, thereby forming gate grooves distributed at intervals on the top layer of the separation gate groove along the Z-axis direction, wherein separation gate electrodes (73) are arranged among the gate grooves, and the depth of the gate grooves is greater than the junction depth of the P-type base region (5) and less than the junction depth of the N-type charge storage layer (6);
step 6: forming a gate dielectric layer (72) at the bottom and on the side wall of the gate trench, depositing polysilicon on the gate dielectric layer (72) to form a gate electrode (71), wherein the gate electrode (71) is isolated from the separation gate electrode (73) through the gate dielectric layer (72), and the thickness of the gate dielectric layer (72) is less than or equal to that of the separation gate dielectric layer (74);
and 7: respectively injecting N-type impurities and P-type impurities into the top layer of the P-type base region (5) through photoetching and ion injection processes, so that N + emitter regions (3) and P + emitter regions (4) which are alternately arranged side by side and are mutually contacted at the side surfaces are formed on the top layer of the P-type base region (5) along the Z-axis direction; one side of the N + emission region (3) is connected with a gate electrode (71) through a gate dielectric layer (72) along the X-axis direction, and one side of the P + emission region (4) is connected with a separation gate electrode (73) through a separation gate dielectric layer (74);
and 8: depositing metal on the surface of the device, and forming emitter metal (1) on the N + emitting region (3) and the P + emitting region (4) by adopting photoetching and etching processes;
and step 9: turning over the silicon wafer, reducing the thickness of the silicon wafer, injecting N-type impurities into the back of the silicon wafer, and manufacturing an N-type field stop layer (9) of the device through multiple times of laser annealing;
step 10: injecting P-type impurities into the back of the N-type field stop layer (9) to form a P-type collector region (10), and performing ion activation through multiple times of laser annealing; then, a collector metal (11) is formed by depositing metal on the back surface.
10. The method of claim 1 or claim 2, wherein the doping concentration of the N-drift region (8) is 10 14 ～10 15 Per cm 3 Or, doping of the P-type buried layer (12)Impurity concentration of 10 16 ～10 18 /cm 3 Or the doping concentration of the N-type charge storage layer (6) is 10 15 ～10 17 /cm 3 Or the doping concentration of the P-type base region (5) is 10 16 ～10 17 /cm 3 。
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