CN108428740A - A kind of igbt chip with the compound grid structure containing empty grid - Google Patents
A kind of igbt chip with the compound grid structure containing empty grid Download PDFInfo
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- CN108428740A CN108428740A CN201810148858.0A CN201810148858A CN108428740A CN 108428740 A CN108428740 A CN 108428740A CN 201810148858 A CN201810148858 A CN 201810148858A CN 108428740 A CN108428740 A CN 108428740A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
- H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
- H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
- H01L29/0692—Surface layout
- H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
- H01L29/404—Multiple field plate structures
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
- H01L29/407—Recessed field plates, e.g. trench field plates, buried field plates
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
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- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
- H01L29/42376—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the length or the sectional shape
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- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
- H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
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Abstract
The invention discloses a kind of igbt chips with the compound grid structure containing empty grid, including several composite grid units being formed on wafer substrate, composite grid unit includes gate regions and active area, gate regions include first groove grid, second groove grid and planar gate, planar gate is connected with first groove grid, and second groove grid is hanging, is grounded or is connected with planar gate；Active area includes the trench gate active area and planar gate active area positioned at gate regions both sides, includes N well regions, p-well region, P+ doped regions and the doped diffusion regions N+ being distributed from bottom to top.Planar gate can be achieved in the present invention and first groove grid coexists in same chip, to greatly promote chip density, and by being interfered with each other between the effective mask plane grid of second groove grid between planar gate and first groove grid and first groove grid the two, optimize composite grid simultaneously outputs and inputs capacitance, optimization chip opens alive change rate, reduces switching loss.
Description
Technical field
The present invention relates to technical field of semiconductor device more particularly to a kind of IGBT with the compound grid structure containing empty grid
Chip.
Background technology
From IGBT before and after 1980 (Insulated Gate Bipolar Transistor, insulated gate bipolar crystal
Pipe) device come out since, since it had not only had the characteristics that bipolar transistor on-state voltage drop was low, current density is big, but also have
MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor, Metal-Oxide Semiconductor field
Effect transistor) the features such as pipe input impedance is high, fast response time, it is widely used in rail traffic, intelligent grid, industry become
The fields such as frequency and new energy development.
Fig. 1 is the diagrammatic cross-section of half cellular of the igbt chip in the prior art with planar gate structure.Such as Fig. 1 institutes
Show, includes mainly：Substrate 101, N well regions 102, p-well region 103, N+ doped regions 104, P+ doped regions 105, planar gate 106, grid
Oxide layer 107, passivation layer 108 and metal layer 109.The major advantage of igbt chip shown in FIG. 1 with planar gate structure
It is that technique makes simply, it is low for equipment requirements, and planar gate good pressure-resistant performance, sturdy degree is high, thus can be used for working environment
Compare severe place.But since its channel region is on surface, gully density is limited by chip list size, is caused
Conductivity modulation effect in igbt chip body is weaker, and conduction voltage drop is higher.
Fig. 2 is the diagrammatic cross-section of half cellular of the igbt chip in the prior art with trench gate structure.Such as Fig. 2 institutes
Show, includes mainly：Substrate 201, N well regions 202, p-well region 203, N+ doped regions 204, P+ doped regions 205, trench-gate 206, grid
Oxide layer 207, passivation layer 208 and metal layer 209.In order to reduce the conduction voltage drop of igbt chip, using ditch as shown in Figure 2
Slot grid structure replaces planar gate structure.As shown in Fig. 2, forming trench-gate by etching technics so that raceway groove enters substrate body
It is interior, it realizes raceway groove by being laterally converted into longitudinal direction, to realize one-dimensional current channel, effectively eliminates the JFET in plane gate groove
Effect, while cellular size is reduced, so that gully density is no longer limited by chip list area, greatly improves cellular density to big
Amplitude promotes chip current density.But with the increase of groove grid density, chip saturation current is excessive, weakens chip
Short-circuit capability, to affect the safety operation area of chip.
Fig. 3 is the diagrammatic cross-section of half cellular of the igbt chip in the prior art for having and accompanying grid and trench gate structure.
As shown in figure 3, including mainly：Substrate 301, N well regions 302, p-well region 303, N+ doped regions 304, P+ doped regions 305, trench-gate
306, grid 307, gate oxide 308, passivation layer 309 and metal layer 310 are accompanied.In order to balance between short-circuit capability and current density
Tradeoff, trench gate structure as shown in Figure 2 is replaced using the structure for accompanying grid and trench-gate to coexist as shown in Figure 3.
There is certain limitation in the bottom of trench-gate in Fig. 2 and Fig. 3 to the damping ability of igbt chip.Itself and Fig. 1 institutes
The igbt chip with planar gate structure shown is compared, and it is resistance to also to sacrifice plane gate part while promoting igbt chip performance
Pressure and sturdy performance.
Invention content
In view of the above technical problems, the present invention provides a kind of igbt chip with the compound grid structure containing empty grid, packets
It includes wafer substrate and is formed in the positive composite grid unit that several are arranged in order of the wafer substrate, each composite grid
Unit includes gate regions and active area：
The gate regions include：
The two adjacent grooves to be formed are etched in the designated position of the gate regions, are respectively set in described two grooves
There are first groove grid and second groove grid；
In the planar gate that the surface of the gate regions is arranged, the planar gate is connected with first groove grid；And
The gate oxidation of the first groove grid, second groove grid and planar gate and the wafer substrate is isolated
Layer, and cover the isolated protective layer of the planar gate outer surface；
The active area includes the trench gate active area and planar gate active area positioned at the gate regions both sides, wherein institute
It includes the N well regions being distributed from bottom to top, p-well region, P+ doped regions and N+ doping to state trench gate active area and planar gate active area
Diffusion region.
In one embodiment, the N well regions are the N-type impurities by injecting the first dosage to the active area belonging to it,
And the lower section of active area of the N-type impurity belonging to the N well regions is made to spread, while in horizontal proliferation to the planar gate and being somebody's turn to do
The lower section at the edge that the active area belonging to N well regions is in contact and the region formed；
The p-well region is and to make the p type impurity by injecting the p type impurity of the second dosage to its corresponding described N well region
The lower section of active area belonging to the p-well region is spread, at the same in horizontal proliferation to the planar gate with having belonging to the p-well region
The lower section at the edge that source region is in contact and the region formed；
The doped diffusion regions N+ are the N-type impurities by spreading third dosage to its corresponding described p-well region, after pass through
Over etching and be retained in the region below the planar gate, wherein the bottom of the doped diffusion regions N+ be higher than its corresponding institute
State the surface that p-well region is exposed by this etching；
The P+ doped regions are the surface injections the exposed by being etched to its corresponding described p-well region by this
The p type impurity of four dosage and the region formed, wherein the side of the P+ doped regions is mixed by spreading the corresponding N+
Miscellaneous diffusion region is connected；
Wherein, the N well regions of the trench gate active area, p-well region and the side of the doped diffusion regions N+ terminate in described first
The gate oxide of trench-gate side wall.
In one embodiment, the planar gate is disconnected with second groove grid.
In one embodiment, the second groove grid is hanging or is grounded.
In one embodiment, the planar gate is also connected with second groove grid.
In one embodiment, further include the covering isolated protective layer, the trench gate active area P+ doped regions and
The metal layer of the P+ doped regions of the planar gate active area.
In one embodiment, first dosage is less than the third dosage, and second dosage is less than the described 4th
Dosage.
In one embodiment, composite grid unit described in each two forms a cellular in a manner of mirror symmetry.
In one embodiment, the cellular is hexagonal cells structure, and multiple cellulars are with cellular distribution
On wafer substrate；Alternatively, the cellular be rectangular structure cell, and multiple cellular matrix forms be distributed in wafer base
On piece；Alternatively, the cellular is bar shaped structure cell, and multiple cellulars are abreast distributed on wafer substrate.
In one embodiment, further include the back structures for being formed in the wafer substrate back, the back structures are
Punch structure, non-punch structure or soft punch structure.
Compared with prior art, one or more embodiments of the invention can have the following advantages that：
1) igbt chip provided by the invention has the compound grid structure of planar gate and trench-gate, while in planar gate
Second groove grid (i.e. empty grid) is introduced between pole and first groove grid to separate the two, it can effective mask plane grid knot
It is interfered with each other between structure and trench gate structure the two, while optimizing the capacitance that outputs and inputs of composite grid, optimization chip opens electric current
Change rate, and reduce switching loss.
2) in the present invention, the second groove grid between planar gate and first groove grid (i.e. empty grid) is by outstanding
Empty, ground connection or the mode being connected with grid interfere with each other between effective mask plane grid structure and trench gate structure the two, simultaneously
Optimization composite grid outputs and inputs capacitance, and optimization chip opens alive change rate, and reduces switching loss.
3) igbt chip provided by the invention has the compound grid structure of planar gate and first groove grid, can be effective
Solve the problems, such as that the high on-state voltage drop of planar gate, low current density and trench-gate damping ability and safety operation area are limited, from
And igbt chip density is significantly promoted, and retain trench gate low pass consumption, high current density and plane grid width safety operation area
Characteristic.
4) first groove grid of the invention and planar gate can be realized by shared polysilicon gate to IGBT cores
The control of piece grid.
Other features and advantages of the present invention will be illustrated in the following description, and partly becomes from specification
It is clear that understand through the implementation of the invention.The purpose of the present invention and other advantages can be by wanting in specification, right
Specifically noted structure is sought in book and attached drawing to realize and obtain.
Description of the drawings
Attached drawing is used to provide further understanding of the present invention, and a part for constitution instruction, the reality with the present invention
It applies example and is used together to explain the present invention, be not construed as limiting the invention.In the accompanying drawings：
Fig. 1 shows the diagrammatic cross-section of half cellular of the igbt chip in the prior art with planar gate structure；
Fig. 2 shows the diagrammatic cross-sections of half cellular of the igbt chip in the prior art with trench gate structure；
Fig. 3 shows the section signal of half cellular of the igbt chip in the prior art for having and accompanying grid and trench gate structure
Figure；
Fig. 4 shows the igbt chip hexagon member with the compound grid structure containing empty grid in first embodiment of the invention
The schematic top plan view of born of the same parents；
Fig. 5 shows the igbt chip with the compound grid structure containing empty grid in first embodiment of the invention along the sides A-A '
To cellular sectional view；
Fig. 6 shows the rectangular cellular of igbt chip with the compound grid structure containing empty grid in first embodiment of the invention
Schematic top plan view；
Fig. 7 shows the igbt chip bar shaped cellular with the compound grid structure containing empty grid in first embodiment of the invention
Schematic top plan view；
Fig. 8 shows the igbt chip with the compound grid structure containing empty grid in second embodiment of the invention along the sides A-A '
To cellular sectional view.
Specific implementation mode
Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings and examples, how to be applied to the present invention whereby
Technological means solves technical problem, and the realization process for reaching technique effect can fully understand and implement.It needs to illustrate
As long as not constituting conflict, each embodiment in the present invention and each feature in each embodiment can be combined with each other,
It is formed by technical solution within protection scope of the present invention.
First embodiment
Fig. 4 is the igbt chip hexagonal cells with the compound grid structure containing empty grid in first embodiment of the invention
Schematic top plan view.As shown in figure 4, each cellular 410 is hexagonal cells structure, and multiple cellulars are distributed in crystalline substance with cellular
Physa on piece.Wherein, each cellular 410 includes gate regions 401 and 402 He of trench gate active area positioned at 401 both sides of gate regions
Planar gate active area 403.
In order to illustrate more clearly of the structure of igbt chip shown in Fig. 4, below with igbt chip shown in Fig. 4 along A-A '
It is described in detail for the cellular sectional view in direction.
Fig. 5 is igbt chip in first embodiment of the invention along the cellular sectional view in the directions A-A '.As shown in figure 5, one
Cellular mainly includes the composite grid unit of two mirror symmetries.Since two composite grid cellular constructions in Fig. 5 are symmetrical, under
Face illustrates the concrete structure of cellular only by taking the composite grid unit on the right as an example.
As shown in figure 5, composite grid unit includes gate regions and active area.Wherein, gate regions include first groove grid
501, second groove grid 502, planar gate 503, gate oxide 504 and isolated protective layer 505, active area include being located at grid
The trench gate active area and planar gate active area of area both sides, trench gate active area and planar gate active area include from bottom to top according to
N well regions 506, p-well region 507, P+ doped regions 508 and the doped diffusion regions N+ 509 of secondary distribution.
First groove grid 501 and second groove grid 502 are located at the side of gate regions, the specific bit in gate regions
It sets in two adjacent grooves that etching is formed downwards.First groove grid 501 and second groove grid 502 be pass through respectively to
Polysilicon is filled in first groove and second groove and is formed.In the present embodiment, first groove grid 501 is as routine
Polysilicon gate, second groove grid 502 is as empty grid.
Planar gate 503 is located at the surface of gate regions, and is connected with first groove grid 501.Specifically, planar gate
503 raceway groove is distributed in crystal column surface, and the channel vertical of first groove grid 501 in crystal column surface and is distributed in wafer ontology,
Planar gate 503 is linked together with first groove grid 501 by polysilicon, and what it is collectively as composite grid unit is in rugosity
Grid.
First groove grid 501, second groove grid 502 and planar gate 503 and wafer base is isolated in gate oxide 504
Piece.505 overlay planes grid of isolated protective layer, 503 outer surface, the metal for being effectively isolated planar gate 503 with being used as source electrode
Layer 510.Gate oxide 504 and isolated protective layer 505 are formed by different processing steps.
Preferably, planar gate 503 is disconnected with second groove grid 502.Specifically, by second groove grid 502
The gate oxide 504 of covering makes planar gate 503 not contacted with second groove grid 502.Preferably, second groove grid
502 hanging or ground connection and as empty grid.Second groove grid 502 between planar gate 503 and first groove grid 501 passes through
Hanging or ground connection mode can be interfered with each other effectively between mask plane grid structure and trench gate structure the two, while be optimized compound
Grid output and input capacitance, and optimization chip opens alive change rate, and reduces switching loss.
N well regions 506 are the N-type impurities by injecting the first dosage to the active area belonging to it, and make the N-type impurity at this
The lower section of active area belonging to N well regions 506 is spread, at the same in horizontal proliferation to planar gate 503 with belonging to the N well regions 506
The lower section at the edge that active area is in contact and the region formed, the junction depth of N well regions 506 are less than the depth of first groove.In this reality
It applies in example, the first dosage can be 1013~1014cm-2, N-type impurity can be phosphorus.Particularly, the N well regions of trench gate active area
506 side terminates in the gate oxide 504 of 501 side wall of first groove grid.It is located in the N well regions 506 of planar gate active area flat
The part of 503 lower section of face grid is arc-shaped, and is in contact with the gate oxide 504 of 503 lower section of planar gate.
P-well region 507 is the p type impurity by injecting the second dosage to its corresponding N well region 506, and the p type impurity is made to exist
The lower section of active area belonging to the p-well region 507 is spread, at the same in horizontal proliferation to planar gate 503 with belonging to the p-well region 507
The active area lower section at edge being in contact and the region formed.In the present embodiment, the second dosage can be 1014~8*
1014cm-2, p type impurity can be boron.It should be noted that N well regions 506 can be further downward with the diffusion of p-well region 507
Diffusion.At this point, the junction depth of N well regions 506 can slightly increase.Particularly, the side of the p-well region 507 of trench gate active area terminates in
The gate oxide 504 of one trench-gate, 501 side wall.It is located at 503 lower section of planar gate in the p-well region 507 of planar gate active area
Part is arc-shaped, and is in contact with the gate oxide 504 of 503 lower section of planar gate.
The doped diffusion regions N+ 507 are the N-type impurities by spreading third dosage to its corresponding p-well region 506, are passed through later
It etches and is retained in the region below gate regions.Specifically, by directly spreading the N-type impurity of third dosage to p-well region 507,
Wherein, the lower section diffusion of active area of the N-type impurity of third dosage belonging to it, while in horizontal proliferation to planar gate 503
The lower section at the edge being in contact with the active area belonging to it and form N+ doped regions.It should be noted that N well regions 506, p-well region
507 can the further diffusion downwards with the diffusion of N+ doped regions.At this point, the junction depth of N well regions 506 and p-well region 507 can slightly increase
Greatly.In the present embodiment, the first dosage is less than third dosage.Then etching N+ doped regions and p-well region 507 below are positioned at having
The part of source region makes active area form the step structure that height is 0.5~1 μm, retains the part that N+ doped regions are located at gate regions
To form the doped diffusion regions N+ 509.It should be noted that in order to etch the doped diffusion regions N+ of active area completely, N+ doping is expanded
The bottom in area 509 is dissipated higher than the surface that p-well region 507 is exposed by this etching.Optionally, if can ensure to carve completely
Lose the doped diffusion regions N+ 509 of active area, the bottoms of the doped diffusion regions N+ 509 can also with p-well region 507 by this etching and
The surface exposed is generally aligned in the same plane.Particularly, the side of the doped diffusion regions N+ 509 of trench gate active area terminates in the first ditch
The gate oxide 504 of 501 side wall of slot grid.
P+ doped regions 508 are the surface injections the 4th exposed by being etched to its corresponding p-well region 507 by this
The p type impurity of dosage and the region formed, the wherein side of P+ doped regions 508, which pass through, spreads the corresponding doped diffusion regions N+
509 are connected.In the present embodiment, the second dosage is less than the 4th dosage, and the 4th dosage can be 1015~5 × 1015cm-2, p-type is miscellaneous
Matter can be boron.
Particularly, by the way that N well regions 506, p-well region 507 and the dopant dose and knot of the doped diffusion regions N+ 509 is rationally arranged
It is deep so that the raceway groove of first groove grid 501 is identical with the threshold voltage of the raceway groove of planar gate 503, so as to make first
The raceway groove of trench-gate 501 and the raceway groove of planar gate 503 are opened and are simultaneously turned off simultaneously.
Preferably, composite grid unit further includes 508 and of P+ doped regions for covering isolated protective layer 505, trench gate active area
The metal layer 510 of the P+ doped regions 508 of planar gate active area.In the present embodiment, 505 upper table of isolated protective layer on gate regions
Face is covered with metal layer 510.Optionally, can also include between 505 upper surface of gate regions isolated protective layer and metal layer 510
Other film layer structures, are not especially limited herein.In the present embodiment, it is covered with metal layer on active area P+ doped regions 508
510, and by high annealing (400~450 degree) so as to form Ohmic contact between P+ doped regions 508 and metal layer 510.
Optionally, rectangular cellular as shown in FIG. 6 or item as shown in Figure 7 can also be used in first embodiment of the invention
Shape structure cell is realized, so that the planar gate and trench-gate is coexisted in same chip.Specifically, as shown in fig. 6, each cellular
610 be rectangular structure cell, and 610 matrix form of multiple cellulars be arranged on wafer substrate.Each cellular 610 includes grid
Area 601 and trench gate active area 602 and planar gate active area 603 positioned at 601 both sides of gate regions.As shown in fig. 7, each cellular
710 be bar shaped structure cell, and multiple cellulars 710 are abreast distributed on wafer substrate.Each cellular 710 includes gate regions
701 and trench gate active area 702 and planar gate active area 703 positioned at 701 both sides of gate regions.
It should be noted that punch structure, non-punch structure or soft punch may be used in the back side of wafer substrate
Structure.
In the present embodiment, igbt chip has the compound grid structure of planar gate and trench-gate, while in planar gate
Second groove grid (i.e. empty grid) is introduced between pole and first groove grid to separate the two, it can effective mask plane grid knot
It is interfered with each other between structure and trench gate structure the two, while optimizing the capacitance that outputs and inputs of composite grid, optimization chip opens electric current
Change rate, and reduce switching loss.
Also, the compound grid structure is equivalent to introduces trench gate in planar gate JFET bulk zones, or is equivalent in ditch
Quote planar gate in slot grid non-active area.Trench gate is introduced in planar gate JFET bulk zones, takes full advantage of igbt chip
Space increases new raceway groove under the premise of not influencing planar gate current density, to increase current density.In trench gate
Planar gate is quoted in non-active area, improves electric current and heat distribution in trench gate body.It is low that the compound grid structure remains trench gate
Logical consumption, high current density and the characteristic of plane grid width safety operation area.Moreover, because introducing empty grid, IGBT is optimized
Chip interior field distribution, to improve the damping ability of planar gate.
To sum up, the present invention not only can significantly promote igbt chip density, and it is close to retain trench gate low pass consumption, high current
The characteristic of degree and plane grid width safety operation area, but also can effective phase between mask plane grid structure and trench gate structure the two
Mutually interference, while optimizing the capacitance that outputs and inputs of composite grid, optimization chip opens alive change rate, and reduces switch damage
Consumption.
Second embodiment
Difference lies in planar gates to be also connected with second groove grid (i.e. empty grid) with first embodiment for the present embodiment.
Fig. 8 is the igbt chip with the compound grid structure containing empty grid in second embodiment of the invention along the directions A-A '
Cellular sectional view.As shown in figure 8, difference is arranged in the gate oxide 804 of Fig. 8 and the gate oxide 504 of Fig. 5.
Specifically, gate oxide 804 be isolated first groove grid 501, second groove grid 502 and planar gate 503 with
Wafer substrate.The polysilicon of planar gate 503 and the polysilicon of first groove grid 501 link together, collectively as compound
The grid in rugosity of grid unit.Polycrystalline of the polysilicon of planar gate 503 also with second groove grid 502 (i.e. empty grid)
Silicon is connected.That is, gate oxide, grid oxygen is not present between planar gate 503 and second groove grid 502 (i.e. empty grid)
Change layer 804 without isolated plane grid 503 and second groove grid 502 (i.e. empty grid).Planar gate 503 and first groove grid
Second groove grid 502 (i.e. empty grid) between pole 501 by with the side of composite grid unit being connected in the grid of rugosity
Formula can be interfered with each other effectively between mask plane grid structure and trench gate structure the two, while optimize outputting and inputting for composite grid
Capacitance, optimization chip opens alive change rate, and reduces switching loss.
While it is disclosed that embodiment content as above but described only to facilitate understanding the present invention and adopting
Embodiment is not limited to the present invention.Any those skilled in the art to which this invention pertains are not departing from this
Under the premise of the disclosed spirit and scope of invention, any modification and change can be made in the implementing form and in details,
But protection scope of the present invention still should be subject to the scope of the claims as defined in the appended claims.
Claims (10)
1. a kind of igbt chip with the compound grid structure containing empty grid, which is characterized in that including wafer substrate and be formed in institute
State the positive composite grid unit that several are arranged in order of wafer substrate, each composite grid unit includes gate regions and active
Area：
The gate regions include：
The two adjacent grooves to be formed are etched in the designated position of the gate regions, is respectively arranged in described two grooves
One trench-gate and second groove grid；
In the planar gate that the surface of the gate regions is arranged, the planar gate is connected with first groove grid；And
The gate oxide of the first groove grid, second groove grid and planar gate and the wafer substrate is isolated, and
Cover the isolated protective layer of the planar gate outer surface；
The active area includes the trench gate active area and planar gate active area positioned at the gate regions both sides, wherein the ditch
Slot grid active area and planar gate active area include the N well regions being distributed from bottom to top, p-well region, P+ doped regions and N+ doping diffusions
Area.
2. igbt chip according to claim 1, which is characterized in that
The N well regions are the N-type impurities by injecting the first dosage to the active area belonging to it, and make the N-type impurity in the N traps
The lower section of active area belonging to area is spread, at the same in horizontal proliferation to the planar gate with the active area phase belonging to the N well regions
The lower section at the edge of contact and the region formed；
The p-well region is and to make the p type impurity at this by injecting the p type impurity of the second dosage to its corresponding described N well region
The lower section of active area belonging to p-well region is spread, at the same in horizontal proliferation to the planar gate with the active area belonging to the p-well region
The lower section at the edge being in contact and the region formed；
The doped diffusion regions N+ are the N-type impurities by spreading third dosage to its corresponding described p-well region, later by carving
The region lost and be retained in below the planar gate, wherein the bottom of the doped diffusion regions N+ is higher than its corresponding described P
The surface that well region is exposed by this etching；
The P+ doped regions are that the surface exposed by being etched to its corresponding described p-well region by this injects the 4th dose
The p type impurity of amount and the region formed, wherein the side of the P+ doped regions passes through and spreads corresponding N+ doping and expand
Area is dissipated to be connected；
Wherein, the N well regions of the trench gate active area, p-well region and the side of the doped diffusion regions N+ terminate in the first groove
The gate oxide of gate lateral wall.
3. igbt chip according to claim 1, which is characterized in that
The planar gate is disconnected with second groove grid.
4. igbt chip according to claim 3, which is characterized in that
The second groove grid is hanging or is grounded.
5. igbt chip according to claim 1, which is characterized in that
The planar gate is also connected with second groove grid.
6. igbt chip according to claim 2, which is characterized in that further include the covering isolated protective layer, the ditch
The metal layer of the P+ doped regions of the P+ doped regions of slot grid active area and the planar gate active area.
7. igbt chip according to claim 2, which is characterized in that first dosage is less than the third dosage, institute
It states the second dosage and is less than the 4th dosage.
8. igbt chip according to any one of claim 1 to 5, which is characterized in that composite grid unit described in each two
A cellular is formed in a manner of mirror symmetry.
9. igbt chip according to claim 8, which is characterized in that
The cellular is hexagonal cells structure, and multiple cellulars are distributed in cellular on wafer substrate；Alternatively,
The cellular be rectangular structure cell, and multiple cellular matrix forms be distributed on wafer substrate；Alternatively,
The cellular is bar shaped structure cell, and multiple cellulars are abreast distributed on wafer substrate.
10. igbt chip according to any one of claim 1 to 5, which is characterized in that further include being formed in the wafer
The back structures of substrate back, the back structures are punch structure, non-punch structure or soft punch structure.
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| CN201810148858.0A CN108428740B (en) | 2018-02-13 | 2018-02-13 | IGBT chip with composite gate structure containing virtual gate |
| PCT/CN2018/106112 WO2019157818A1 (en) | 2018-02-13 | 2018-09-18 | Igbt chip having composite gate structure comprising dummy gate |
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| CN201810148858.0A CN108428740B (en) | 2018-02-13 | 2018-02-13 | IGBT chip with composite gate structure containing virtual gate |
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| CN108899319A (en) * | 2018-08-30 | 2018-11-27 | 赵少峰 | A kind of layouts and layout method increasing VDMOS gully density |
| CN109801911A (en) * | 2019-01-29 | 2019-05-24 | 上海擎茂微电子科技有限公司 | A kind of integrated IGBT device of mixing cellular type |
| WO2019157818A1 (en) * | 2018-02-13 | 2019-08-22 | 株洲中车时代电气股份有限公司 | Igbt chip having composite gate structure comprising dummy gate |
| CN111128725A (en) * | 2018-10-30 | 2020-05-08 | 株洲中车时代电气股份有限公司 | IGBT device preparation method |
| GB2592032A (en) * | 2020-02-13 | 2021-08-18 | Mqsemi Ag | Trench planar MOS cell for transistors |
| WO2022063210A1 (en) * | 2020-09-24 | 2022-03-31 | 比亚迪半导体股份有限公司 | Semiconductor cell structure, igbt cell structure and preparation method therefor, and semiconductor structure |
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Also Published As
| Publication number | Publication date |
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| CN108428740B (en) | 2020-09-04 |
| WO2019157818A1 (en) | 2019-08-22 |
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Effective date of registration: 20200925 Address after: 412001 Room 309, floor 3, semiconductor third line office building, Tianxin hi tech park, Shifeng District, Zhuzhou City, Hunan Province Patentee after: Zhuzhou CRRC times Semiconductor Co.,Ltd. Address before: The age of 412001 in Hunan Province, Zhuzhou Shifeng District Road No. 169 Patentee before: ZHUZHOU CRRC TIMES ELECTRIC Co.,Ltd. |