CN106783952A - A kind of trench gate IGBT device - Google Patents
A kind of trench gate IGBT device Download PDFInfo
- Publication number
- CN106783952A CN106783952A CN201611207993.5A CN201611207993A CN106783952A CN 106783952 A CN106783952 A CN 106783952A CN 201611207993 A CN201611207993 A CN 201611207993A CN 106783952 A CN106783952 A CN 106783952A
- Authority
- CN
- China
- Prior art keywords
- well
- floating
- false grid
- grid
- igbt device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 62
- 229920005591 polysilicon Polymers 0.000 claims abstract description 49
- 238000000034 method Methods 0.000 abstract description 20
- 230000008569 process Effects 0.000 abstract description 16
- 230000001413 cellular effect Effects 0.000 description 8
- 230000000694 effects Effects 0.000 description 6
- 238000005530 etching Methods 0.000 description 6
- 230000035755 proliferation Effects 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 238000002360 preparation method Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000004080 punching Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 230000001052 transient effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
- H01L29/7398—Vertical transistors, e.g. vertical IGBT with both emitter and collector contacts in the same substrate side
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
- H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
- H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
The invention discloses a kind of trench gate IGBT device, including the emitter layer, N-type drift layer, N-type cushion, the P+ electrode layers that set gradually from top to bottom, the p-well and floating p-well being connected with the emitter layer are provided with the N-type drift layer, the p-well both sides are provided with polysilicon gate, the side adjacent with the polycrystalline silicon grid layer is provided with false grid in the floating p-well, and the false grid are used to separate the floating p-well and the polycrystalline silicon grid layer.The trench gate IGBT device, false grid are set by adjacent with polycrystalline silicon grid layer side in the floating p-well, the floating p-well and the polycrystalline silicon grid layer are separated, efficiently reduce IGBT device gate voltage overshoot in opening process, so as to reduce the turn-on consumption and EMI of device, more preferable switching characteristic and reliability are obtained.
Description
Technical field
The present invention relates to technical field of semiconductor device preparation, more particularly to a kind of trench gate IGBT device.
Background technology
There is the phenomenon of gate voltage overshoot in traditional trench gate IGBT, can cause device opens damage in opening process
Consumption (Eon) and electromagnetic interference (EMI) increase, and then reduce the reliability and service life of device.
For this problem, a kind of existing solution is, by using the floating depth p-well for polycrystalline trench gate separate
Structure, significantly reduces the device transient state gate voltage overshoot that hole current is caused by trenched side-wall in opening process,
So as to reduce the turn-on consumption and electromagnetic interference of device.
However, to ensure the pressure-resistant of trench gate IGBT cellulars, in this solution, floating depth p-well must be diffused to
Enough depth (would generally be than the depth depth of groove), to avoid horizontal proliferation from causing p-well and polysilicon gate trenched side-wall
Contact, it has to be ensured that there is enough distances between polysilicon gate and p-well in structure, which greatly limits trench gate
The width design free degree of IGBT cellulars, limits the further minute design of IGBT structure cells.
The content of the invention
It is an object of the invention to provide a kind of trench gate IGBT device, by setting false grid by floating p-well and polysilicon gate
Separate, efficiently reduce device gate voltage overshoot in opening process, so as to reduce device turn-on consumption and
EMI, obtains more preferable switching characteristic and reliability, together.
In order to solve the above technical problems, a kind of trench gate IGBT device is the embodiment of the invention provides, including from top to bottom
Emitter layer, N-type drift layer, N-type cushion, the P+ electrode layers for setting gradually, be provided with the N-type drift layer with it is described
The p-well and floating p-well of emitter layer connection, the p-well both sides are provided with polysilicon gate, many with described in the floating p-well
The adjacent side of crystal silicon gate layer is provided with false grid, and the false grid are used to separate the floating p-well and the polycrystalline silicon grid layer.
Wherein, the deep equality of the depth of the false grid and the polysilicon gate.
Wherein, the width of the false grid is equal with the width of the polysilicon gate.
Wherein, the false grid are parallel in depth direction with the polysilicon gate.
Wherein, depth of the depth of the polysilicon gate more than or equal to the floating p-well.
Wherein, the both sides of the floating p-well are provided with the described false grid of same size.
The trench gate IGBT device that the embodiment of the present invention is provided, compared with prior art, with advantages below：
Trench gate IGBT device provided in an embodiment of the present invention, including emitter layer, the N-type drift for setting gradually from top to bottom
Layer, N-type cushion, P+ electrode layers are moved, the p-well and floating P being connected with the emitter layer are provided with the N-type drift layer
Trap, the p-well both sides are provided with polysilicon gate, and the side adjacent with the polycrystalline silicon grid layer is provided with the floating p-well
False grid, the false grid are used to separate the floating p-well and the polycrystalline silicon grid layer.
The trench gate IGBT device, false grid are set by adjacent with polycrystalline silicon grid layer side in floating p-well, will be floating
Empty p-well is separated with polycrystalline silicon grid layer, IGBT device gate voltage overshoot in opening process is efficiently reduced, so as to reduce
The turn-on consumption and EMI of device, obtains more preferable switching characteristic and reliability.Meanwhile, using false grid by floating p-well and polycrystalline
Si-gate is separated, the limitation to cellular width that floating p-well horizontal proliferation can be avoided to cause, by adjusting false grid and polysilicon gate
The distance between can obtain the bigger cellular width design free degree.
Brief description of the drawings
In order to illustrate more clearly about the embodiment of the present invention or technical scheme of the prior art, below will be to embodiment or existing
The accompanying drawing to be used needed for having technology description is briefly described, it should be apparent that, drawings in the following description are the present invention
Some embodiments, for those of ordinary skill in the art, on the premise of not paying creative work, can also basis
These accompanying drawings obtain other accompanying drawings.
Fig. 1 is a kind of structural representation of specific embodiment of trench gate IGBT device provided in an embodiment of the present invention.
Specific embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is carried out clear, complete
Site preparation is described, it is clear that described embodiment is only a part of embodiment of the invention, rather than whole embodiments.It is based on
Embodiment in the present invention, it is every other that those of ordinary skill in the art are obtained under the premise of creative work is not made
Embodiment, belongs to the scope of protection of the invention.
Fig. 1 is refer to, Fig. 1 is a kind of knot of specific embodiment of trench gate IGBT device provided in an embodiment of the present invention
Structure schematic diagram.
In a kind of specific embodiment, the trench gate IGBT device, including the emitter stage for setting gradually from top to bottom
Layer 10, N-type drift layer 20, N-type cushion 30, P+ electrode layers 40, are provided with and the emitter stage in the N-type drift layer 20
The p-wells 14 and floating p-well 12 of the connection of layer 10, the both sides of the p-well 14 are provided with polysilicon gate 11, in the floating p-well 12 with
11 layers of adjacent side of the polysilicon gate are provided with false grid 13, and the false grid 13 are used for the floating p-well 12 is more with described
11 layers of crystal silicon grid are separated.
The trench gate IGBT device, false grid are set by floating p-well 12 with 11 layers of adjacent side of polysilicon gate
13, by floating p-well 12 and polysilicon gate, 11 layers separate, and efficiently reduce IGBT device grid voltage mistake in opening process
Punching, so as to reduce the turn-on consumption and EMI of device, obtains more preferable switching characteristic and reliability.
Meanwhile, floating p-well 12 is separated with polysilicon gate 11 using false grid 13, floating p-well horizontal proliferation can be avoided to make
Into the limitation to cellular width, by adjusting the distance between false grid 13 and polysilicon gate 11, bigger cellular can be obtained wide
Degree design freedom.
So, designer can design the IGBT device of the spacing of different false grid and polysilicon gate, meet various need
Will.And can be reduced by by the spacing of false grid and polysilicon gate, the less IGBT cellulars of size are obtained, be conducive to IGBT units
The further minute design of born of the same parents' structure.
It is pointed out that the embodiment of the present invention does not do specific limit for the set-up mode of false grid and the material of false grid
It is fixed, and false grid can be possibly even the false grid of polysilicon formation with polysilicon gate setting simultaneously, so hardly increase
Processing step, does not increase process costs, it is possible to improve the switching characteristic and reliability of device.
Further to reduce the complexity of technique, process costs, in a kind of specific embodiment, the false grid are reduced
The deep equality of 13 depth and the polysilicon gate 11, the width of the false grid 13 and the width phase of the polysilicon gate 11
Deng.
It is pointed out that the present invention is not specifically limited to the spacing between false grid 13 and polysilicon gate 11, false grid 13
Effect be to separate floating p-well 12 and polysilicon gate 11 so that horizontal during longitudinal diffusion of floating p-well 12 expands
Dissipate and shielded by false grid 13.Staff can design different in width by controlling the spacing between false grid 13 and polysilicon gate 11
Cellular.
Here false grid 13 can be provided in the left and right sides of floating p-well 12, or be set around floating p-well 12,
The present invention is not especially limited to the set-up mode of this false grid and the manufacture craft of false grid.
False grid 13 are to the width of the isolation effect of polysilicon gate 11 and floating p-well 12 and false grid 13, false grid 13 and polysilicon
Spacing between grid 11 is related, i.e., related to the minimum spacing between false grid 13 and polysilicon gate 11, to improve isolation effect, institute
State false grid 13 parallel in depth direction with the polysilicon gate 11.
So in the manufacturing process for carrying out false grid 13 and polysilicon gate 11, etching effect anisotropy is typically inclined to use
Dry etching very high so that horizontal erosion is less, and etching effect is good.
It is pointed out that false grid 13 can typically be performed etching simultaneously with polysilicon gate 11, the good directionality for so etching,
Easily parallel in etching depth direction, the present invention does not do specific limit to the false grid 13 and the etching technics of the polysilicon gate 11
It is fixed.
Set-up mode of the set-up mode of so false grid 13 completely with polysilicon gate is identical, it is only necessary to change layout design i.e.
Can, new technological process is increased without, advantageously reduce process costs.
To cause that false grid 13 thoroughly isolate polysilicon gate 11 with floating p-well 12, floating p-well 12 is eliminated to polysilicon gate 11
Influence, more than or equal to the depth of the floating p-well 12, so false grid 13 will can float completely for the depth of the polysilicon gate 11
The side of empty p-well 12 is blocked, and gate voltage overshoot of the device in opening process is reduced or eliminated, and improves the switching characteristic of device
And reliability.
In a kind of specific embodiment, the depth of the depth, the depth of polysilicon gate 11 and the floating p-well 12 of false grid 13
Degree is equal, and the technological parameter so allowed in the technological process of the trench gate IGBT device is less, while false grid 13 also can
Polysilicon gate 11, floating p-well are separated, the problem of the gate voltage overshoot for reducing IGBT device in opening process is reached.
Due in a trench gate IGBT structure cell, typically can be provided with groove in the both sides of floating p-well 12,
Polysilicon gate 11 can be provided with the side wall of groove, and, even if the wherein side of floating p-well 12 does not have polysilicon gate 11,
The side of floating p-well 12 sets false grid and can also reduce or eliminate the negative effect to the other structures of device.
In a kind of specific embodiment, the both sides of the floating p-well 12 are provided with the described false grid 13 of same size.
False grid 13 in embodiments of the present invention, can be provided in the column of the left surface of floating p-well 12 or right flank
False grid, can also be the false grid of the ring-type type set around floating p-well, and the specific shape and structure to the false grid of the invention is not
Do specific lower fixed, as long as floating p-well and polysilicon gate can be separated, it is to avoid the horizontal proliferation of floating p-well and polysilicon gate ditch
Groove measures contact, can be overshooted this makes it possible to reduce grid voltage of the IGBT device in opening process, so as to reduce
The turn-on consumption of IGBT device, improves the effective energy service efficiency of device so that device obtains more preferable switching characteristic.Together
When also reduce the generation of electromagnetic interference phenomenon, improve the anti-electromagnetic interference capability of IGBT device, improve the reliability of device
Property.
It is difficult in order to reduce technique it is pointed out that setting the false grid 13 of same size in the both sides of floating p-well 12
Degree, reduces process costs, while also ensure that the electrical uniformity of IGT device insides, improves the reliability of device.
The different false grid of size can also be set in the both sides of floating p-well 12 in the present invention, therefore the present invention is to described
The depth of false grid 13, width and it is not specifically limited with the manufacture craft of the spacing between polysilicon gate 11, false grid 13.
In sum, trench gate IGBT device provided in an embodiment of the present invention, by floating p-well with polycrystalline silicon grid layer
Adjacent side sets false grid, and floating p-well and polycrystalline silicon grid layer are separated, and efficiently reduces IGBT device in opening process
Middle gate voltage overshoot, so as to reduce the turn-on consumption and EMI of device, obtains more preferable switching characteristic and reliability.
Trench gate IGBT device provided by the present invention is described in detail above.Specific case used herein
Principle of the invention and implementation method are set forth, the explanation of above example is only intended to help and understands side of the invention
Method and its core concept.It should be pointed out that for those skilled in the art, not departing from the principle of the invention
Under the premise of, some improvement and modification can also be carried out to the present invention, these are improved and modification also falls into the claims in the present invention
In protection domain.
Claims (6)
1. a kind of trench gate IGBT device, it is characterised in that including set gradually from top to bottom emitter layer, N-type drift layer,
N-type cushion, P+ electrode layers, are provided with the p-well and floating p-well being connected with the emitter layer, institute in the N-type drift layer
State p-well both sides and be provided with polysilicon gate, the side adjacent with the polycrystalline silicon grid layer is provided with false grid in the floating p-well,
The false grid are used to separate the floating p-well and the polycrystalline silicon grid layer.
2. trench gate IGBT device as claimed in claim 1, it is characterised in that the depth of the false grid and the polysilicon gate
Deep equality.
3. trench gate IGBT device as claimed in claim 2, it is characterised in that the width of the false grid and the polysilicon gate
Width is equal.
4. trench gate IGBT device as claimed in claim 3, it is characterised in that the false grid are with the polysilicon gate in depth side
To parallel.
5. the trench gate IGBT device as described in claim 1-4 any one, it is characterised in that the depth of the polysilicon gate is big
In the depth equal to the floating p-well.
6. trench gate IGBT device as claimed in claim 5, it is characterised in that the both sides of the floating p-well are provided with identical chi
Very little described false grid.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201611207993.5A CN106783952A (en) | 2016-12-23 | 2016-12-23 | A kind of trench gate IGBT device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201611207993.5A CN106783952A (en) | 2016-12-23 | 2016-12-23 | A kind of trench gate IGBT device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN106783952A true CN106783952A (en) | 2017-05-31 |
Family
ID=58920016
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201611207993.5A Pending CN106783952A (en) | 2016-12-23 | 2016-12-23 | A kind of trench gate IGBT device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN106783952A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108428740A (en) * | 2018-02-13 | 2018-08-21 | 株洲中车时代电气股份有限公司 | A kind of igbt chip with the compound grid structure containing empty grid |
| CN117410346A (en) * | 2023-12-14 | 2024-01-16 | 深圳市森国科科技股份有限公司 | Trench gate silicon carbide MOSFET and manufacturing method |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102792448A (en) * | 2010-03-09 | 2012-11-21 | 富士电机株式会社 | Semiconductor device |
| US20140054644A1 (en) * | 2012-08-21 | 2014-02-27 | Rohm Co., Ltd. | Semiconductor device |
| CN106206698A (en) * | 2015-05-27 | 2016-12-07 | 丰田自动车株式会社 | Reverse-conducting insulated gate bipolar transistor |
-
2016
- 2016-12-23 CN CN201611207993.5A patent/CN106783952A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102792448A (en) * | 2010-03-09 | 2012-11-21 | 富士电机株式会社 | Semiconductor device |
| US20140054644A1 (en) * | 2012-08-21 | 2014-02-27 | Rohm Co., Ltd. | Semiconductor device |
| CN106206698A (en) * | 2015-05-27 | 2016-12-07 | 丰田自动车株式会社 | Reverse-conducting insulated gate bipolar transistor |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108428740A (en) * | 2018-02-13 | 2018-08-21 | 株洲中车时代电气股份有限公司 | A kind of igbt chip with the compound grid structure containing empty grid |
| WO2019157818A1 (en) * | 2018-02-13 | 2019-08-22 | 株洲中车时代电气股份有限公司 | Igbt chip having composite gate structure comprising dummy gate |
| CN108428740B (en) * | 2018-02-13 | 2020-09-04 | 株洲中车时代电气股份有限公司 | IGBT chip with composite gate structure containing virtual gate |
| CN117410346A (en) * | 2023-12-14 | 2024-01-16 | 深圳市森国科科技股份有限公司 | Trench gate silicon carbide MOSFET and manufacturing method |
| CN117410346B (en) * | 2023-12-14 | 2024-03-26 | 深圳市森国科科技股份有限公司 | Trench gate silicon carbide MOSFET and manufacturing method |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US10164025B2 (en) | Semiconductor device having termination trench | |
| CN101853852B (en) | Groove MOS (Metal Oxide Semiconductor) device integrating Schottky diodes in unit cell and manufacture method | |
| CN105914230A (en) | Ultra-low power consumption semiconductor power device and preparation method thereof | |
| CN108428740A (en) | A kind of igbt chip with the compound grid structure containing empty grid | |
| CN104882477A (en) | Trench gate IGBT device and manufacturing method thereof | |
| CN104009072A (en) | Insulated gate bipolar transistor and manufacturing method thereof | |
| CN104183634A (en) | Trench gate IGBT chip | |
| CN201663162U (en) | Trench MOS device with schottky diode integrated in unit cell | |
| US20150372075A1 (en) | Edge termination structure for a power integrated device and corresponding manufacturing process | |
| CN106783952A (en) | A kind of trench gate IGBT device | |
| CN108511521B (en) | Manufacturing method of IGBT chip with composite gate structure containing virtual gate | |
| CN114141621A (en) | Carrier storage groove gate bipolar transistor with split gate and preparation method thereof | |
| CN106783956A (en) | Groove field limiting ring terminal structure and preparation method with side wall variable-angle | |
| CN104810384A (en) | Power semiconductor device and manufacture method thereof and cut-off ring | |
| CN103681817A (en) | IGBT device and manufacturing method thereof | |
| CN202948932U (en) | Trench type IGBT layout structure | |
| CN106684134A (en) | Power semiconductor device and manufacturing method thereof | |
| CN108376713A (en) | A kind of semiconductor devices and preparation method thereof with super-junction structure | |
| CN104934469A (en) | IGBT terminal structure and manufacturing method thereof | |
| CN103839802A (en) | Manufacturing method of trench type IGBT structure | |
| CN106229339A (en) | The terminal structure of a kind of superjunction MOS and manufacture method thereof | |
| CN205564757U (en) | Ultra -low power consumption semiconductor power device | |
| CN111106043A (en) | Power semiconductor device cell structure, preparation method thereof and power semiconductor device | |
| CN105590958A (en) | Double-trench high-voltage shielded lateral insulated-gate bipolar device and preparation method thereof | |
| CN202423293U (en) | High-voltage transient voltage suppressor (TVS) chip |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20170531 |
|
| RJ01 | Rejection of invention patent application after publication |