CN109244128B - Semi-closed shielding grid IEGT device structure and manufacturing method thereof - Google Patents
Semi-closed shielding grid IEGT device structure and manufacturing method thereof Download PDFInfo
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 14
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 48
- 229920005591 polysilicon Polymers 0.000 claims abstract description 32
- 210000000746 body region Anatomy 0.000 claims abstract description 26
- 230000003647 oxidation Effects 0.000 claims abstract description 21
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 21
- 239000004065 semiconductor Substances 0.000 claims abstract description 20
- 239000000758 substrate Substances 0.000 claims abstract description 12
- 229910052751 metal Inorganic materials 0.000 claims description 37
- 239000002184 metal Substances 0.000 claims description 37
- 238000005530 etching Methods 0.000 claims description 22
- 238000000034 method Methods 0.000 claims description 22
- 239000012535 impurity Substances 0.000 claims description 13
- 238000000151 deposition Methods 0.000 claims description 9
- 229910052782 aluminium Inorganic materials 0.000 claims description 7
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 7
- 238000001259 photo etching Methods 0.000 claims description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims 1
- 229910052710 silicon Inorganic materials 0.000 claims 1
- 239000010703 silicon Substances 0.000 claims 1
- 230000003071 parasitic effect Effects 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 65
- 238000002347 injection Methods 0.000 description 5
- 239000007924 injection Substances 0.000 description 5
- 239000000969 carrier Substances 0.000 description 4
- 230000010355 oscillation Effects 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000011241 protective layer Substances 0.000 description 2
- 239000002131 composite material Substances 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- 230000007613 environmental effect Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
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Abstract
The invention belongs to the technical field of manufacturing of semiconductor devices, and relates to a semi-closed type shielding grid IEGT device structure, wherein a semiconductor substrate comprises a first conductive type drift layer, a second conductive type body region, a groove and a first conductive type emitter are arranged at the upper part of the first conductive type drift layer, the second conductive type body region and the first conductive type emitter are adjacent to one side of the groove, a polysilicon grid wrapped by a first oxidation layer and one side of the second oxidation layer is arranged in the groove, a semi-closed type shielding grid which is positioned outside the first oxidation layer and semi-closed type shielding grid is wrapped by the second oxidation layer, and the second oxidation layer is tightly attached to the inner wall of the groove; the device provided by the invention has the advantages that the semi-enclosed type shielding gate is arranged outside the polysilicon gate, so that the transverse induced current generated when the device is turned on and turned off can be effectively eliminated, the overshoot phenomenon of the gate voltage is avoided, the parasitic capacitance is reduced, the switching speed is increased, and the switching loss is reduced.
Description
Technical Field
The invention relates to a power semiconductor device and a manufacturing method thereof, in particular to a semi-closed shielding grid IEGT device structure and a manufacturing method thereof, belonging to the technical field of manufacturing of semiconductor devices.
Background
IGBT (Insulated Gate Bipolar Transistor) the insulated gate bipolar transistor is a composite fully-controlled voltage-driven power semiconductor device composed of a BJT (bipolar transistor) and a MOS (insulated gate field effect transistor), has the advantages of high input impedance of the MOSFET and low conduction voltage drop of the GTR, is a novel power semiconductor device integrating high frequency, high voltage resistance, low conduction voltage drop and a simple driving circuit, and is widely applied to the field of medium and high voltage. Along with the urgent energy crisis in the world and the improvement of environmental protection consciousness, the energy-saving efficient and simple-driving products become a new trend of market development. Due to various outstanding advantages of IGBTs, power semiconductor device manufacturers in various countries are striving to develop, and further improvement of withstand voltage and current capability of IGBTs is desired for application in higher voltage fields.
The electron injection enhancement gate transistor IEGT (Injection Enhancement Gate Transistor is developed from an IGBT, as shown in fig. 1, and is a schematic cross-sectional structure of a single cell of the conventional IEGT device, the IEGT utilizes a dummy region design to accumulate a large number of holes in the dummy region, so as to achieve charge balance, and can induce an electron injection enhancement effect (Injection Enhancement) of an emitter, an increase in the number of carriers enhances a conductivity modulation effect of the device, an on-state voltage drop is greatly reduced, and meanwhile, the carrier distribution balance in the drift region is improved, and the switching and steady-state characteristics of the device are optimized.
Currently, stability, switching loss and reliability are key challenges for power devices. In a normal working state, the IEGT utilizes the structure of the dummy region to enable a large number of hole carriers to flow into the dummy region, and when the IEGT is started, the carriers transversely move on the surface of the dummy region to form surface transverse current and form a certain potential difference with the bottom of the grid electrode. Such a potential difference creates an induced current in the gate, flowing through the gate equivalent resistance, enhancing the gate voltage, and gate voltage overshoot. Also, at the turn-off time, a large number of hole carriers in the dummy region need to flow out to form a surface transverse current, which causes an increase in gate voltage in the gate, resulting in the device not being turned off normally, and oscillation is formed. Both of the above cases are extremely prone to failure caused by excessive instantaneous voltage changes in the power device.
On the other hand, due to the adoption of the dummy area, the contact area between the grid electrode and the drain electrode is increased, and the design can cause overlarge Miller capacitance, so that the switching speed of the device is influenced, and further the switching loss of the device is influenced.
Therefore, there is a need for an IEGT structure with better reliability and smaller switching loss to overcome the shortcomings of the prior art.
Disclosure of Invention
The invention aims to overcome the defects in the prior art, and provides a semi-closed type shielding grid IEGT device structure and a manufacturing method thereof. In order to achieve the technical purpose, the technical scheme of the invention is as follows: the semiconductor substrate comprises a first conductive type drift layer, a second conductive type body region, a groove and a first conductive type emitter positioned at the upper part in the first conductive type drift layer are arranged at the upper part in the first conductive type drift layer, the second conductive type body region and the first conductive type emitter are adjacent to one side of the groove, and the semiconductor substrate is characterized in that a polysilicon grid wrapped by a first oxide layer and one side of the second oxide layer and a semi-closed shielding grid which is positioned at the outer side of the first oxide layer and semi-surrounds the polysilicon grid are arranged in the groove, the semi-closed shielding grid is wrapped by the second oxide layer, and the second oxide layer 11 is tightly adhered to the inner wall of the groove 13.
Further, the semi-closed shielding gate is distributed on one side of the polysilicon gate away from the first conductive type emitter and below the polysilicon gate, and one side of the polysilicon gate away from the first conductive type emitter and the first conductive type drift layer sequentially pass through the first oxide layer, the semi-closed shielding gate and the second oxide layer at intervals.
Further, an oxidation protection layer and an emitter metal are sequentially covered on the first conductive type drift layer, the emitter metal is in ohmic contact with the second conductive type body region and the first conductive type emitter, and the semi-closed shielding gate is electrically connected with the emitter metal.
Further, a first conductive type cut-off layer, a second conductive type collector and a collector metal are sequentially arranged below the first conductive type drift layer, and the collector metal is in ohmic contact with the second conductive type collector.
Further, one side of the second oxide layer, which is clung to the polysilicon gate, is a gate oxide layer.
In order to further achieve the technical purpose, the invention also provides a manufacturing method of the semi-closed shielding gate IEGT device structure, which is characterized by comprising the following steps:
the first step: selecting a semiconductor substrate, wherein the semiconductor substrate comprises a first conductive type drift layer, and etching the upper surface of the first conductive type drift layer by adopting an etching process to obtain a plurality of grooves;
and a second step of: forming a second oxide layer in the groove through oxidation, and continuously growing polysilicon in the groove, wherein the polysilicon fills the groove;
and a third step of: etching the polysilicon in the groove by adopting an etching process, etching one side of the groove to obtain an inner groove, and simultaneously obtaining a semi-closed shielding gate below the groove and on the other side of the groove;
fourth step: forming a first oxide layer in the inner groove through oxidation, continuously growing polysilicon in the first oxide layer and filling the inner groove, and obtaining a polysilicon grid in the inner groove;
fifth step, the method comprises the following steps; selectively injecting second conductivity type impurities into the surface of the first conductivity type drift layer by using a photoetching process and pushing a well to form a second conductivity type body region;
sixth step: selectively injecting first conductivity type impurities into the surface of the first conductivity type drift layer by using a photoetching process, pushing the well at a high temperature to obtain a first conductivity type emitter, and then depositing an oxidation protection layer;
seventh step: selectively etching the oxidation protection layer and the first conductive type emitter by adopting an etching process until the second conductive type body area is exposed;
eighth step: depositing metal aluminum on the front side of the device to form an emitter metal;
ninth step: sequentially injecting first conductive type impurities and second conductive type impurities into the back of the device to form a first conductive type cut-off layer and a second conductive type collector respectively;
tenth step: and depositing metal aluminum on the second conductive type collector to form collector metal, thereby completing the manufacture of the semi-enclosed shielding grid IEGT.
Further, for an N-type shielded gate IEGT device, the first conductivity type is N-type conductivity and the second conductivity type is P-type conductivity; for a P-type shielded gate IEGT device, the first conductivity type is P-type conductivity and the second conductivity type is N-type conductivity.
Compared with the traditional trench gate IGBT device, the invention has the following advantages:
1) According to the invention, the semi-enclosed shielding grid is arranged outside the polysilicon grid electrode, and is electrically connected to the N-type emitter electrode (namely, connected to zero potential), so that in the starting process of a device, the polysilicon grid electrode is subjected to forward voltage, the semi-enclosed shielding grid electrode is subjected to zero potential, when transverse current flows through a dummy region (a region of the N-type drift layer on one side of a groove), and when induced current flows through the semi-enclosed shielding grid electrode, the induced current is eliminated, therefore, the voltage condition on the isolated polysilicon grid electrode is not influenced, the grid voltage change generated by the transverse current is avoided, and the phenomenon of grid voltage overshoot is eliminated; in the turn-off process of the device, the transverse current is also eliminated when the transverse current flows through the semi-closed shielding grid, so that the device has higher capability of resisting the influence of collector voltage oscillation on the grid, and the normal turn-off of the device is ensured;
2) The semi-closed shielding grid isolates the grid electrode (namely the polycrystalline silicon grid electrode) from the collector electrode, so that the contact area of the grid electrode and the collector electrode is reduced, the Miller capacitance (Cgd) is greatly reduced, the switching speed is higher, and the switching loss is smaller.
Drawings
The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification, illustrate the invention and together with the description serve to explain, without limitation, the invention. In the drawings:
fig. 1 is a schematic cross-sectional structure of a conventional IEGT device cell unit.
Fig. 2 is a schematic cross-sectional view of the trench formed in embodiment 1 of the present invention.
Fig. 3 is a schematic cross-sectional view of a first oxide layer and a polysilicon-filled trench formed in embodiment 1 of the present invention.
Fig. 4 is a schematic cross-sectional view of the structure of forming an inner trench and a semi-closed shield gate in embodiment 1 of the present invention.
Fig. 5 is a schematic cross-sectional view of the formation of the second oxide layer and the polysilicon gate in embodiment 1 of the present invention.
Fig. 6 is a schematic cross-sectional view of a P-type body region formed in example 1 of the present invention.
Fig. 7 is a schematic cross-sectional structure of an N-type emitter and an oxide protective layer formed in embodiment 1 of the present invention.
Fig. 8 is a schematic diagram showing a cross-sectional structure of etching an N-type emitter and an oxide protective layer in embodiment 1 of the present invention.
Fig. 9 is a schematic cross-sectional structure of an emitter metal formed in embodiment 1 of the present invention.
Fig. 10 is a schematic cross-sectional view of the formation of an N-type stop layer, a P-type collector and collector metal in embodiment 1 of the present invention.
Reference numerals illustrate: 1. a P-type collector; 2. an N-type cut-off layer; 3. An N-type drift layer; 4. an N-type emitter; 5. a P-type body region; 6. a polysilicon gate; 7. a first oxide layer; 8. protecting the oxide layer; 9. an emitter metal; 10. semi-closed shielding grid; 11. a second oxide layer; 12. a collector metal; 13. a groove; 14. an inner groove.
Detailed Description
The following detailed description of the invention refers to the accompanying drawings and examples, which are included to provide a further understanding of the invention. It should be understood that the detailed description and specific examples, while indicating and illustrating the invention, are not intended to limit the invention.
In embodiment 1, the invention is further described by taking an N-type semi-closed shielding gate IEGT as an example, wherein the first conductivity type is N-type, and the second conductivity type is P-type;
as shown in fig. 10, an N-type semi-closed shielded gate IEGT device structure comprises an active region, wherein the active region comprises a plurality of device cell units connected in parallel, each device cell unit comprises a semiconductor substrate, a collector metal 12, a P-type collector 1, an N-type stop layer 2 and an N-type drift layer 3 are sequentially arranged in the cross section direction of each device cell unit from bottom to top, a P-type body region 5, a trench 13 and an N-type emitter 4 positioned at the upper part in the P-type body region 5 are arranged at the upper part in the N-type drift layer 3, the P-type body region 5 and the N-type emitter 4 are both adjacent to one side of the trench 13, a dummy region (namely a hole carrier injection region) is arranged at the other side of the trench 13, a polysilicon gate 6 wrapped by a first oxide layer 7 and a second oxide layer 11 is arranged in the trench 13, a semi-closed shielded gate 10 positioned at the outer side of the first oxide layer 7 is wrapped by the second oxide layer 11, and the semi-closed shielded gate 10 is tightly attached to the inner wall of the trench 13; one side of the second oxide layer 11, which is clung to the polysilicon gate 6, is a gate oxide layer;
the semi-closed shielding grid 10 is distributed on one side of the polycrystalline silicon grid 6 far away from the N-type emitter 4 and below the polycrystalline silicon grid, a first oxide layer 7, the semi-closed shielding grid 10 and a second oxide layer 11 are sequentially arranged between one side of the polycrystalline silicon grid 6 far away from the N-type emitter 4 and the N-type drift layer 3 at intervals, and the polycrystalline silicon grid 6 and the semi-closed shielding grid 10 are isolated through the first oxide layer 7;
an oxidation protection layer 8 and an emitter metal 9 are covered on the N-type drift layer 3 in sequence, the emitter metal 9 is in ohmic contact with the P-type body region 5 and the N-type emitter 4, the semi-closed shielding gate 10 is electrically connected with the emitter metal 9, and the polysilicon gate 6 is isolated from the emitter metal 9 through the oxidation protection layer 8;
an N-type cut-off layer 2, a P-type collector 1 and a collector metal 12 are sequentially arranged below the N-type drift layer 3, and the collector metal 12 is in ohmic contact with the P-type collector 1.
The manufacturing method of the N-type semi-closed shielding grid IEGT device structure of the embodiment 1 of the invention comprises the following steps:
as shown in fig. 2, the first step is: selecting a semiconductor substrate, wherein the semiconductor substrate comprises an N-type drift layer 3, and etching the upper surface of the N-type drift layer 3 by adopting an etching process to obtain a plurality of grooves 13;
as shown in fig. 3, the second step: forming a second oxide layer 11 in the groove 13 through oxidation, and continuing to grow polycrystalline silicon in the groove 13, wherein the polycrystalline silicon fills the groove 13;
as shown in fig. 4, the third step: etching polysilicon in the groove 13 by adopting an etching process, etching one side of the groove 13 to obtain an inner groove 14, and simultaneously obtaining a semi-closed shielding gate 10 below the groove 13 and on the other side;
as shown in fig. 5, the fourth step: forming a first oxide layer 7 in the inner groove 14 through oxidation, and continuously growing polysilicon in the first oxide layer and filling the inner groove 14 to obtain a polysilicon gate 6 in the inner groove 14;
as shown in fig. 6, a fifth step; selectively injecting P-type impurities into the surface of the N-type drift layer 3 by using a photoetching process and pushing a well to form a P-type body region 5, wherein the P-type body region 5 is positioned on one side of the groove 13 and is adjacent to the groove;
as shown in fig. 7, the sixth step: selectively injecting N-type impurities on the surface of the N-type drift layer 3 by using a photoetching process, pushing a well at a high temperature to obtain an N-type emitter 4, and then depositing an oxidation protection layer 8; the N-type emitter 4 is positioned in the P-type body region 5 and is adjacent to the groove 13;
as shown in fig. 8, seventh step: etching the oxidation protection layer 8 and the N-type emitter 4 selectively by adopting an etching process until the P-type body region 5 is exposed, so as to obtain metal contact holes for leading out the grid and the emitter;
the photolithography process can be used again, and P-type impurities are selectively injected into the surface of the P-type body region 5 to form a P-type well region for improving ohmic contact between metal and the P-type body region 5;
as shown in fig. 9, eighth step: depositing metal aluminum on the front surface of the device, and filling the metal contact holes with the metal aluminum to form emitter metal 9 for leading out an emitter;
as shown in fig. 10, a ninth step: the back of the device is sequentially injected with N-type impurities and P-type impurities to form an N-type cut-off layer 2 and a P-type collector 1 respectively, which are well known to those skilled in the art and are not repeated;
tenth step: and depositing metal aluminum on the P-type collector 1 to form a collector metal 12 for leading out the collector, thereby completing the manufacture of the semi-closed shielding grid IEGT.
The invention is characterized in that a semi-enclosed shielding grid 10 is arranged outside a polycrystalline silicon grid 6, and meanwhile, the semi-enclosed shielding grid 10 is electrically connected to an N-type emitter 9 (namely, connected to zero potential); in the device starting process, the polysilicon gate 6 is applied with forward voltage, the semi-closed shielding gate 10 is connected with zero potential, when transverse current flows in a dummy region (the region of the N-type drift layer 3 on one side of the groove 13), and when induced current flows in the semi-closed shielding gate 10, the induced current is eliminated, so that the voltage condition on the isolated polysilicon gate 6 is not influenced, the gate voltage change generated by the transverse current is avoided, and the phenomenon of gate voltage overshoot is eliminated; in the turn-off process of the device, the transverse current can be eliminated when the transverse current flows through the semi-closed shielding gate 10, so that the device has higher capability of resisting the influence of collector voltage oscillation on the gate, and the normal turn-off of the device is ensured;
in addition, since the semi-closed shielding gate 10 isolates the gate electrode (i.e., the polysilicon gate electrode 6) and the collector electrode, the contact area between the gate electrode and the collector electrode is reduced, and thus the miller capacitance (Cgd) is greatly reduced, the switching speed is faster, and the switching loss is smaller.
The invention and its embodiments have been described above with no limitation, and the actual construction is not limited to the embodiments of the invention as shown in the drawings. In summary, if one of ordinary skill in the art is informed by this disclosure, a structural manner and an embodiment similar to the technical solution should not be creatively devised without departing from the gist of the present invention.
Claims (5)
1. The semiconductor device structure comprises an active region, wherein the active region comprises a plurality of device cell units which are connected in parallel, the device cell units comprise a semiconductor substrate, the semiconductor substrate comprises a first conductive type drift layer (3), a second conductive type body region (5), a groove (13) and a first conductive type emitter (4) positioned at the inner upper part of the second conductive type body region (5) are arranged at the inner upper part of the first conductive type drift layer (3), the second conductive type body region (5) and the first conductive type emitter (4) are adjacent to one side of the groove (13), and the semiconductor device structure is characterized in that a silicon grid (6) wrapped by a first oxide layer (7) and one side of a second oxide layer (11) and a semi-closed type grid (10) which is positioned at the outer side of the first oxide layer (7) and is positioned at the semi-closed type grid (6) are arranged in the groove (13), the second conductive type body region (5) and the first conductive type emitter (4) is positioned at the inner upper part of the second conductive type drift layer (3), and the second conductive type body region (5) and the first conductive type emitter (4) is adjacent to one side of the groove (13), and the second conductive type emitter (11) is tightly attached to the inner wall of the groove (13);
the semi-closed shielding grid (10) is distributed on one side of the polycrystalline silicon grid (6) far away from the first conductive type emitter (4) and below the polycrystalline silicon grid, and the first oxide layer (7), the semi-closed shielding grid (10) and the second oxide layer (11) are sequentially arranged between one side of the polycrystalline silicon grid (6) far away from the first conductive type emitter (4) and the first conductive type drift layer (3);
an oxidation protection layer (8) and an emitter metal (9) are sequentially covered on the first conductive type drift layer (3), the emitter metal (9) is in ohmic contact with the second conductive type body region (5) and the first conductive type emitter (4), and the semi-closed shielding grid (10) is electrically connected with the emitter metal (9).
2. The semi-enclosed shielded gate IEGT device structure according to claim 1 wherein a first conductivity type cut-off layer (2), a second conductivity type collector (1) and a collector metal (12) are provided in order below the first conductivity type drift layer (3), the collector metal (12) being in ohmic contact with the second conductivity type collector (1).
3. The semi-enclosed shielded gate IEGT device structure according to claim 1 wherein a gate oxide layer is provided on a side of the second oxide layer (11) that is adjacent to the polysilicon gate (6).
4. The semi-enclosed shielded gate IEGT device structure and method of fabricating the same according to claim 1 wherein for an N-type shielded gate IEGT device, the first conductivity type is N-type conductivity and the second conductivity type is P-type conductivity; for a P-type shielded gate IEGT device, the first conductivity type is P-type conductivity and the second conductivity type is N-type conductivity.
5. The manufacturing method of the semi-closed shielding grid IEGT device structure is characterized by comprising the following steps:
the first step: selecting a semiconductor substrate, wherein the semiconductor substrate comprises a first conductive type drift layer (3), and etching the upper surface of the first conductive type drift layer (3) by adopting an etching process to obtain a plurality of grooves (13);
and a second step of: forming a second oxide layer (11) in the groove (13) through oxidation, and continuing to grow polycrystalline silicon in the groove (13), wherein the polycrystalline silicon fills the groove (13);
and a third step of: etching polysilicon in the groove (13) by adopting an etching process, etching one side of the groove (13) to obtain an inner groove (14), and simultaneously obtaining a semi-closed shielding gate (10) below the groove (13) and at the other side of the groove; the semi-closed shielding grid (10) is distributed on one side of the polycrystalline silicon grid (6) far away from the first conductive type emitter (4) and below the polycrystalline silicon grid, and the first oxide layer (7), the semi-closed shielding grid (10) and the second oxide layer (11) are sequentially arranged between one side of the polycrystalline silicon grid (6) far away from the first conductive type emitter (4) and the first conductive type drift layer (3);
fourth step: forming a first oxide layer (7) in the inner groove (14) through oxidation, continuously growing polysilicon in the first oxide layer and filling the inner groove (14), and obtaining a polysilicon grid (6) in the inner groove (14);
fifth step, the method comprises the following steps; selectively injecting second conductivity type impurities into the surface of the first conductivity type drift layer (3) by using a photoetching process and pushing a well to form a second conductivity type body region (5);
sixth step: selectively injecting first conductivity type impurities on the surface of the first conductivity type drift layer (3) by using a photoetching process, pushing the well at a high temperature to obtain a first conductivity type emitter (4), and then depositing an oxidation protection layer (8);
seventh step: selectively etching the oxidation protection layer (8) and the first conductive type emitter (4) until the second conductive type body region (5) is exposed by adopting an etching process;
eighth step: depositing metal aluminum on the front side of the device to form an emitter metal (9);
ninth step: sequentially injecting first conductive type impurities and second conductive type impurities into the back of the device to form a first conductive type cut-off layer (2) and a second conductive type collector (1) respectively;
tenth step: and depositing metal aluminum on the second conductive type collector (1) to form a collector metal (12), thereby completing the manufacture of the semi-closed shielding grid IEGT.
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| JP2023542401A (en) * | 2020-09-24 | 2023-10-06 | 比亜迪半導体股▲ふん▼有限公司 | Semiconductor cell structure, IGBT cell structure, semiconductor structure and manufacturing method thereof |
| CN116153989A (en) * | 2021-11-23 | 2023-05-23 | 无锡华润华晶微电子有限公司 | IEGT structure and manufacturing method thereof |
| CN117650164A (en) * | 2023-10-31 | 2024-03-05 | 海信家电集团股份有限公司 | Semiconductor device with a semiconductor device having a plurality of semiconductor chips |
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| US8441046B2 (en) * | 2010-10-31 | 2013-05-14 | Alpha And Omega Semiconductor Incorporated | Topside structures for an insulated gate bipolar transistor (IGBT) device to achieve improved device performances |
| US10211333B2 (en) * | 2017-04-26 | 2019-02-19 | Alpha And Omega Semiconductor (Cayman) Ltd. | Scalable SGT structure with improved FOM |
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| CN107799587A (en) * | 2017-10-20 | 2018-03-13 | 电子科技大学 | A kind of reverse blocking IGBT and its manufacture method |
| CN107799582A (en) * | 2017-10-20 | 2018-03-13 | 电子科技大学 | A kind of trench gate electric charge memory type insulated gate bipolar transistor and its manufacture method |
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