CN105489644A - IGBT device and fabrication method thereof - Google Patents
IGBT device and fabrication method thereof Download PDFInfo
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- CN105489644A CN105489644A CN201511023881.XA CN201511023881A CN105489644A CN 105489644 A CN105489644 A CN 105489644A CN 201511023881 A CN201511023881 A CN 201511023881A CN 105489644 A CN105489644 A CN 105489644A
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- 238000000034 method Methods 0.000 title claims abstract description 19
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 18
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- 239000000758 substrate Substances 0.000 claims abstract description 87
- 239000002184 metal Substances 0.000 claims abstract description 35
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 36
- 229920005591 polysilicon Polymers 0.000 claims description 36
- 125000006850 spacer group Chemical group 0.000 claims description 30
- 150000001875 compounds Chemical class 0.000 claims description 26
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 9
- 229910052710 silicon Inorganic materials 0.000 claims description 9
- 239000010703 silicon Substances 0.000 claims description 9
- 230000005684 electric field Effects 0.000 claims description 8
- 238000005516 engineering process Methods 0.000 claims description 7
- 230000003647 oxidation Effects 0.000 claims description 3
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- 238000010586 diagram Methods 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 238000001259 photo etching Methods 0.000 description 3
- 238000005728 strengthening Methods 0.000 description 3
- VMXJCRHCUWKQCB-UHFFFAOYSA-N NPNP Chemical compound NPNP VMXJCRHCUWKQCB-UHFFFAOYSA-N 0.000 description 2
- 238000009825 accumulation Methods 0.000 description 2
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- 230000002708 enhancing effect Effects 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
- H01L29/7398—Vertical transistors, e.g. vertical IGBT with both emitter and collector contacts in the same substrate side
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
- H01L29/66333—Vertical insulated gate bipolar transistors
- H01L29/66348—Vertical insulated gate bipolar transistors with a recessed gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
- H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
- H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
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Abstract
The invention provides an IGBT device and a fabrication method thereof. A composite gate structure is adopted by the IGBT device; the composite gate structure comprises a plane gate and a trench gate; the plane gate is formed on the front surface of a semiconductor substrate; the trench gate is formed in the front surface of the semiconductor substrate; and the trench gate can increase an effective length of a gate of the IGBT device, so that the target of achieving an electron injection enhancement effect can be achieved under the condition of reducing the length of the plane gate and reducing the cell dimension. Furthermore, according to the IGBT device, an auxiliary trench gate is added to a P well region, so that holes can be accumulated at the bottom part and the side walls of the auxiliary trench gate; and the electron injection enhancement effect at the lower part of the P well region is strengthened. Meanwhile, the auxiliary trench gate is electrically connected with an emitter metal electrode, so that the capacitance between an emitter and a collector of the IGBT device can be effectively improved; and the stability of the device is improved.
Description
Technical field
The present invention relates to power semiconductor field, particularly a kind of IGBT device and preparation method thereof.
Background technology
Insulated gate bipolar transistor (InsulatedGateBipolarTransistor, be called for short IGBT) be by double pole triode (BipolarJunctionTransistor, be called for short BJT) and insulating gate type field effect tube (Metal-Oxide-SemiconductorField-EffectTransistor, be called for short MOSFET) the compound full-control type voltage driven type power semiconductor that forms, have the advantage of the high input impedance of MOSFET element and low conduction voltage drop two aspect of BJT device concurrently.Because IGBT has the little and advantages such as saturation pressure reduction of driving power, be therefore widely applied to every field as a kind of novel power electronic device, such as, all have a wide range of applications at field IGBT such as Switching Power Supply, rectifier, inverter, UPS.
Saturation voltage Vce (sat) between collector electrode-emitter and turn-off power loss Eoff is the important parameter of IGBT device, and the former is in order to characterize the loss of IGBT in opening process, power consumption when the latter turns off in order to characterizing device.The conductivity modulation effect of IGBT causes high resistant N-type drift region to there is a large amount of charge carrier, pressure drop Vce (sat) when can reduce break-over of device.But device can cause tail currents long when turning off, and causes turn-off power loss Eoff very high.Both Vce (sat) and Eoff restrict mutually, and IGBT device development new technology makes two parameters reach optimum combination.
Inject enhanced grid transistor (IEGT) to develop on IGBT structure basis, achieved the low conducting voltage characteristic of IGBT device by the effect strengthening carrier injection.Compared with IGBT device, IEGT device has larger gate area, when big current conducting, the N-type drift region accumulation that a large amount of hole is directly square under the gate, for reaching charge balance, N-type drift region can inject more electronics to emitter region, this phenomenon is called electron injection enhancement effect (IE effect), therefore near emitter, form the Carrier Profile of high concentration, reduce the conducting resistance in this region, thus reach the object reducing device conduction voltage drop Vce (sat), and while electron injection significantly strengthens, the injection in the accumulation meeting hole, restriction set electrode side that hole is square under the gate, N-type drift region hole concentration does not increase, therefore the tail currents of IEGT device can not increase, turn-off power loss Eoff also can not obviously increase.
At present, IEGT device mainly contains planar gate and groove grid two kinds of structures.The narrow trench structure that the IEGT of slot grid structure adopts the emitter unit of wider groove structure or part unsettled usually, realizes the electron injection enhancement effect of emitter.Planar gate IEGT device architecture and planar gate IGBT close, difference is only that the former grid length is longer, and during break-over of device, the N-type drift region of hole directly below long gate is piled up, and causes the electron injection enhancement effect of emitter.The structure of traditional planar gate IEGT device as shown in Figure 1, comprises N-Semiconductor substrate 104, is formed at the P type collector region 102 at N-Semiconductor substrate 104 back side, N-type electric field cutoff layer 103 and collector electrode metal electrode 101, the P trap 105 being formed at N-Semiconductor substrate 104 front, P type contact zone 106, N-type emitter region 107, gate dielectric layer 108, polysilicon gate 109, spacer medium layer 110 and emitter metal electrode 112.
Inventor finds, although slot grid structure IEGT can improve device cellular density, eliminate JFET effect, reduce conduction voltage drop Vce (sat), but device capacitor can be caused to increase, especially collector electrode grid feedback capacity Crss is greater than the planar gate product of same size, cause device to turn off comparatively slow, increase turn-off power loss Eoff, therefore high-tension current IEGT device mainly adopts planar gate structure.But for strengthening the gathering of hole in cellular region, the polysilicon gate length of traditional planar gate IEGT device is very long, will certainly have influence on cellular density, causes device area larger.
Summary of the invention
The object of the present invention is to provide a kind of IGBT device and preparation method thereof, to solve existing technical problem.
For solving the problems of the technologies described above, the invention provides a kind of IGBT device, comprising:
N type semiconductor substrate;
Be formed at the P type collector region at the described Semiconductor substrate back side;
Be formed at the P trap in described Semiconductor substrate front;
Be formed at the N-type emitter region in described P trap;
Be formed at the compound grid structure in described Semiconductor substrate front;
It is characterized in that, described compound grid structure comprises the planar gate be formed on described Semiconductor substrate front and the trench gate be formed in described Semiconductor substrate front.
Optionally, in described IGBT device, described planar gate comprises planar polysilicon grid and the planar gate dielectric layer between planar polysilicon grid and Semiconductor substrate, and described trench gate comprises trench polysilicon silicon gate and the trench gate dielectric layer between trench polysilicon silicon gate and Semiconductor substrate.
Optionally, in described IGBT device, also comprise:
Be formed at the spacer medium layer on described Semiconductor substrate front and in described planar gate, described spacer medium layer has the through hole exposing described N-type emitter region part surface;
Be formed at the emitter metal electrode on described Semiconductor substrate front and on described spacer medium layer.
Optionally, in described IGBT device, also comprise:
Be formed at the secondary trenches grid that described P trap is electrically connected away from described trench gate side and with described emitter metal electrode.
Optionally, in described IGBT device, described secondary trenches grid comprise secondary trenches polysilicon gate and the secondary trenches gate dielectric layer between secondary trenches polysilicon gate and Semiconductor substrate.
Optionally, in described IGBT device, also comprise:
Be formed at the spacer medium layer of described secondary trenches grid end face, be formed with through hole in described spacer medium layer and be electrically connected with described emitter metal electrode to make described secondary trenches grid.
Optionally, in described IGBT device, also comprise:
Be formed at the N-type electric field cutoff layer between the described Semiconductor substrate back side and P type collector region.
Optionally, in described IGBT device, also comprise:
Be formed at the collector electrode metal electrode at the back side, described P type collector region.
Optionally, in described IGBT device, also comprise:
To be formed in described P trap and to be positioned at the P type contact zone of side, described N-type emitter region.
Optionally, in described IGBT device, described N type semiconductor substrate is N-type light dope, and described P type collector region is the heavy doping of P type, and described N-type emitter region is N-type heavy doping.
Present invention also offers a kind of IGBT device manufacture method, comprising:
One N type semiconductor substrate is provided;
Form P type collector region at the described Semiconductor substrate back side, in described Semiconductor substrate front, form P trap, in described P trap, form N-type emitter region, form compound grid structure in described Semiconductor substrate front; Wherein, described compound grid structure comprises the planar gate be formed on described Semiconductor substrate front and the trench gate be formed in described Semiconductor substrate front.
Optionally, in described IGBT device manufacture method, the step forming compound grid structure in described Semiconductor substrate front comprises:
In described Semiconductor substrate, form the first groove and the second groove, then formed the gate dielectric layer covering described Semiconductor substrate front and the first groove and the second flute surfaces by oxidation technology;
In described first groove and the second groove, fill polysilicon, described polysilicon covers the surface of described gate dielectric layer;
Etch described polysilicon and gate dielectric layer formation planar gate, trench gate and secondary trenches grid.
Optionally, in described IGBT device manufacture method, also comprise:
On described Semiconductor substrate front and in described planar gate, form spacer medium layer, described spacer medium layer has the through hole exposing described N-type emitter region part surface;
Emitter metal electrode is formed on described Semiconductor substrate front and on described spacer medium layer.
Optionally, in described IGBT device manufacture method, while described Semiconductor substrate front forms compound grid structure, form the secondary trenches grid be electrically connected with described emitter metal electrode away from described trench gate side at described P trap.
Optionally, in described IGBT device manufacture method, also comprise:
Form spacer medium layer at described secondary trenches grid end face, be formed with through hole in described spacer medium layer and be electrically connected with described emitter metal electrode to make described secondary trenches grid.
Optionally, in described IGBT device manufacture method, also comprise:
N-type electric field cutoff layer is formed between the described Semiconductor substrate back side and P type collector region.
Optionally, in described IGBT device manufacture method, also comprise:
Collector electrode metal electrode is formed at the back side, described P type collector region.
In IGBT device provided by the invention and preparation method thereof, adopt compound grid structure, described compound grid structure comprises the planar gate be formed on Semiconductor substrate front and the trench gate be formed in Semiconductor substrate front, described trench gate can increase the effective length of IGBT device grid, therefore in the length reducing planar gate, the object realizing electron injection enhancement effect can also can be reached when reducing cellular size.
In addition, IGBT device of the present invention increases secondary trenches grid at P well area, hole can be piled up in the bottom of secondary trenches grid and sidewall, strengthen electron injection enhancement effect below P well area.Meanwhile, because these secondary trenches grid are electrically connected with emitter metal electrode, can effectively improve electric capacity between the emitter of IGBT device and collector electrode, improve the stability of device.
Accompanying drawing explanation
Fig. 1 is the structural representation of traditional planar gate IEGT device;
Fig. 2 a is the schematic top plan view of the IGBT device of the embodiment of the present invention;
Fig. 2 b is the generalized section along AA ' direction in Fig. 2 a;
Fig. 2 c is the generalized section along BB ' direction in Fig. 2 a;
Fig. 3 ~ 5 are the device profile schematic diagrames in the IGBT device manufacturing process of the embodiment of the present invention;
Fig. 6 is the output characteristic curve comparison diagram of the compound grid-type IGBT of traditional IGBT and the present embodiment under equal area.
Embodiment
As stated in the Background Art, the IEGT of traditional planar gate structure is for realizing electron injection enhancement effect (IE effect), need longer polysilicon gate length, cause its cellular density lower, device area is larger, although and adopt slot grid structure can improve device cellular density, eliminate JFET effect, grid capacitance can be made to increase, affect switching speed and turn-off power loss.For this reason, compound grid structure is adopted in IGBT device of the present invention, described compound grid structure comprises the planar gate be formed on Semiconductor substrate front and the trench gate be formed in Semiconductor substrate front, described trench gate can increase the effective length of IGBT device grid, therefore in the length reducing planar gate, the object realizing electron injection enhancement effect can also can be reached when reducing cellular size.In addition, IGBT device of the present invention increases secondary trenches grid at P well area, hole can be piled up in the bottom of secondary trenches grid and sidewall, strengthen electron injection enhancement effect below P well area.Meanwhile, because these secondary trenches grid are electrically connected with emitter metal electrode, can effectively improve electric capacity between the emitter of IGBT device and collector electrode, improve the stability of device.
Below in conjunction with the drawings and specific embodiments, IGBT device that the present invention proposes and preparation method thereof is described in further detail.According to the following describes and claims, advantages and features of the invention will be clearer.It should be noted that, accompanying drawing all adopts the form that simplifies very much and all uses non-ratio accurately, only in order to object that is convenient, the aid illustration embodiment of the present invention lucidly.
Fig. 2 a is the schematic top plan view of the IGBT device of the embodiment of the present invention, and Fig. 2 b is the generalized section along AA ' direction in Fig. 2 a, and Fig. 2 c is the generalized section along BB ' direction in Fig. 2 a.As shown in Fig. 2 a ~ 2c, the IGBT device that the present embodiment proposes, comprise: N type semiconductor substrate 104, be formed at the P type collector region 102 at described Semiconductor substrate 104 back side, be formed at the P trap 105 in described Semiconductor substrate 104 front, be formed at the N-type emitter region 107 in described P trap 105, be formed at the compound grid structure in described Semiconductor substrate 104 front, wherein, described compound grid structure comprises the planar gate 1091 be formed on described Semiconductor substrate 104 front and the trench gate 1092 be formed in described Semiconductor substrate 104 front, both be conducive to strengthening electron injection enhancement effect, cell density can be reduced again.
In the present embodiment, described N type semiconductor substrate 104 is N-type light dope (N-), and described P type collector region 102 is P type heavy doping (P+), and described N-type emitter region 107 is N-type heavy doping (N+).Described N-type emitter region 107 and compound grid structure form the MOS part of IGBT device.Described Semiconductor substrate 104 is as N-type drift region, and described N-type emitter region 107, P trap 105, N-type drift region and P type collector region 102 constitute a parasitic NPNP thyristor.Described NPNP thyristor comprises NPN transistor (N-type emitter region 107, P trap 105, N-type drift region) and PNP transistor (P trap 105, N-type drift region, P type collector region 102).
Continue with reference to figure 2a ~ 2c, described IGBT device also comprises: be formed at the N-type electric field cutoff layer 103 between described Semiconductor substrate 104 back side and P type collector region 102, be formed at the collector electrode metal electrode 101 at the back side, described P type collector region 102, to be formed in described P trap 105 and to be positioned at the P type contact zone 106 of side, described N-type emitter region 107, be formed at the spacer medium layer 110 in described planar gate 1091, be formed at the emitter metal electrode 112 in described spacer medium layer 110 and Semiconductor substrate 104, described spacer medium layer 110 has and exposes the part surface of described N-type emitter region 107 and the through hole 110 ' of P type contact zone 106.The material of described spacer medium layer 110 is such as phosphorosilicate glass (PSG).For the details in clearer understanding figure, do not indicate in Fig. 2 a in emitter metal electrode 112, figure and be not isolated dielectric layer 110 overlay area and be through hole 110 '.
In preferred version, described IGBT device also comprises and is formed at described P trap 105 side and the secondary trenches grid 1093 be electrically connected with emitter metal electrode 112.By increasing the secondary trenches grid 1093 be electrically connected with emitter metal electrode 112, hole can be piled up in the bottom of secondary trenches grid 1093 and sidewall, strengthen electron injection enhancement effect below P trap.Meanwhile, because these secondary trenches grid 1093 are electrically connected with emitter metal electrode 112, effectively can improve the electric capacity between the emitter of IGBT device and collector electrode, improve the stability of device.When traditional IGBT device is short-circuited, due to the electron injection enhancement effect of IEGT, the a large amount of charge carriers accumulated below the area of grid of IGBT device under the effect of highfield to the grid oxic horizon of IGBT and channel region iunjected charge, the grid voltage of IGBT device is occurred unstable, thus cause component failure.And in IGBT device provided by the invention, because the P well area of cellular emitter region increases the secondary trenches grid 1093 be electrically connected with emitter, when device is short-circuited phenomenon, effectively can absorb the iunjected charge because electron injection enhancement effect causes, maintain the stability of grid voltage, the reliability of device is provided.
Wherein, described planar gate 1091 comprises planar polysilicon grid 1091a and the planar gate dielectric layer 1091b between planar polysilicon grid 1091a and Semiconductor substrate 104, described trench gate 1092 comprises trench polysilicon silicon gate 1092a and the trench gate dielectric layer 1092b between trench polysilicon silicon gate 1092a and Semiconductor substrate 104, and described secondary trenches grid 1093 comprise secondary trenches polysilicon gate 1093a and the secondary trenches gate dielectric layer 1093b between secondary trenches polysilicon gate 1093a and Semiconductor substrate 104.As a unrestriced example, the degree of depth of trench gate 1092 is 3 μm ~ 6 μm, and the width of trench gate 1092 is 0.6 μm ~ 1.5 μm, and trench gate 1092 is 5 μm ~ 25 μm with the spacing of secondary trenches grid 1093.Should be understood that, the present invention does not limit the spacing of the degree of depth of trench gate 1092, width and trench gate 1092 and secondary trenches grid 1093, can require that adaptability regulates the spacing of the degree of depth of the trench gate 1092 of described IGBT device and width and trench gate 1092 and secondary trenches grid 1093 according to device parameters setting.
As from the foregoing, in the IGBT device that the present embodiment proposes, trench gate 1092 and secondary trenches grid 1093 play the effect of electron injection enhancement effect simultaneously.Specifically, the hole that collector electrode produces can be piled up below planar gate 1091 and trench gate 1092, in order to reach charge balance, the electron injection enhancement effect (IE effect) of emitter can be caused, due to the longitudinal extension of trench gate 1092, the effective length of the grid of IGBT device can be improved, without the need to as traditional IEGT device increasing planar gate length, sacrifice device area for cost and realize the effect of electron injection enhancement.In addition, when the IGBT device conducting that the present embodiment proposes, the hole that collector electrode produces can be piled up in the bottom of the secondary trenches grid 1093 be electrically connected with emitter metal electrode 112 and sidewall, hole concentration near the secondary trenches grid that enhancing is electrically connected with emitter, thus increase the carrier concentration at edge, cellular emitter region.
Below in conjunction with the manufacture method introducing the IGBT device that the present invention proposes shown in Fig. 2 a ~ 2c and Fig. 3 ~ 5 in detail.
As shown in Figure 3, first, the Semiconductor substrate 104 of one N-type light dope (N-) is provided, described Semiconductor substrate 104 as N-type drift region, the zone melting and refining silicon substrate of described Semiconductor substrate 104 to be such as crystal orientation be <100>.Then, the active area (not shown in Fig. 3) of potential dividing ring terminal structure and device structure cell to be processed is formed in the front of described Semiconductor substrate 104, and the first groove 1092 ' and the second groove 1093 ' is formed by photoetching and etching technics in described active area, form gate dielectric layer 108 by oxidation technology again, described gate dielectric layer 108 covers the front of described Semiconductor substrate 104 and the surface of the first groove 1092 ' and the second groove 1093 '.
As shown in Figure 4, in described first groove 1092 ' and the second groove 1093 ', fill polysilicon 109, described polysilicon 109 covers the surface of described gate dielectric layer 108 simultaneously.
As shown in Figure 5, etch described polysilicon 109 and gate dielectric layer 108 forms planar gate 1091, trench gate 1092, secondary trenches grid 1093, described planar gate 1091 comprises planar polysilicon grid 1091a and the planar gate dielectric layer 1091b between planar polysilicon grid 1091a and Semiconductor substrate 104, described trench gate 1092 comprises trench polysilicon silicon gate 1092a and the trench gate dielectric layer 1092b between trench polysilicon silicon gate 1092a and Semiconductor substrate 104, described secondary trenches grid 1093 comprise secondary trenches polysilicon gate 1093a and the secondary trenches gate dielectric layer 1093b between secondary trenches polysilicon gate 1093a and Semiconductor substrate 104.
Then, with reference to figure 2a ~ 2c, in described Semiconductor substrate 104, form P trap 105, and form P type contact zone 106 and N-type emitter region 107 in P trap 105.Spacer medium layer 110 is formed again by depositing technics, described spacer medium layer 110 covers the surface of described compound grid structure and Semiconductor substrate 104, and in described spacer medium layer 110, forming through hole 110 ' by photoetching and etching technics, the bottom-exposed of described through hole 110 ' goes out described N-type emitter region 107, P type contact zone 106 and secondary trenches grid 1093.Next, form emitter metal electrode 112, described emitter metal electrode 112 is electrically connected with described N-type emitter region 107, P type contact zone 106 by described through hole 110 '.
In the present embodiment, when forming P trap 105 or P type contact zone 106, the end face of secondary trenches grid 1093 covers spacer medium layer 110, and in spacer medium layer 110, forms through hole 110 ' by photoetching and etching technics and be electrically connected with emitter metal electrode 112 to make secondary trenches grid 1093.
Continue with reference to figure 2a ~ 2c, next, to the thinning back side of the Semiconductor substrate 104 of front technique be completed to preset thickness, and inject N-type ion at described Semiconductor substrate 104 back side, to form N-type electric field cut-off region 103, again at the below implanting p-type ion of described N-type electric field cut-off region 103, form P type collector region 102, form collector electrode metal electrode 101 finally by sputtering or evaporation technology.
Fig. 6 is compound grid-type IGBT output characteristic curve comparison diagram when Vg=15V condition of traditional IGBT and the present embodiment under equal area.As shown in Figure 6, the IGBT of the present embodiment is in same set electrode voltage V (collector) situation, and output current I (collector) is comparatively large, and the saturation voltage Vce (sat) therefore between collector electrode-emitter is lower.
In sum, in the IGBT device that the present invention proposes, compound grid and secondary trenches grid all can play the effect of electron injection enhancement effect.The hole that collector electrode produces can be piled up in the below of the planar gate part of compound grid and trench gate, in order to reach charge balance, the electron injection enhancement effect (IE effect) of emitter can be caused, due to the longitudinal extension of trench gate, the effective length of the grid of IGBT device can be improved, without the need to as traditional IEGT device increasing planar gate length, sacrifice device area for cost and realize the effect of electron injection enhancement.And, when the compound grid-type IGBT device conducting that the present invention proposes, the hole that collector electrode produces can be piled up in the bottom of the secondary trenches grid be electrically connected with emitter metal electrode and sidewall, hole concentration near the auxiliary polycrystalline trench gate that enhancing is electrically connected with emitter metal electrode, thus increase the carrier concentration at edge, cellular emitter region.Meanwhile, because these secondary trenches grid are electrically connected with emitter metal electrode, can effectively improve electric capacity between the emitter of composite grid IGBT device and collector electrode, improve the stability of device.
Foregoing description is only the description to present pre-ferred embodiments, any restriction not to the scope of the invention, and any change that the those of ordinary skill in field of the present invention does according to above-mentioned disclosure, modification, all belong to the protection range of claims.
Claims (17)
1. an IGBT device, comprising:
N type semiconductor substrate;
Be formed at the P type collector region at the described Semiconductor substrate back side;
Be formed at the P trap in described Semiconductor substrate front;
Be formed at the N-type emitter region in described P trap;
Be formed at the compound grid structure in described Semiconductor substrate front;
It is characterized in that, described compound grid structure comprises the planar gate be formed on described Semiconductor substrate front and the trench gate be formed in described Semiconductor substrate front.
2. IGBT device as claimed in claim 1, it is characterized in that, described planar gate comprises planar polysilicon grid and the planar gate dielectric layer between planar polysilicon grid and Semiconductor substrate, and described trench gate comprises trench polysilicon silicon gate and the trench gate dielectric layer between trench polysilicon silicon gate and Semiconductor substrate.
3. IGBT device as claimed in claim 1, is characterized in that, also comprise:
Be formed at the spacer medium layer on described Semiconductor substrate front and in described planar gate, described spacer medium layer has the through hole exposing described N-type emitter region part surface;
Be formed at the emitter metal electrode on described Semiconductor substrate front and on described spacer medium layer.
4. IGBT device as claimed in claim 3, is characterized in that, also comprise:
Be formed at the secondary trenches grid that described P trap is electrically connected away from described trench gate side and with described emitter metal electrode.
5. IGBT device as claimed in claim 4, it is characterized in that, described secondary trenches grid comprise secondary trenches polysilicon gate and the secondary trenches gate dielectric layer between secondary trenches polysilicon gate and Semiconductor substrate.
6. IGBT device as claimed in claim 4, is characterized in that, also comprise:
Be formed at the spacer medium layer of described secondary trenches grid end face, be formed with through hole in described spacer medium layer and be electrically connected with described emitter metal electrode to make described secondary trenches grid.
7. as the IGBT device in claim 1 to 6 as described in any one, it is characterized in that, also comprise:
Be formed at the N-type electric field cutoff layer between the described Semiconductor substrate back side and P type collector region.
8. as the IGBT device in claim 1 to 6 as described in any one, it is characterized in that, also comprise:
Be formed at the collector electrode metal electrode at the back side, described P type collector region.
9. as the IGBT device in claim 1 to 6 as described in any one, it is characterized in that, also comprise:
To be formed in described P trap and to be positioned at the P type contact zone of side, described N-type emitter region.
10. as the IGBT device in claim 1 to 6 as described in any one, it is characterized in that, described N type semiconductor substrate is N-type light dope, and described P type collector region is the heavy doping of P type, and described N-type emitter region is N-type heavy doping.
11. 1 kinds of IGBT device manufacture methods, is characterized in that, comprising:
One N type semiconductor substrate is provided;
Form P type collector region at the described Semiconductor substrate back side, in described Semiconductor substrate front, form P trap, in described P trap, form N-type emitter region, form compound grid structure in described Semiconductor substrate front; Wherein, described compound grid structure comprises the planar gate be formed on described Semiconductor substrate front and the trench gate be formed in described Semiconductor substrate front.
12. IGBT device manufacture methods as claimed in claim 11, it is characterized in that, the step forming compound grid structure in described Semiconductor substrate front comprises:
In described Semiconductor substrate, form the first groove and the second groove, then formed the gate dielectric layer covering described Semiconductor substrate front and the first groove and the second flute surfaces by oxidation technology;
In described first groove and the second groove, fill polysilicon, described polysilicon covers the surface of described gate dielectric layer;
Etch described polysilicon and gate dielectric layer formation planar gate, trench gate and secondary trenches grid.
13. IGBT device manufacture methods as claimed in claim 11, is characterized in that, also comprise:
On described Semiconductor substrate front and in described planar gate, form spacer medium layer, described spacer medium layer has the through hole exposing described N-type emitter region part surface;
Emitter metal electrode is formed on described Semiconductor substrate front and on described spacer medium layer.
14. IGBT device manufacture methods as claimed in claim 11, it is characterized in that, while described Semiconductor substrate front forms compound grid structure, form the secondary trenches grid be electrically connected with described emitter metal electrode away from described trench gate side at described P trap.
15. IGBT device manufacture methods as claimed in claim 14, is characterized in that, also comprise:
Form spacer medium layer at described secondary trenches grid end face, be formed with through hole in described spacer medium layer and be electrically connected with described emitter metal electrode to make described secondary trenches grid.
16., as the IGBT device manufacture method in claim 11 to 15 as described in any one, is characterized in that, also comprise:
N-type electric field cutoff layer is formed between the described Semiconductor substrate back side and P type collector region.
17., as the IGBT device manufacture method in claim 11 to 15 as described in any one, is characterized in that, also comprise:
Collector electrode metal electrode is formed at the back side, described P type collector region.
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107706237A (en) * | 2017-10-31 | 2018-02-16 | 珠海格力电器股份有限公司 | Insulated-gate bipolar transistor device and preparation method thereof, power electronic equipment |
| CN108615707A (en) * | 2018-02-13 | 2018-10-02 | 株洲中车时代电气股份有限公司 | A kind of production method of the igbt chip with the compound grid structure of folded form |
| CN108682624A (en) * | 2018-02-13 | 2018-10-19 | 株洲中车时代电气股份有限公司 | A kind of igbt chip production method with composite grid |
| CN108767006A (en) * | 2018-05-31 | 2018-11-06 | 电子科技大学 | A kind of IGBT device of integrated voltage sample function |
| CN111106043A (en) * | 2019-12-23 | 2020-05-05 | 珠海格力电器股份有限公司 | Power semiconductor device cell structure, preparation method thereof and power semiconductor device |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2012108167A1 (en) * | 2011-02-11 | 2012-08-16 | Denso Corporation | Silicon carbide semiconductor device and method for manufacturing the same |
| CN102859698A (en) * | 2011-03-30 | 2013-01-02 | 住友电气工业株式会社 | Igbt |
| CN105047705A (en) * | 2015-06-30 | 2015-11-11 | 西安理工大学 | Electron injection enhanced high voltage IGBT and manufacturing method thereof |
| CN205231070U (en) * | 2015-12-30 | 2016-05-11 | 杭州士兰集成电路有限公司 | IGBT device |
-
2015
- 2015-12-30 CN CN201511023881.XA patent/CN105489644B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2012108167A1 (en) * | 2011-02-11 | 2012-08-16 | Denso Corporation | Silicon carbide semiconductor device and method for manufacturing the same |
| CN102859698A (en) * | 2011-03-30 | 2013-01-02 | 住友电气工业株式会社 | Igbt |
| CN105047705A (en) * | 2015-06-30 | 2015-11-11 | 西安理工大学 | Electron injection enhanced high voltage IGBT and manufacturing method thereof |
| CN205231070U (en) * | 2015-12-30 | 2016-05-11 | 杭州士兰集成电路有限公司 | IGBT device |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107706237A (en) * | 2017-10-31 | 2018-02-16 | 珠海格力电器股份有限公司 | Insulated-gate bipolar transistor device and preparation method thereof, power electronic equipment |
| CN107706237B (en) * | 2017-10-31 | 2024-03-29 | 珠海零边界集成电路有限公司 | Insulated gate bipolar transistor device, manufacturing method thereof and power electronic equipment |
| CN108615707A (en) * | 2018-02-13 | 2018-10-02 | 株洲中车时代电气股份有限公司 | A kind of production method of the igbt chip with the compound grid structure of folded form |
| CN108682624A (en) * | 2018-02-13 | 2018-10-19 | 株洲中车时代电气股份有限公司 | A kind of igbt chip production method with composite grid |
| CN108615707B (en) * | 2018-02-13 | 2020-08-28 | 株洲中车时代电气股份有限公司 | Manufacturing method of IGBT chip with folding type composite gate structure |
| CN108767006A (en) * | 2018-05-31 | 2018-11-06 | 电子科技大学 | A kind of IGBT device of integrated voltage sample function |
| CN108767006B (en) * | 2018-05-31 | 2020-09-15 | 电子科技大学 | IGBT device integrating voltage sampling function |
| CN111106043A (en) * | 2019-12-23 | 2020-05-05 | 珠海格力电器股份有限公司 | Power semiconductor device cell structure, preparation method thereof and power semiconductor device |
| CN111106043B (en) * | 2019-12-23 | 2022-08-19 | 珠海格力电器股份有限公司 | Power semiconductor device cell structure, preparation method thereof and power semiconductor device |
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