CN105047705A - Electron injection enhanced high voltage IGBT and manufacturing method thereof - Google Patents
Electron injection enhanced high voltage IGBT and manufacturing method thereof Download PDFInfo
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- CN105047705A CN105047705A CN201510375474.9A CN201510375474A CN105047705A CN 105047705 A CN105047705 A CN 105047705A CN 201510375474 A CN201510375474 A CN 201510375474A CN 105047705 A CN105047705 A CN 105047705A
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- 238000002347 injection Methods 0.000 title claims abstract description 20
- 239000007924 injection Substances 0.000 title claims abstract description 20
- 238000004519 manufacturing process Methods 0.000 title claims description 10
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 23
- 239000010703 silicon Substances 0.000 claims abstract description 23
- 239000000758 substrate Substances 0.000 claims abstract description 20
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 10
- 238000009825 accumulation Methods 0.000 claims description 46
- 239000002800 charge carrier Substances 0.000 claims description 24
- 238000000034 method Methods 0.000 claims description 16
- 238000000137 annealing Methods 0.000 claims description 15
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 12
- -1 phosphonium ion Chemical class 0.000 claims description 11
- 229920005591 polysilicon Polymers 0.000 claims description 9
- 229910004298 SiO 2 Inorganic materials 0.000 claims description 6
- 229910052796 boron Inorganic materials 0.000 claims description 6
- 238000005468 ion implantation Methods 0.000 claims description 5
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 4
- 238000001020 plasma etching Methods 0.000 claims description 4
- 238000000151 deposition Methods 0.000 claims description 3
- 238000005538 encapsulation Methods 0.000 claims description 3
- 230000003647 oxidation Effects 0.000 claims description 3
- 238000007254 oxidation reaction Methods 0.000 claims description 3
- 238000002360 preparation method Methods 0.000 claims description 3
- 230000000903 blocking effect Effects 0.000 abstract description 28
- 230000007423 decrease Effects 0.000 description 5
- 238000004088 simulation Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 230000001413 cellular effect Effects 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- 210000003127 knee Anatomy 0.000 description 1
- 238000005036 potential barrier Methods 0.000 description 1
- 230000006798 recombination Effects 0.000 description 1
- 238000005215 recombination Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 238000005211 surface analysis Methods 0.000 description 1
- 238000012795 verification Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
Abstract
The invention discloses an electron injection enhanced high voltage IGBT. Gate oxide layers are arranged in a trench in a middle part on an n- silicon substrate and flat surface parts at two sides, and a polycrystalline silicon layer is arranged on the gate oxide layers, which is called a trench-planar gate G; two sides of the trench-planar gate G are each provided with a p base region on the n- silicon substrate, the p base regions are isolated from the trench-planar gate G through the gate oxides, and in each p base region an upper surface of an n+ emitter region and the p base region are short-circuited to form an emitting electrode E; joints of the upper side of an n- drift region and bottoms of the p base regions at the two sides are provided with discrete n carrier storage layers; and an n field stop layer, a p+ collector region and a collector electrode C are arranged in sequence under the n- drift region. The high voltage IGBT structure provided by the invention remarkably improves saturation voltage when a device is turned on, blocking voltage is high, on-state loss is low, and latch current density is relatively high.
Description
Technical field
The invention belongs to power semiconductor device technical field, relate to a kind of high pressure IGBT of electron injection enhancement type, the invention still further relates to the high pressure IGBT manufacture method of this kind of electron injection enhancement type.
Background technology
High pressure IGBT needs one of key technical problem solved in development, is exactly saturation voltage when reducing on-state.In existing planar gate IGBT and trench gate IGBT structure, usually introduce charge carrier and store (CS) layer, to produce electron injection enhancement effect, thus increase the conductance modulation of conduction period, reach the object reducing saturation voltage.
But, for planar gate IGBT structure, though adopt CS layer to effectively reduce saturation voltage, and there is higher short-circuit capacity, be at high temperature still easy to breech lock occurs, cause the reliability decrease of device.For trench gate IGBT structure, although effectively can suppress latch-up, needing wide grid spacing, causing cellular density to reduce to obtain higher short-circuit capacity, current capacity declines; Simultaneously because groove is comparatively dark, cause process costs higher.
Summary of the invention
The object of the present invention is to provide a kind of high pressure IGBT of electron injection enhancement type, have employed groove-planar gate and charge carrier accumulation layer, can effectively reduce its saturation voltage, the application requirement of high voltage switch can be met well.
Another object of the present invention is also the high pressure IGBT manufacture method providing this kind of electron injection enhancement type, the structural design of device and the degree of freedom of making is increased, and has comparatively simple manufacture craft.
The technical solution used in the present invention is, a kind of high pressure IGBT of electron injection enhancement type, comprises as n
-the n of drift region
-silicon substrate, at n
-the middle part, top of silicon substrate has groove, the gate oxide having thickness identical with the planar section of both sides in groove, is provided with a T-shaped polysilicon layer, is called groove-planar gate G above gate oxide; At the n of groove-planar gate G both sides
-silicon substrate is respectively provided with a p base, and is isolated by gate oxide and groove-planar gate G, in each p base, be provided with a n
+emitter region, the n of every side
+the p base short circuit at emitter region upper surface and place forms an emitter E respectively; At n
-with bottom connection place, p base, both sides above drift region, be respectively arranged with discrete n charge carrier accumulation layer; At n
-be provided with n field stop layer below drift region, below n field stop layer, be provided with p+ collector region, the below of p+ collector region is provided with collector electrode C.
Another technical scheme that the present invention adopts is, a kind of high pressure IGBT manufacture method of above-mentioned electron injection enhancement type, and the method is carried out according to the following steps:
Step 1: at the treated <100>n type silicon substrate back side, first adopt phosphonium ion to inject, annealing is held concurrently and is advanced, and forms n field stop layer;
Step 2: on n field stop layer surface, then adopt boron ion implantation, annealing is held concurrently and is advanced, and forms p
+collector region;
Step 3: by thermal oxidation at n
-surface of silicon grows one deck SiO
2masking layer;
Step 4: along n
-middle part, silicon substrate upper end longitudinally sets the window of groove, utilizes reactive ion etching mode to etch shallow trench;
Step 5: erode SiO
2masking layer, another warm growth gate oxide, and depositing polysilicon, adopt method for planarizing surface, form the polysilicon layer of surfacing;
Step 6: etches polycrystalline Si-gate and gate oxide, forms grid G;
Step 7: adopt boron ion implantation, annealing is held concurrently and is advanced, and forms p base on surface;
Step 8: adopt high energy phosphonium ion to inject, annealing is held concurrently and is advanced, with n immediately below p base
-silicon substrate joint forms discrete n charge carrier accumulation layer;
Step 9: adopt phosphonium ion to inject, annealing is held concurrently and is advanced, and forms n at p base region surface
+emitter region;
Step 10: carry out electrode preparation, scribing, encapsulation.
The invention has the beneficial effects as follows, the high pressure IGBT of electron injection enhancement type of the present invention is hereinafter referred to as CS-TP-IGBT, have employed groove-planar gate and charge carrier accumulation layer, can effectively reduce its saturation voltage, the application requirement of high voltage switch can be met well.
Accompanying drawing explanation
Fig. 1 is the existing planar gate IGBT structure generalized section with charge carrier accumulation layer;
Fig. 2 is existing groove-planar gate IGBT structure generalized section;
Fig. 3 is the structural profile schematic diagram that the present invention injects enhancement mode high pressure IGBT (CS-TP-IGBT);
Fig. 4 is the schematic equivalent circuit of CS-TP-IGBT structure of the present invention;
Fig. 5 is that CS-TP-IGBT of the present invention compares with existing TP-IGBT with CS-IGBT forward blocking simulated behavior curve under identical structural parameters;
Fig. 6 is that CS-TP-IGBT of the present invention compares with existing TP-IGBT with CS-IGBT on state characteristic simulation curve under identical structural parameters;
Fig. 7 is that CS-TP-IGBT of the present invention compares with the turn-on characteristics simulation curve of existing TP-IGBT and CS-IGBT under same structure parameter and external circuit condition;
Fig. 8 is that CS-TP-IGBT of the present invention compares with the turn-off characteristic simulation curve of existing TP-IGBT and CS-IGBT under same structure parameter and external circuit condition;
Fig. 9 is that CS-TP-IGBT of the present invention compares with the I-V simulated behavior curve variation with temperature of existing TP-IGBT and CS-IGBT under same structure parameter;
Figure 10 is that CS-TP-IGBT blocking voltage of the present invention is with trench mesas width W
mchange curve;
Figure 11 is that CS-TP-IGBT blocking voltage of the present invention is with gash depth d
tchange curve;
Figure 12 is that CS-TP-IGBT blocking voltage of the present invention is with accumulation layer concentration N
cSchange curve;
Figure 13 is that CS-TP-IGBT blocking voltage of the present invention is with accumulation layer thickness W
cSchange curve;
Figure 14 is that CS-TP-IGBT on state characteristic of the present invention is with trench mesas width W
mchange curve;
Figure 15 is that CS-TP-IGBT on state characteristic of the present invention is with gash depth d
tchange curve;
Figure 16 is that CS-TP-IGBT on state characteristic of the present invention is with accumulation layer concentration N
cSchange curve;
Figure 17 is that CS-TP-IGBT on state characteristic of the present invention is with accumulation layer thickness W
cSchange curve.
Embodiment
Below in conjunction with the drawings and specific embodiments, the present invention is described in detail.
With reference to Fig. 1, the conducting channel of existing CS-IGBT structure is on surface, and its length is by p base and n
+the difference of the horizontal junction depth of emitter region diffusion determines.In addition, an a little higher than n of concentration is had in the below of p base
-the n charge carrier accumulation layer of drift region.
With reference to Fig. 2, the conducting channel of existing TP-IGBT structure, also on surface, is the n between two p bases
-be provided with a shallow trench above drift region, and gash depth is less than the degree of depth of p base, groove width is less than the spacing between p base, both sides.
With reference to Fig. 3, the high pressure IGBT structure of electron injection enhancement type of the present invention comprises as n
-the n of drift region
-silicon substrate, at n
-the middle part, top of silicon substrate has (shallow) groove, the gate oxide having thickness identical with the planar section of both sides in groove, is provided with a T-shaped polysilicon layer, is called groove-planar gate G above gate oxide; At the n of groove-planar gate G both sides
-silicon substrate is respectively provided with a p base, and is isolated by gate oxide and groove-planar gate G, in each p base, be provided with a n
+emitter region, the n of every side
+the p base short circuit at emitter region upper surface and place forms an emitter E respectively; At n
-with bottom connection place, p base, both sides above drift region, be respectively arranged with discrete n charge carrier accumulation layer (being called for short CS); At n
-be provided with n field stop layer below drift region, below n field stop layer, be provided with p+ collector region, the below of p+ collector region is provided with collector electrode C.
All there are three pn knots in Fig. 1-Fig. 3 from bottom to top, are called J
1, J
2, J
3knot.
Fig. 3 and Fig. 1, Fig. 2 are contrasted visible, in structure of the present invention, includes n charge carrier accumulation layer and groove-planar gate, on the basis of existing TP-IGBT structure, keep original groove-planar gate, p base, n
+emitter region, n
-n field stop layer, the p+ collector region structure of drift region and below thereof are constant, especially, at two p bases and n
-be provided with a n charge carrier accumulation layer be similar in CS-IGBT structure between drift region respectively, other regions all do not have significant change.
The state modulator scope of CS-TP-IGBT of the present invention is:
The shape of groove is rectangular channel, and bottom corners place is smooth, and gash depth is less than the junction depth (degree of depth) of p base, and groove width is less than the spacing of p base, both sides, and the surface of p base is 1 ~ 2 μm apart from trenched side-wall mesa width.
The concentration of n charge carrier accumulation layer is 1 × 10
15~ 5 × 10
15cm
-3time, the thickness of n charge carrier accumulation layer is 2 ~ 3 μm.
The operation principle of CS-TP-IGBT of the present invention is,
As shown in Figure 3, high pressure IGBT structure of the present invention, when adding forward voltage (U at CS-TP-IGBT two ends
cE>0) time, J
2tie reverse-biased, bear forward blocking voltage.Because the concentration of charge carrier accumulation layer is higher than n
-drift region, causes its blocking voltage to decline to some extent.Simultaneously owing to there is shallow trench, can by J
2the electric field that knot knee is concentrated transfers to the bottom of groove, makes up the impact of charge carrier accumulation layer on device blocking voltage;
When adding the positive grid voltage (U higher than threshold voltage in CS-TP-IGBT grid G
gE>U
t) time, raceway groove is formed on the surface of p base, and trenched side-wall can form electron accumulation district, n simultaneously
+emitter region can by raceway groove and accumulation area to n
-electronics is injected in drift region, causes J
1tie positively biased more, so collector region can to n
-drift region injected hole.Inject a part of hole can with by n
+the electron recombination come in emitter region, n can only be passed through in another part hole
+p base immediately below emitter region and flow into emitter.Owing to there is n charge carrier accumulation layer, make place between p base and n charge carrier accumulation layer define a hole barrier, this potential barrier can stop hole smoothly by p base, so this part hole just can n below shallow trench and accumulation layer
-accumulate in drift region.In order to ensure n
-the electric neutrality of drift region, n
+emitter region just can to n
-more electronics is injected in drift region.As compared to existing TP-IGBT with CS-IGBT, CS-TP-IGBT of the present invention, owing to there being the double action of shallow trench and accumulation layer, can making electron injection enhancement effect more violent, strengthen n thus
-the conductance modulation of drift region, causes overall device to have lower saturation voltage;
When adding minus gate voltage (U in CS-TP-IGBT grid G
gE<0), time, the shutoff of CS-TP-IGBT is then identical with TP-IGBT with CS-IGBT.First, the raceway groove of p base region surface disappears, and has cut off the source of electronics, then, and n
-the non equilibrium carrier of drift region will pass through the extraction of compound and the additional positive voltage of collection-emitter-base bandgap grading voluntarily and reduce gradually, until all non equilibrium carriers disappear completely, CS-TP-IGBT just thoroughly turns off.
Fig. 4 is the equivalent electric circuit of CS-TP-IGBT of the present invention, visible, and CS-TP-IGBT device of the present invention is equivalent to the parallel circuits of a pnp transistor controlled by MOSFET and pin diode.
Simplation verification
In order to evaluate the characteristic of CS-TP-IGBT of the present invention, for 6.5kV electric pressure, establishing structural model according to Fig. 3, utilizing ISE simulation software to CS-TP-IGBT forward blocking characteristic at ambient and elevated temperatures
,on state characteristic, switching characteristic and I-V characteristic emulate respectively, and with there is same structure parameter (namely as accumulation layer thickness W
cSwhen being 0, CS-TP-IGBT structure is identical with TP-IGBT structure; As gash depth d
twhen being 0, CS-TP-IGBT structure is then identical with CS-IGBT structure) existing TP-IGBT and CS-IGBT compare.
1) blocking characteristics
Fig. 5 gives CS-TP-IGBT of the present invention and compares with the forward blocking simulated behavior curve of existing TP-IGBT and CS-IGBT under same structure parameter.As seen from Figure 5, under normal temperature 300K, CS-TP-IGBT forward blocking characteristic curve of the present invention and existing TP-IGBT and CS-IGBT are closely, and the forward blocking voltage about 20V lower than TP-IGBT of CS-TP-IGBT, than CS-IGBT height about 50V.But under high temperature 420K, the high temperature blocking characteristics curve of CS-TP-IGBT of the present invention almost overlaps with TP-IGBT, and both high-temperature current leakages are slightly lower than existing CS-IGBT.
2) on state characteristic
Fig. 6 gives CS-TP-IGBT of the present invention and compares with the on state characteristic simulation curve of existing TP-IGBT and CS-IGBT under same structure parameter.As seen from Figure 6, when 300K, the on-state characteristic of CS-TP-IGBT of the present invention obviously goes with CS-IGBT than TP-IGBT.At 100A/cm
2current density under, CS-TP-IGBT saturation voltage than the low about 0.15V of TP-IGBT, than the low about 0.45V of CS-IGBT.And the zero temperature coefficient point of CS-TP-IGBT of the present invention is lower, corresponding current density is only 26A/cm
2, illustrate that CS-TP-IGBT high temperature on state characteristic is better.
3) switching characteristic
Fig. 7, Fig. 8 are respectively CS-TP-IGBT of the present invention and compare with the simulated behavior curve that turns on and off of existing TP-IGBT and CS-IGBT under same structure parameter and external circuit condition.Turn-on characteristics is as shown in Figure 7 visible, and opening with opening of existing TP-IGBT of CS-TP-IGBT of the present invention is very close, but all obviously fast than opening of existing CS-IGBT.Further, the impact by temperature is all very little.Turn-off characteristic is as shown in Figure 8 visible, and the shutoff curve of CS-TP-IGBT of the present invention almost overlaps with the shutoff curve of existing TP-IGBT, all slightly slow than CS-IGBT.Further, the tail currents under 420K high temperature reduces all to some extent.
4) I-V characteristic
Fig. 9 is the I-V simulated behavior curve variation with temperature comparison diagram of CS-TP-IGBT of the present invention and existing TP-IGBT and CS-IGBT under same structure parameter.As seen from Figure 9, when 300K the saturation current density of CS-TP-IGBT than TP-IGBT height about 30A/cm
2, than CS-IGBT height about 110A/cm
2; When 420K, the latch-up current density of CS-TP-IGBT is up to 1150A/cm
2, than the low about 30A/cm of TP-IGBT
2, than the height about 240A/cm of CS-IGBT
2.Illustrate that the anti-breech lock ability of CS-TP-IGBT is higher.
In order to take into account every characteristic of device, need key structural parameters, the concentration as gash depth, mesa width and accumulation layer strictly controls.Lower these key parameters of surface analysis are on the impact of device property of the present invention.
Figure 10, Figure 11 are the change curve of blocking voltage with groove parameter of CS-TP-IGBT of the present invention.As seen from Figure 10, with trench mesas width w
mincrease, blocking voltage first increases and then declines fast, and works as w
mwhen=1 μm, blocking voltage is the highest.As seen from Figure 11, with gash depth d
tincrease, blocking voltage first can increase and then decline fast, and works as d
twhen=3.5 μm, blocking voltage is the highest.Comparatively speaking, gash depth on the impact of blocking voltage than mesa width w
mimpact larger, the impact of groove width is then very little.So, need strictly to control gash depth.
Figure 12, Figure 13 are the change of blocking characteristics curve with accumulation layer parameter of CS-TP-IGBT of the present invention.As seen from Figure 12, W is worked as
cSwhen=2 μm, with accumulation layer concentration N
cSincrease, blocking voltage declines fast, and works as N
cS=1 × 10
16cm
-3time, blocking voltage declines very fast.As seen from Figure 13, N is worked as
cS=1 × 10
15cm
-3time, with accumulation layer thickness W
cSincrease, blocking voltage declines, and works as W
cSwhen=4 μm, blocking voltage declines more; Comparatively speaking, accumulation layer concentration N
cSon the impact of blocking voltage than accumulation layer width W
cSimpact larger.So, accumulation layer concentration N
cSneed strict control.
Figure 14, Figure 15 are the change of CS-TP-IGBT on state characteristic curve of the present invention with groove parameter.As seen from Figure 14, with trench mesas width W
mincrease, saturation voltage declines fast.As seen from Figure 15, with gash depth d
tincrease, saturation voltage also can decline.Comparatively speaking, trench mesas width w
mlarger on the impact of saturation voltage.
Figure 16, Figure 17 are the change of CS-TP-IGBT on state characteristic curve of the present invention with accumulation layer parameter.Figure 16 is visible, works as W
cSwhen=2 μm, with accumulation layer concentration N
cSincrease, saturation voltage declines fast, and works as N
cS=1 × 10
16cm
-3time, saturation voltage declines very fast.As seen from Figure 17, N is worked as
cS=1 × 10
15cm
-3time, with accumulation layer thickness W
cSincrease, saturation voltage decline less.Comparatively speaking, accumulation layer concentration N
cSon the impact of saturation voltage than accumulation layer width W
cSimpact larger.So, accumulation layer concentration N
cSneed strict control.
CS-TP-IGBT manufacture method of the present invention, specifically implement according to following steps:
Step 1: at the treated <100>n type silicon substrate back side, first adopt phosphonium ion (P
+) inject, annealing is held concurrently and is advanced, and forms n field stop layer;
Step 2: on n field stop layer surface, then adopt boron ion (B
+) inject, annealing is held concurrently and is advanced, and forms p
+collector region;
Step 3: by thermal oxidation at n
-surface of silicon grows one deck SiO
2masking layer;
Step 4: along n
-middle part, silicon substrate upper end longitudinally sets the window of groove, utilizes reactive ion etching mode (RIE) to etch shallow trench;
Step 5: erode SiO
2masking layer, another warm growth gate oxide, and depositing polysilicon, adopt method for planarizing surface, form the polysilicon layer of surfacing;
Step 6: etches polycrystalline Si-gate and gate oxide, forms grid G;
Step 7: adopt boron ion (B
+) inject, annealing is held concurrently and is advanced, and forms p base on surface;
Step 8: adopt high energy phosphonium ion (P
+) inject, annealing is held concurrently and is advanced, with n immediately below p base
-silicon substrate joint forms discrete n charge carrier accumulation layer; Or be called that n charge carrier stores (CS) layer
Step 9: adopt phosphonium ion (P
+) inject, annealing is held concurrently and is advanced, and forms n at p base region surface
+emitter region;
Step 10: to carry out after electrode preparation, scribing, encapsulation.
In sum, CS-TP-IGBT structure of the present invention, compared with existing TP-IGBT or CS-IGBT structure, can produce stronger electron injection enhancement effect, cause n during break-over of device
-the conductance modulation of drift region is strengthened, and effectively can reduce the saturation voltage of device, and obtains compromise preferably between blocking voltage, high temperature latch-up current and saturation current density.In addition, because gash depth is more shallow, accumulation layer thickness range is wider, and the degree of freedom of device layout and making is larger.When the technique of reality makes, CS-TP-IGBT only needs on the Process ba-sis of traditional planar gate IGBT, increase the etching technics of shallow trench and the ion implantation technology of accumulation layer, and cost is lower, is convenient to device and promotes.
Claims (6)
1. a high pressure IGBT for electron injection enhancement type, is characterized in that: comprise as n
-the n of drift region
-silicon substrate, at n
-the middle part, top of silicon substrate has groove, the gate oxide having thickness identical with the planar section of both sides in groove, is provided with a T-shaped polysilicon layer, is called groove-planar gate G above gate oxide; At the n of groove-planar gate G both sides
-silicon substrate is respectively provided with a p base, and is isolated by gate oxide and groove-planar gate G, in each p base, be provided with a n
+emitter region, the n of every side
+the p base short circuit at emitter region upper surface and place forms an emitter E respectively; At n
-with bottom connection place, p base, both sides above drift region, be respectively arranged with discrete n charge carrier accumulation layer; At n
-be provided with n field stop layer below drift region, below n field stop layer, be provided with p+ collector region, the below of p+ collector region is provided with collector electrode C.
2. according to the high pressure IGBT of electron injection enhancement type according to claim 1, it is characterized in that: the shape of described groove is rectangular channel, bottom corners place is smooth, gash depth is less than the degree of depth of p base, groove width is less than the spacing between p base, both sides, and the surface of p base is 1 ~ 2 μm apart from trenched side-wall mesa width.
3. according to the high pressure IGBT of electron injection enhancement type according to claim 1, it is characterized in that: the concentration of described n charge carrier accumulation layer is 1 × 10
15~ 5 × 10
15cm
-3time, the thickness of n charge carrier accumulation layer is 2 ~ 3 μm.
4. a high pressure IGBT manufacture method for electron injection enhancement type according to claim 1, is characterized in that, the method is carried out according to the following steps:
Step 1: at the treated <100>n type silicon substrate back side, first adopt phosphonium ion to inject, annealing is held concurrently and is advanced, and forms n field stop layer;
Step 2: on n field stop layer surface, then adopt boron ion implantation, annealing is held concurrently and is advanced, and forms p
+collector region;
Step 3: by thermal oxidation at n
-surface of silicon grows one deck SiO
2masking layer;
Step 4: along n
-middle part, silicon substrate upper end longitudinally sets the window of groove, utilizes reactive ion etching mode to etch shallow trench;
Step 5: erode SiO
2masking layer, another warm growth gate oxide, and depositing polysilicon, adopt method for planarizing surface, form the polysilicon layer of surfacing;
Step 6: etches polycrystalline Si-gate and gate oxide, forms grid G;
Step 7: adopt boron ion implantation, annealing is held concurrently and is advanced, and forms p base on surface;
Step 8: adopt high energy phosphonium ion to inject, annealing is held concurrently and is advanced, with n immediately below p base
-silicon substrate joint forms discrete n charge carrier accumulation layer;
Step 9: adopt phosphonium ion to inject, annealing is held concurrently and is advanced, and forms n at p base region surface
+emitter region;
Step 10: carry out electrode preparation, scribing, encapsulation.
5. according to the high pressure IGBT manufacture method of electron injection enhancement type according to claim 4, it is characterized in that, the shape of described groove is rectangular channel, bottom corners place is smooth, gash depth is less than the degree of depth of p base, groove width is less than the spacing between p base, both sides, and the surface of p base is 1 ~ 2 μm apart from trenched side-wall mesa width.
6. according to the high pressure IGBT manufacture method of electron injection enhancement type according to claim 4, it is characterized in that, the concentration of described n charge carrier accumulation layer is 1 × 10
15~ 5 × 10
15cm
-3time, the thickness of n charge carrier accumulation layer is 2 ~ 3 μm.
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