CN107342317B - Novel U-shaped groove IGBT and manufacturing method thereof - Google Patents

Novel U-shaped groove IGBT and manufacturing method thereof Download PDF

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Publication number
CN107342317B
CN107342317B CN201610280931.0A CN201610280931A CN107342317B CN 107342317 B CN107342317 B CN 107342317B CN 201610280931 A CN201610280931 A CN 201610280931A CN 107342317 B CN107342317 B CN 107342317B
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region
shaped groove
base region
semiconductor substrate
igbt
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CN107342317A (en
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刘国友
朱利恒
覃荣震
罗海辉
黄建伟
戴小平
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Zhuzhou CRRC Times Semiconductor Co Ltd
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Zhuzhou CRRC Times Electric Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395—Vertical transistors, e.g. vertical IGBT
    • H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
    • H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
    • H01L29/66333—Vertical insulated gate bipolar transistors
    • H01L29/66348—Vertical insulated gate bipolar transistors with a recessed gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395—Vertical transistors, e.g. vertical IGBT
    • H01L29/7398—Vertical transistors, e.g. vertical IGBT with both emitter and collector contacts in the same substrate side

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  • Condensed Matter Physics & Semiconductors (AREA)
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Abstract

The invention provides a novel U-shaped groove IGBT and a manufacturing method thereof, wherein the IGBT comprises: a semiconductor substrate and a cell region; the cell region comprises a first base region, a second base region, a first source region, a second source region and a U-shaped groove, wherein the first base region, the second base region and the U-shaped groove are located in the surface of a semiconductor substrate, the first source region is located in the first base region, the second source region is located in the second base region, the U-shaped groove is located between the first base region and the second base region, the bottom of the U-shaped groove is located in the semiconductor substrate, an oxidation layer covers the inner surface of the U-shaped groove, the coverage range of the oxidation layer extends to a part of the first source region and a part of the second source region from. The IGBT structure can introduce more carriers, and the structure only introduces a large amount of unbalanced carriers when in conduction, so that the breakdown voltage of the IGBT cannot be reduced, and the compromise relationship between the conduction current density and the breakdown voltage of the IGBT can be obviously improved.

Description

Novel U-shaped groove IGBT and manufacturing method thereof
Technical Field
The invention relates to the field of semiconductor devices, in particular to a novel U-shaped groove IGBT and a manufacturing method thereof.
Background
An Insulated Gate Bipolar Transistor (IGBT) is used as a Bipolar device controlled by an Insulated Gate, and the higher the concentration of non-equilibrium carriers in a body, the stronger the conductance modulation effect of the IGBT, and the higher the current density of the IGBT. Taking an N-type IGBT with an N-type substrate as an example, holes are injected by means of an anode emitter junction, and electrons are injected by means of a cathode channel. The electron injection capability on the cathode side is limited due to channel resistance. The JFET area between two P base areas of the ordinary IGBT cellular structure limits the expansion of an electron current path, and the JFET resistance generated by the JFET area can also reduce the concentration of cathode carriers and reduce the on-state current density of the IGBT. In order to enhance the electron injection capability of the IGBT cathode, the carrier concentration on one side of the cathode is enhanced by adding the N-type injection method in the JFET region, so that the conductivity modulation capability of the IGBT can be obviously enhanced, and the current density of the IGBT is improved.
However, the above prior art still has the disadvantages that the introduced JFET region is realized by implanting N-type impurities with high doping concentration, and the N-type impurities increase the electric field peak value near the region, and reduce the breakdown voltage of the IGBT cell. Therefore, the IGBT cellular structure can improve the on-current density and reduce the breakdown voltage.
Disclosure of Invention
The invention provides a novel U-shaped groove IGBT and a manufacturing method thereof, which are used for solving the technical problem that the breakdown voltage can be reduced while the current density of the IGBT is improved in the prior art.
One aspect of the present invention provides a novel U-shaped slot IGBT, including:
a semiconductor substrate and a cell region; the cell region comprises a first base region, a second base region, a first source region, a second source region and a U-shaped groove, wherein the first base region, the second base region and the U-shaped groove are located in the surface of a semiconductor substrate, the first source region is located in the first base region, the second source region is located in the second base region, the U-shaped groove is located between the first base region and the second base region, the bottom of the U-shaped groove is located in the semiconductor substrate, an oxidation layer covers the inner surface of the U-shaped groove, the coverage range of the oxidation layer extends to a part of the first source region and a part of the second source region from.
Further, the cell region further comprises a passivation layer and a first metal layer, wherein the passivation layer covers the polysilicon layer, a part of the first source region and a part of the second source region, and the first metal layer covers the passivation layer, a part of the first source region, a part of the second source region, a part of the first base region and a part of the second base region.
Furthermore, the semiconductor device further comprises an emitter region positioned on the back surface of the semiconductor substrate and a second metal layer covering the emitter region.
Furthermore, the junction depths of the first base region and the second base region are greater than the depth of the U-shaped groove.
Furthermore, the part of the U-shaped groove, which is positioned in the surface of the semiconductor substrate, is not contacted with the first base region and the second base region.
Further, the first source region, the second source region and the semiconductor substrate are doped regions of a first conductivity type, and the first base region, the second base region and the emitter region are doped regions of a second conductivity type, wherein the first conductivity type is different from the second conductivity type.
Further, the cellular region further comprises a first carrier storage region and a second carrier storage region which are positioned in the surface of the semiconductor substrate, wherein the first carrier storage region is arranged at the periphery of the first base region and separates the first base region from the semiconductor substrate, and the second carrier storage region is arranged at the periphery of the second base region and separates the second base region from the semiconductor substrate.
The invention provides a novel U-shaped groove IGBT manufacturing method on the other hand, which comprises the following steps:
step 101, forming a first base region and a second base region in the surface of a semiconductor substrate;
step 102, etching a U-shaped groove between a first base region and a second base region in the surface of a semiconductor substrate, wherein the bottom of the U-shaped groove is positioned in the semiconductor substrate,
103, sequentially growing an oxide layer and depositing a polycrystalline silicon layer on the surface of the semiconductor substrate and in the U-shaped groove;
104, etching the oxide layer and the polycrystalline silicon layer, wherein the etched oxide layer covers the U-shaped groove, part of the first base region and part of the second base region, and the polycrystalline silicon layer covers the oxide layer and fills the U-shaped groove;
and 105, performing first source region injection on the first base region, and performing second source region injection on the second base region, wherein the first source region and the second source region are both in contact with the oxide layer.
Further, after step 105, the method further includes:
106, depositing a passivation layer on the front surface of the semiconductor substrate, and etching the passivation layer, wherein the etched passivation layer covers the polycrystalline silicon layer, a part of the first source region and a part of the second source region;
and 107, depositing a first metal layer on the front surface of the semiconductor substrate, so that the first metal layer covers the passivation layer, part of the first source region, part of the second source region, part of the first base region and part of the second base region.
Further, after step 107, the method further includes:
and 108, sequentially forming an emitting region and a second metal layer on the back surface of the semiconductor substrate, wherein the second metal layer covers the emitting region.
The novel U-shaped groove IGBT and the manufacturing method thereof provided by the invention have the advantages that the grid oxide layer and the polycrystalline silicon electrode of the IGBT structure are of a U-shaped structure, the grid oxide layer and the polycrystalline silicon are deeply inserted into the JEFT area, accumulated layer carriers can be formed on the lower surface (a contact area between the grid oxide layer and the surface of a semiconductor substrate) of the U-shaped grid oxide layer when the IGBT is conducted, and the concentration of the accumulated layer carriers is closely related to the grid voltage. The higher the gate voltage, the higher the carrier concentration of the accumulation layer, and when the gate voltage is zero, the accumulation layer disappears. Compared with the common IGBT, the gate electrode of the IGBT is longer, so that more carriers can be introduced, the effect of enhancing the concentration of the nonequilibrium carriers on the cathode side is better, in addition, a large number of nonequilibrium carriers are introduced only when the structure is switched on, and the accumulation layer disappears when the IGBT is switched off, so the breakdown voltage of the IGBT cannot be reduced, and the compromise relation between the conduction current density and the breakdown voltage of the IGBT can be obviously improved.
Drawings
The invention will be described in more detail hereinafter on the basis of embodiments and with reference to the accompanying drawings. Wherein:
fig. 1 is a schematic structural diagram of a novel U-shaped groove IGBT according to a first embodiment of the present invention;
fig. 2 is a schematic structural diagram of a novel U-shaped groove IGBT according to a second embodiment of the present invention;
fig. 3 is another schematic structural diagram of the novel U-shaped groove IGBT according to the second embodiment of the present invention;
fig. 4 is a schematic flow chart of a manufacturing method of the novel U-shaped groove IGBT according to the third embodiment of the present invention;
fig. 5 is a schematic view of a first structure obtained by the novel U-shaped groove IGBT manufacturing method according to the third embodiment of the present invention;
fig. 6 is a schematic view of a second structure obtained by the manufacturing method of the novel U-shaped groove IGBT according to the third embodiment of the present invention;
fig. 7 is a schematic diagram of a third structure obtained by the novel U-shaped groove IGBT manufacturing method according to the third embodiment of the present invention;
fig. 8 is a schematic view of a fourth structure obtained by the manufacturing method of the novel U-shaped groove IGBT according to the third embodiment of the present invention;
fig. 9 is a schematic flow chart of a manufacturing method of the novel U-shaped groove IGBT according to the fourth embodiment of the present invention;
fig. 10 is a schematic view of a first structure obtained by the novel U-shaped groove IGBT manufacturing method according to the fourth embodiment of the present invention;
fig. 11 is a schematic view of a second structure obtained by the manufacturing method of the novel U-shaped groove IGBT according to the fourth embodiment of the present invention.
In the drawings, like parts are provided with like reference numerals. The figures are not drawn to scale.
Detailed Description
The invention will be further explained with reference to the drawings.
Example one
Fig. 1 is a schematic structural diagram of a novel U-shaped groove IGBT according to a first embodiment of the present invention; as shown in fig. 1, the present embodiment provides a novel U-shaped slot IGBT, including:
a semiconductor substrate 1 and a cell region 2; the cell region 2 comprises a first base region 21, a second base region 22, a first active region 23 located in the first base region 21, a second active region 24 located in the second base region 22, and a U-shaped groove 25 located between the first base region 21 and the second base region 22, wherein the bottom of the U-shaped groove 25 is located in the semiconductor substrate 1, an oxide layer 251 covers the inner surface of the U-shaped groove 25, the coverage range of the oxide layer 251 extends from the inner surface of the U-shaped groove 25 to a part of the first active region 23 and a part of the second active region 24, a polysilicon layer 252 covers the oxide layer 251, and the U-shaped groove 25 is filled with the polysilicon layer 252.
Specifically, "in the semiconductor substrate surface" in the present specification means a region of a certain depth extending downward from the surface of the front surface of the semiconductor substrate 1, the region belonging to a part of the semiconductor substrate 1.
The semiconductor substrate 1 may include a semiconductor element such as silicon or silicon germanium with a single crystal, polycrystalline or amorphous structure, or a mixed semiconductor structure such as silicon carbide, an alloy semiconductor, or a combination thereof, which is not limited herein. The semiconductor substrate 1 in the present embodiment is preferably a silicon substrate, and an N-type or P-type silicon substrate may be used.
A plurality of cell regions are provided, each cell region includes a first base region 21, a second base region 22, a first active region 23 located in the first base region 21, a second active region 24 located in the second base region 22, and a U-shaped groove 25 located between the first base region 21 and the second base region 22, the bottom of the U-shaped groove 25 is located in the semiconductor substrate 1, the top of the U-shaped groove 25 is flush with the upper surface of the front surface of the semiconductor substrate 1, the inner surface of the U-shaped groove 25 is covered with an oxide layer 251 to form a gate oxide layer 251, the oxide layer 251 may be specifically silicon dioxide or silicon oxynitride, the coverage range of the oxide layer 251 extends from the inner surface of the U-shaped groove 25 to the first active region 23 and the second active region 24, but does not completely cover the first active region 23 and the second active region 24, to cover a part of the first active region 23 and a part of the second active region 24 close to the U-shaped groove 25, the oxide layer 251 is, to form a polysilicon electrode. In the novel U-shaped trench IGBT provided in this embodiment, the gate oxide layer and the polysilicon electrode are U-shaped structures, the oxide layer 251 and the polysilicon layer 252 are deep into the JEFT region, and when the IGBT is turned on, an accumulation layer carrier is formed on the lower surface of the U-shaped gate oxide layer 251 (the contact region between the oxide layer 251 and the surface of the semiconductor substrate 1), and the concentration of the accumulation layer carrier is closely related to the gate voltage. The higher the gate voltage, the higher the carrier concentration of the accumulation layer, and when the gate voltage is zero, the accumulation layer disappears. Compared with the common IGBT, the gate electrode of the IGBT is longer, so that more carriers can be introduced, the effect of enhancing the carrier concentration of the cathode side is better, in addition, a large amount of non-equilibrium carriers are introduced only when the structure is switched on, and the accumulation layer disappears when the IGBT is switched off, so the breakdown voltage of the IGBT cannot be reduced, and the compromise relation between the conduction current density and the breakdown voltage of the IGBT can be obviously improved.
Example two
This embodiment is a supplementary explanation based on the above embodiment.
Fig. 2 is a schematic structural diagram of a novel U-shaped groove IGBT according to a second embodiment of the present invention; as shown in fig. 2, the cell region further includes a passivation layer 26 and a first metal layer 27, wherein the passivation layer 26 covers the polysilicon layer 252, a portion of the first source region 23 and a portion of the second source region 24, and the first metal layer 27 covers the passivation layer 26, a portion of the first source region 23, a portion of the second source region 24, a portion of the first base region 21 and a portion of the second base region 22.
Specifically, the passivation layer 26 is used to separate the first metal layer 27 from the oxide layer 251 and the polysilicon layer 252 (the gate oxide layer 251 and the polysilicon electrode), and the first metal layer 27 is preferably an aluminum layer.
Further, the IGBT further includes an emitter region 3 on the back surface of the semiconductor substrate 1 and a second metal layer 4 covering the emitter region 3.
Further, the junction depths of the first base region 21 and the second base region 22 are both greater than the depth of the U-shaped groove 25.
Specifically, the first base region 21 and the second base region 22 on both sides of the U-shaped groove 25 can reduce the peak electric field at the bottom of the U-shaped groove 25, and improve the voltage endurance capability of the U-shaped groove 25. In order to ensure that the first base region 21 and the second base region 22 have a good protection effect on the U-shaped groove 25, the depths of the first base region 21 and the second base region 22 in the semiconductor substrate 1 need to be greater than the depth of the U-shaped groove 25 in the semiconductor substrate 1.
Further, the portion of the U-shaped groove 25 located in the semiconductor substrate 1 is not in contact with the first base region 21 and the second base region 22.
Specifically, the introduction of the U-shaped groove 25 may cause a JFET region between the first base region 21 and the second base region 22 to be reduced, which may weaken the electron injection capability of the IGBT cathode, and to avoid this, it should be ensured that a portion of the U-shaped groove 25 located in the semiconductor substrate 1 is not in contact with the first base region 21 and the second base region 22, that is, the maximum width of the U-shaped groove 25 should be smaller than the distance between the first base region 21 and the second base region 22, so as to leave a certain space for the JFET region.
Further, the first source region 23, the second source region 24 and the semiconductor substrate 1 are doped regions of a first conductivity type, and the first base region 21, the second base region 22 and the emitter region 3 are doped regions of a second conductivity type, wherein the first conductivity type is different from the second conductivity type.
Specifically, the first conductivity type and the second conductivity type may be both N-type or P-type, and only the first conductivity type and the second conductivity type need to be different.
Preferably, the first source region 23 and the second source region 24 are heavily doped regions of the first conductivity type, and the emitter region 3 is a heavily doped region of the second conductivity type.
Further, as shown in fig. 3, the cell region further includes a first carrier storage region 28 and a second carrier storage region 29 in the semiconductor substrate 1, wherein the first carrier storage region 28 is disposed on the periphery of the first base region 21 to separate the first base region 21 from the semiconductor substrate 1, and the second carrier storage region 29 is disposed on the periphery of the second base region 22 to separate the second base region 22 from the semiconductor substrate 1.
Specifically, the first carrier storage region 28 and the second carrier storage region 29 are both heavily doped regions of the first conductivity type, and this method of increasing the injection of the first conductivity type at the peripheries of the first base region 21 and the second base region 22 enhances the carrier concentration at the cathode side, so that the conductance modulation capability of the IGBT can be obviously enhanced, and the current density of the IGBT is improved.
EXAMPLE III
The manufacturing method of the novel U-shaped groove IGBT provided by this embodiment can be used to manufacture the novel U-shaped groove IGBT in the first embodiment.
Fig. 4 is a schematic flow chart of a manufacturing method of the novel U-shaped groove IGBT according to the third embodiment of the present invention; as shown in fig. 4, the present embodiment provides a method for manufacturing a novel U-shaped slot IGBT, including:
step 101, forming a first base region and a second base region in the surface of a semiconductor substrate.
The structure formed in this step is shown in fig. 5, where reference numeral 400 is a semiconductor substrate, 401 is a first base region, and 402 is a second base region.
And 102, etching a U-shaped groove between the first base region and the second base region in the surface of the semiconductor substrate, wherein the bottom of the U-shaped groove is positioned in the semiconductor substrate.
Specifically, a U-shaped groove is formed in the surface of the semiconductor substrate by adopting plasma dry etching, and the U-shaped groove is vertical to the substrate.
Dry etching is a technique of performing thin film etching using plasma. When the gas is present in the form of a plasma, it has two characteristics: on one hand, the chemical activity of the gases in the plasma is much stronger than that of the gases in a normal state, and the gases can react with the materials more quickly by selecting proper gases according to the difference of the etched materials, so that the aim of etching removal is fulfilled; on the other hand, the electric field can be used for guiding and accelerating the plasma, so that the plasma has certain energy, and when the plasma bombards the surface of the etched object, atoms of the etched object material can be knocked out, thereby achieving the purpose of etching by utilizing physical energy transfer. Thus, dry etching is a result of a balance of both physical and chemical processes on the wafer surface. And a U-shaped groove is formed in the surface of the semiconductor substrate by adopting plasma dry etching, so that the realization is convenient and the effect is excellent.
The structure formed in this step is shown in fig. 6, and reference numeral 403 is a U-shaped groove.
And 103, growing an oxide layer and depositing a polycrystalline silicon layer on the surface of the semiconductor substrate and in the U-shaped groove in sequence.
Specifically, the oxide layer plays a role in isolation, and the oxide layer may be specifically silicon dioxide or silicon oxynitride. And depositing a polysilicon layer on the oxide layer and completely filling the trench to form a gate electrode.
And 104, etching the oxide layer and the polycrystalline silicon layer, wherein the etched oxide layer covers the U-shaped groove, part of the first base region and part of the second base region, and the polycrystalline silicon layer covers the oxide layer and fills the U-shaped groove.
Specifically, the oxide layer and the polysilicon layer are etched, a part of the oxide layer and the polysilicon layer which cover the surface of the semiconductor substrate are etched, the etched oxide layer covers the U-shaped groove, a part of the first base region and a part of the second base region, the coverage range of the polysilicon layer is consistent with that of the oxide layer, and the U-shaped groove is filled with the polysilicon layer.
The structure formed in this step is shown in fig. 7, where reference numeral 404 is an oxide layer and 405 is a polysilicon layer.
And 105, performing first source region injection on the first base region, and performing second source region injection on the second base region, wherein the first source region and the second source region are both in contact with the oxide layer.
Further, the first source region, the second source region and the semiconductor substrate are doped regions of a first conductivity type, and the first base region, the second base region and the emitter region are doped regions of a second conductivity type, wherein the first conductivity type is different from the second conductivity type. The first conductivity type and the second conductivity type can be both N-type or P-type.
The structure formed in this step is shown in fig. 8, where reference numeral 406 is a first base region, and 407 is a second base region.
In the manufacturing method of the novel U-shaped groove IGBT of this embodiment, the U-shaped groove is disposed between the first base region and the second base region, so that the oxide layer and the polysilicon layer are deep into the JEFT region, and when the IGBT is turned on, an accumulation layer carrier is formed on the lower surface of the U-shaped gate oxide layer (the contact region between the oxide layer and the surface of the semiconductor substrate), and the concentration of the accumulation layer carrier is closely related to the gate voltage. The higher the gate voltage, the higher the carrier concentration of the accumulation layer, and when the gate voltage is zero, the accumulation layer disappears. Compared with the common IGBT, the gate electrode of the IGBT is longer, so that more carriers can be introduced, the effect of enhancing the carrier concentration of the cathode side is better, in addition, a large amount of non-equilibrium carriers are introduced only when the structure is switched on, and the accumulation layer disappears when the IGBT is switched off, so the breakdown voltage of the IGBT cannot be reduced, and the compromise relation between the conduction current density and the breakdown voltage of the IGBT can be obviously improved.
Example four
This embodiment is a supplementary explanation based on the third embodiment.
Fig. 9 is a schematic flow chart of a manufacturing method of the novel U-shaped groove IGBT according to the fourth embodiment of the present invention; as shown in fig. 9, the third embodiment of the present invention further includes:
and 106, depositing a passivation layer on the front surface of the semiconductor substrate, and etching the passivation layer, wherein the etched passivation layer covers the polycrystalline silicon layer, part of the first source region and part of the second source region.
The structure formed in this step is shown in fig. 10, and reference numeral 408 is a passivation layer.
And 107, depositing a first metal layer on the front surface of the semiconductor substrate, so that the first metal layer covers the passivation layer, part of the first source region, part of the second source region, part of the first base region and part of the second base region.
The structure formed in this step is shown in fig. 11, and reference numeral 409 denotes a first metal layer.
And 108, sequentially forming an emitting region and a second metal layer on the back surface of the semiconductor substrate, wherein the second metal layer covers the emitting region.
While the invention has been described with reference to a preferred embodiment, various modifications may be made and equivalents may be substituted for elements thereof without departing from the scope of the invention. In particular, the technical features mentioned in the embodiments can be combined in any way as long as there is no structural conflict. It is intended that the invention not be limited to the particular embodiments disclosed, but that the invention will include all embodiments falling within the scope of the appended claims.

Claims (6)

1. The utility model provides a novel U type groove IGBT which characterized in that includes:
a semiconductor substrate and a cell region; the cell region comprises a first base region, a second base region, a first source region, a second source region and a U-shaped groove, wherein the first base region, the second base region, the first source region, the second source region and the U-shaped groove are positioned in the surface of a semiconductor substrate, the first source region, the second source region and the U-shaped groove are positioned in the second base region, the bottom of the U-shaped groove is positioned in the semiconductor substrate, the inner surface of the U-shaped groove is covered with an oxidation layer, the coverage range of the oxidation layer extends to a part of the first source region and a part of the second source region from the inner surface of the U-,
the cell region further comprises a first carrier storage region and a second carrier storage region which are positioned in the surface of the semiconductor substrate, wherein the first carrier storage region is arranged at the periphery of the first base region to separate the first base region from the semiconductor substrate, the part of the first carrier storage region, with the same depth as the part of the U-shaped groove in the surface of the semiconductor substrate, is configured not to be in contact with the part of the U-shaped groove in the surface of the semiconductor substrate, the second carrier storage region is arranged at the periphery of the second base region to separate the second base region from the semiconductor substrate, and the part of the second carrier storage region, with the same depth as the part of the U-shaped groove in the surface of the semiconductor substrate, is configured not to be in contact with the part of the U-shaped groove in the surface of the semiconductor substrate.
2. The novel U-shaped slot IGBT according to claim 1, wherein the cell region further comprises a passivation layer and a first metal layer, wherein the passivation layer covers the polysilicon layer, a part of the first source region and a part of the second source region, and the first metal layer covers the passivation layer, a part of the first source region, a part of the second source region, a part of the first base region and a part of the second base region.
3. The novel U-slot IGBT of claim 2 further comprising an emitter region on the back side of the semiconductor substrate and a second metal layer covering the emitter region.
4. The novel U-shaped groove IGBT according to claim 1, characterized in that the junction depth of the first base region and the second base region is larger than the depth of the U-shaped groove.
5. The novel U-shaped groove IGBT according to claim 1, characterized in that the part of the U-shaped groove in the surface of the semiconductor substrate is not in contact with the first base region and the second base region.
6. The novel U-type slot IGBT as claimed in claim 3, wherein the first source region, the second source region and the semiconductor substrate are doped regions of a first conductivity type, and the first base region, the second base region and the emitter region are doped regions of a second conductivity type, wherein the first conductivity type is different from the second conductivity type.
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CN105047705A (en) * 2015-06-30 2015-11-11 西安理工大学 Electron injection enhanced high voltage IGBT and manufacturing method thereof

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JP2007311574A (en) * 2006-05-18 2007-11-29 Nec Electronics Corp Semiconductor device, and manufacturing method thereof
CN103839988A (en) * 2012-11-23 2014-06-04 中国科学院微电子研究所 Structure of EMPT-TI-IGBT device and manufacturing method thereof

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CN105047705A (en) * 2015-06-30 2015-11-11 西安理工大学 Electron injection enhanced high voltage IGBT and manufacturing method thereof

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