CN109713030B - RC-IGBT device - Google Patents
RC-IGBT device Download PDFInfo
- Publication number
- CN109713030B CN109713030B CN201811587937.8A CN201811587937A CN109713030B CN 109713030 B CN109713030 B CN 109713030B CN 201811587937 A CN201811587937 A CN 201811587937A CN 109713030 B CN109713030 B CN 109713030B
- Authority
- CN
- China
- Prior art keywords
- region
- collector
- cut
- layer
- collector region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 239000002184 metal Substances 0.000 claims description 6
- 239000004065 semiconductor Substances 0.000 claims description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 3
- 230000000903 blocking effect Effects 0.000 claims 1
- 238000000034 method Methods 0.000 description 5
- 230000002441 reversible effect Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000002411 adverse Effects 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 230000000750 progressive effect Effects 0.000 description 1
Images
Landscapes
- Thin Film Transistor (AREA)
Abstract
The invention discloses an RC-IGBT device. A first grid oxide layer is arranged between the dielectric layer and the grid layer of the RC-IGBT device; a second grid oxide layer is arranged between the grid layer and the P well region; p-type heavily doped regions are arranged on two sides of the P well region; a current carrier storage layer is arranged at the bottom of the P well region; the carrier storage layer is arranged in the drift region; a collector electrode, a collector region and a cut-off region are sequentially arranged at the bottom of the drift region from bottom to top; the first cut-off region is arranged at the upper part of the first collector region, the second cut-off region is arranged at the upper part of the second collector region, and the first cut-off region and the second cut-off region are isolated by the vertical end of the first collector region; the first collector region is in contact with the second collector region. The RC-IGBT device provided by the invention can effectively inhibit the negative resistance phenomenon.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to an RC-IGBT device.
Background
In green industries or products such as new energy, high-speed rails, electric vehicles and smart grids, Insulated Gate Bipolar Transistors (IGBTs) are indispensable core power devices. With the popularization of low-carbon and energy-saving concepts in the global scope, the IGBT will become a mainstream product in the power device market. Since birth, the IGBT is developed toward high power, high reliability, low power consumption and low cost, and in recent years, the rapid development of the sheet process technology and the advanced chip design technology makes the key performances of the IGBT, such as on-voltage drop, turn-off loss, and short-circuit safe operating region, reach unprecedented excellent levels. In order to expand the development space of the IGBT, people begin to try to integrate the IGBT with a freewheeling diode, and research and develop a reverse conducting IGBT (RC-IGBT) device. Because the IGBT does not have reverse conduction capability, in most IGBT application circuits, the reverse parallel freewheeling diode is protected, the IGBT and the diode are manufactured respectively in the early stage and then are integrated and packaged together to form the IGBT and the diode pair, and in order to reduce the cost and improve the power density of a chip, people begin to integrate the IGBT and the diode through a process to develop the IGBT-IGBT device.
When the traditional RC-IGBT device structure is switched from single-carrier to double-carrier operation, negative resistance phenomenon is caused due to conductance modulation phenomenon, and the negative resistance phenomenon can bring adverse effect on the operation and stability of the device when the device is operated at low temperature, so that the reliability and performance of the device are damaged.
Disclosure of Invention
The invention aims to provide an RC-IGBT device to solve the problem that a negative resistance phenomenon is easy to occur in a traditional RC-IGBT device.
In order to achieve the purpose, the invention provides the following scheme:
an RC-IGBT device comprising: the semiconductor device comprises a dielectric layer, a gate oxide layer, a P well region, a current carrier storage layer, a P type heavily doped region, a drift region, a cut-off region, a collector region and a collector electrode, wherein the gate oxide layer, the P well region, the current carrier storage layer, the P type heavily doped region, the drift region, the cut-off region, the collector region and the collector electrode are arranged on two sides of the gate layer;
a first grid oxide layer is arranged between the dielectric layer and the grid layer; a second grid oxide layer is arranged between the grid layer and the P well region; the two sides of the P well region are provided with the P type heavily doped regions; a current carrier storage layer is arranged at the bottom of the P well region; the carrier storage layer is arranged in the drift region; a collector electrode, a collector region and a cut-off region are sequentially arranged at the bottom of the drift region from bottom to top;
the collector region comprises a first collector region and a second collector region; the cut-off region comprises a first cut-off region and a second cut-off region;
the first cut-off region is arranged at the upper part of the first collector region, the second cut-off region is arranged at the upper part of the second collector region, and the first cut-off region and the second cut-off region are isolated by the vertical end of the first collector region; the first collector region is in contact with the second collector region.
Optionally, the method further includes: metal connecting wires;
the metal connecting wire sequentially penetrates through the dielectric layer, the first grid oxide layer, the grid layer and the second grid oxide layer to be connected with the P-type heavily doped region.
Optionally, a plurality of trenches are arranged in the P well region; polycrystalline silicon is arranged in the groove.
Optionally, the vertical end of the first collector region is in a strip shape, a zigzag shape or a zigzag shape.
Optionally, the vertical end of the first collector region passes through the cut-off region and contacts the drift region.
Optionally, the first collector region and the second collector region have different conductivity types.
Optionally, the carrier storage layer is U-shaped; and two ends of the U shape are contacted with the P well region.
Optionally, the carrier storage layer includes a plurality; the carrier storage layers are distributed below the P well region at equal intervals.
According to the specific embodiment provided by the invention, the invention discloses the following technical effects: the invention provides an RC-IGBT device, wherein a current carrier storage layer is arranged at the bottom of a P well region, so that the conductivity modulation efficiency can be effectively improved, and the probability of insufficient single-current-carrier conductivity modulation is reduced, thereby reducing the on-resistance and avoiding the negative resistance phenomenon; meanwhile, different cut-off regions and collector regions are arranged, the first cut-off region and the second cut-off region are isolated by the vertical end of the first collector region, the moving path of a single carrier is increased by the vertical end of the first collector region, and therefore the potential difference between the first collector region and the second collector region of the RC-IGBT device is increased, and the negative resistance phenomenon can be further effectively inhibited.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings needed to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings without inventive exercise.
Fig. 1 is a structural diagram of an RC-IGBT device provided by the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The invention aims to provide an RC-IGBT device which can effectively inhibit the negative resistance phenomenon.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in further detail below.
Fig. 1 is a structural diagram of an RC-IGBT device provided by the present invention, and as shown in fig. 1, an RC-IGBT device includes: the semiconductor device comprises a dielectric layer 1, a gate electrode layer 2, a gate oxide layer arranged on two sides of the gate electrode layer 2, a P well region 3, a current carrier storage layer 4, a P type heavily doped region 5, a drift region 6, a cut-off region 7, a collector region 8 and a collector electrode 9; a first grid oxide layer 2-1 is arranged between the dielectric layer 1 and the grid layer 2; a second gate oxide layer 2-2 is arranged between the gate layer 2 and the P well region 3; the P-type heavily doped regions 5 are arranged on two sides of the P-well region 3; a current carrier storage layer 4 is arranged at the bottom of the P well region 3; the carrier storage layer 4 is arranged in the drift region 6; a collector electrode 9, a collector region 8 and a cut-off region 7 are sequentially arranged at the bottom of the drift region 6 from bottom to top; the collector region 8 comprises a first collector region 8-1 and a second collector region 8-2; the cut-off region 7 comprises a first cut-off region 7-1 and a second cut-off region 7-2; the first cut-off region 7-1 is arranged at the upper part of the first collector region 8-1, the second cut-off region 7-2 is arranged at the upper part of the second collector region 8-2, and the first cut-off region 7-1 and the second cut-off region 7-2 are isolated by the vertical end of the first collector region 8-1; the first collector region 8-1 is in contact with the second collector region 8-2.
In practical application, the method further comprises the following steps: a metal wiring 10.
The metal connecting wire 10 sequentially penetrates through the dielectric layer 1, the first grid oxide layer 2-1, the grid layer 2 and the second grid oxide layer 2-2 to be connected with the P-type heavily doped region 5.
In practical application, a plurality of grooves are arranged in the P well region 3; polycrystalline silicon is arranged in the groove.
In practical application, the vertical end of the first collector region 8-1 is in a strip shape, a zigzag shape or a zigzag shape. The vertical ends are set to be different in shape, so that the moving distance of single carriers is increased, and the negative resistance phenomenon is further inhibited.
In practical applications, the vertical end of the first collector region 8-1 passes through the cut-off region 7 to contact the drift region 6.
In practical applications, the first collector region 8-1 and the second collector region 8-2 have different conductivity types.
In practical application, the carrier storage layer 4 is in a U shape; the two ends of the U shape are contacted with the P well region 3.
In practical applications, the carrier storage layer 4 includes a plurality of layers; the carrier storage layers 4 are distributed at equal intervals below the P well regions 3.
The invention provides an RC-IGBT device which can effectively improve the conductivity modulation efficiency and reduce the probability of insufficient single-carrier conductivity modulation, thereby reducing the on-resistance and avoiding the negative resistance phenomenon.
The embodiments in the present description are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other.
The principles and embodiments of the present invention have been described herein using specific examples, which are provided only to help understand the method and the core concept of the present invention; meanwhile, for a person skilled in the art, according to the idea of the present invention, the specific embodiments and the application range may be changed. In view of the above, the present disclosure should not be construed as limiting the invention.
Claims (7)
1. An RC-IGBT device, comprising: the semiconductor device comprises a dielectric layer, a gate oxide layer, a P well region, a current carrier storage layer, a P type heavily doped region, a drift region, a cut-off region, a collector region and a collector electrode, wherein the gate oxide layer, the P well region, the current carrier storage layer, the P type heavily doped region, the drift region, the cut-off region, the collector region and the collector electrode are arranged on two sides of the gate layer;
a first grid oxide layer is arranged between the dielectric layer and the grid layer; a second grid oxide layer is arranged between the grid layer and the P well region; the two sides of the P well region are provided with the P type heavily doped regions; a current carrier storage layer is arranged at the bottom of the P well region; the carrier storage layer is arranged in the drift region; a collector electrode, a collector region and a cut-off region are sequentially arranged at the bottom of the drift region from bottom to top;
the collector region comprises a first collector region and a second collector region; the cut-off region comprises a first cut-off region and a second cut-off region;
the first cut-off region is arranged at the upper part of the first collector region, the second cut-off region is arranged at the upper part of the second collector region, and the first cut-off region and the second cut-off region are isolated by the vertical end of the first collector region; the first collector region is in contact with the second collector region;
the carrier storage layer is U-shaped; and two ends of the U shape are contacted with the P well region.
2. The RC-IGBT device of claim 1, further comprising: metal connecting wires;
the metal connecting wire sequentially penetrates through the dielectric layer, the first grid oxide layer, the grid layer and the second grid oxide layer to be connected with the P-type heavily doped region.
3. The RC-IGBT device of claim 1, wherein a plurality of trenches are disposed in the P-well region; polycrystalline silicon is arranged in the groove.
4. The RC-IGBT device according to claim 1, wherein the vertical end of the first collector region is shaped as a bar, a zigzag, or a dog-leg.
5. The RC-IGBT device of claim 1, wherein a vertical end of the first collector region contacts the drift region through the blocking region.
6. The RC-IGBT device of claim 1, wherein the first collector region and the second collector region are of different conductivity types.
7. The RC-IGBT device according to claim 1, wherein the carrier storage layer comprises a plurality; the carrier storage layers are distributed below the P well region at equal intervals.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811587937.8A CN109713030B (en) | 2018-12-25 | 2018-12-25 | RC-IGBT device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811587937.8A CN109713030B (en) | 2018-12-25 | 2018-12-25 | RC-IGBT device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN109713030A CN109713030A (en) | 2019-05-03 |
| CN109713030B true CN109713030B (en) | 2021-12-31 |
Family
ID=66257490
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201811587937.8A Expired - Fee Related CN109713030B (en) | 2018-12-25 | 2018-12-25 | RC-IGBT device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN109713030B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112331715B (en) * | 2019-08-05 | 2024-04-02 | 广东美的白色家电技术创新中心有限公司 | Insulated gate bipolar transistor and manufacturing method thereof |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0837508A2 (en) * | 1996-10-18 | 1998-04-22 | Hitachi, Ltd. | Semiconductor device and electric power conversion apparatus therewith |
| CN102157551A (en) * | 2011-03-10 | 2011-08-17 | 电子科技大学 | IGBT with current carrier storage layer and additional hole passage |
| CN105047705A (en) * | 2015-06-30 | 2015-11-11 | 西安理工大学 | Electron injection enhanced high voltage IGBT and manufacturing method thereof |
| CN105355655A (en) * | 2015-11-16 | 2016-02-24 | 电子科技大学 | Trench insulated gate bipolar transistor |
| WO2018016208A1 (en) * | 2016-07-19 | 2018-01-25 | 三菱電機株式会社 | Semiconductor device, and manufacturing method for same |
| CN108649068A (en) * | 2018-06-29 | 2018-10-12 | 中国科学院微电子研究所 | RC-IGBT device and preparation method thereof |
-
2018
- 2018-12-25 CN CN201811587937.8A patent/CN109713030B/en not_active Expired - Fee Related
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0837508A2 (en) * | 1996-10-18 | 1998-04-22 | Hitachi, Ltd. | Semiconductor device and electric power conversion apparatus therewith |
| CN102157551A (en) * | 2011-03-10 | 2011-08-17 | 电子科技大学 | IGBT with current carrier storage layer and additional hole passage |
| CN105047705A (en) * | 2015-06-30 | 2015-11-11 | 西安理工大学 | Electron injection enhanced high voltage IGBT and manufacturing method thereof |
| CN105355655A (en) * | 2015-11-16 | 2016-02-24 | 电子科技大学 | Trench insulated gate bipolar transistor |
| WO2018016208A1 (en) * | 2016-07-19 | 2018-01-25 | 三菱電機株式会社 | Semiconductor device, and manufacturing method for same |
| CN108649068A (en) * | 2018-06-29 | 2018-10-12 | 中国科学院微电子研究所 | RC-IGBT device and preparation method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN109713030A (en) | 2019-05-03 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN108767000B (en) | Insulated gate bipolar semiconductor device and manufacturing method thereof | |
| CN103208531B (en) | Fast recovery diode (FRD) chip and manufacturing method for FRD chip | |
| CN103733344A (en) | Semiconductor device | |
| CN110379852B (en) | Groove type IGBT device capable of reducing Miller capacitance | |
| CN100521207C (en) | Semiconductor device having IGBT and diode | |
| CN202282352U (en) | High-voltage IGBT forming FS layer through epitaxial method | |
| CN103489910A (en) | Power semiconductor device and manufacturing method thereof | |
| CN104319287A (en) | Trench gate type semiconductor device structure and manufacturing method thereof | |
| CN115832057A (en) | Silicon carbide MOSFET device and preparation method thereof | |
| CN102544084B (en) | Insulated gate bipolar translator (IGBT) device with two short-circuit positive electrodes | |
| CN109713030B (en) | RC-IGBT device | |
| CN208570614U (en) | A kind of insulated gate bipolar semiconductor devices | |
| CN115050815B (en) | Self-protection semiconductor structure and manufacturing method | |
| CN108767001B (en) | Trench IGBT device with shielding gate | |
| CN216450648U (en) | Self-aligned split gate structure | |
| CN103022155A (en) | Groove MOS (metal oxide semiconductor) structure Schottky diode and preparation method thereof | |
| CN212874493U (en) | Planar groove gate IGBT semiconductor power device | |
| CN111211167B (en) | RC-IGBT device structure for eliminating negative resistance effect | |
| CN108091567A (en) | Half superjunction FS IEGT structures and its manufacturing method | |
| CN111293168B (en) | IGBT device and manufacturing method thereof | |
| CN114300536A (en) | Gate-controlled fast ionization transistor and symmetric structure thereof | |
| CN113725209A (en) | Multi-chip parallel structure for SiC/Si Cascode device | |
| CN205900548U (en) | High efficiency carborundum schottky chip | |
| CN216980569U (en) | Super junction RB-IGBT device structure | |
| CN112750902B (en) | Trench gate IGBT with high short-circuit resistance |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20211231 |
|
| CF01 | Termination of patent right due to non-payment of annual fee |