CN216980569U

CN216980569U - Super junction RB-IGBT device structure

Info

Publication number: CN216980569U
Application number: CN202122270243.5U
Authority: CN
Inventors: 吴玉舟; 刘铁川; 李欣; 李菲; 禹久赢
Original assignee: Super Semiconductor Shanghai Co ltd
Current assignee: Super Semiconductor Shanghai Co ltd
Priority date: 2021-09-18
Filing date: 2021-09-18
Publication date: 2022-07-15
Anticipated expiration: 2031-09-18

Abstract

The utility model discloses a super-junction RB-IGBT device structure, which comprises: a metallized collector layer; a P-type collector region located above the metalized collector layer; the first N-type epitaxial layer is positioned above the P-type collector region; the second N-type epitaxial layer is positioned above the first N-type epitaxial layer; and a P-type buried layer is formed in the first N-type epitaxial layer through high-energy ion implantation, P columns are arranged in the first N-type epitaxial layer and spaced from the P-type buried layer, and the P columns are formed through deep groove etching and backfilling processes. According to the super-junction RB-IGBT device, the reverse withstand voltage can be borne, various optimized structures can be adopted through the design of the P-type collector region, and the electrical performance and reliability of the super-junction RB-IGBT device are improved.

Description

Super junction RB-IGBT device structure

Technical Field

The utility model relates to the technical field of power semiconductors, in particular to a super-junction RB-IGBT device structure.

Background

An RB-IGBT (Reverse Blocking Insulated Gate Bipolar Transistor) is an IGBT device having Reverse Blocking capability, and has the same level of withstand voltage capability in the forward and Reverse directions. By the development and the demand of a modern digital alternating current system driving and electric energy conversion module, the RB-IGBT is of great importance to electric energy conversion efficiency, energy utilization rate, system reliability and the like. The two RB-IGBTs are connected in anti-parallel to form a bidirectional switch, and the bidirectional switch can control current flowing in two directions. Compared with a traditional bidirectional switch formed by two common IGBTs and two FRDs, the RB-IGBT is used without an additional FRD, the number of components is saved, and the packaging volume is reduced. Therefore, the RB-IGBT is suitable for application in AC-AC conversion devices such as matrix converters, alternating current choppers and the like.

The conventional RB-IGBT is manufactured using a Non-Punch-Through (NPT) IGBT structure. However, NPT-IGBT has no junction termination structure during reverse voltage withstanding, and cannot achieve the same voltage withstanding capability as the forward direction, so the current processing mode is to manufacture heavily doped P-type regions penetrating through the whole chip up and down in the termination region of the device as the termination structure of the reverse voltage withstanding (Takei, M; Natio, T; Ueno, K.the R-even Blocking IGBT for Matrix Converter With Ultra-Thin Wafer technology. proceedings ISPSD2003, pp.129-132). However, for the IGBT device with 600V or more, the manufacturing process of the heavily doped P-type region is complex, and occupies a huge chip area, increasing the manufacturing difficulty and cost. In addition, the NPT structure is used for having adverse effects on the forward conduction voltage drop and turn-off loss of the IGBT device.

SUMMERY OF THE UTILITY MODEL

Aiming at the defects in the prior art, the utility model aims to provide a super-junction RB-IGBT device structure which has the capability of bearing reverse withstand voltage, and can adopt various optimized structures through the design of a P-type collector region, so that the electrical performance and the reliability of the super-junction RB-IGBT device are improved. To achieve the above objects and other advantages in accordance with the present invention, there is provided a super junction RB-IGBT device structure including:

A metallized collector layer;

the P-type collector region is positioned above the metalized collector layer;

the first N-type epitaxial layer is positioned above the P-type collector region;

the second N-type epitaxial layer is positioned above the first N-type epitaxial layer;

and a P-type buried layer is formed in the first N-type epitaxial layer through high-energy ion implantation, P columns are arranged in the first N-type epitaxial layer and spaced from the P-type buried layer, and the P columns are formed through deep groove etching and backfilling processes.

Preferably, a groove gate is formed in the second N-type epitaxial layer through reactive ion etching, a gate oxide layer is formed on the surface of the groove gate through thermal growth, and heavily doped polysilicon is deposited in the groove gate.

Preferably, a P-type body region is formed above the second N-type epitaxial layer by self-aligned process ion implantation annealing.

Preferably, heavily doped N-type emitting regions are arranged on two sides of one end, away from the first N-type epitaxial layer, of the groove gate, boron-phosphorus-silicon glass is deposited above the second N-type epitaxial layer, and an upper surface metalized emitter is arranged above the boron-phosphorus-silicon glass.

Preferably, the thickness and the doping concentration of the P-type buried layer are adjusted according to a device, the position of the P-type buried layer relative to the P-type collector region is adjusted according to a device structure, and the width of the P-type buried layer is determined by a P column in the first N-type epitaxial layer.

Preferably, when the device framework is an NPT structure, the P-type buried layer is arranged in a floating mode and is connected with the P-type collector region;

when the device framework is an FS structure, the P-type buried layer is arranged in a floating mode and is located above an FS layer.

Preferably, the P column in the first N-type epitaxial layer is not connected to the P-type body region in the second N-type epitaxial layer.

Compared with the prior art, the utility model has the beneficial effects that: the super junction structure is manufactured by adopting deep groove etching and backfilling processes, so that the forward conduction voltage drop of the device can be reduced, and the switching speed is increased. The reverse blocking capability of the device is obtained by manufacturing the P-type buried layer through high-energy ion implantation after the deep groove is etched, the manufacturing process is simple, no extra area is occupied, and the chip cost is saved. The floating design of the P-type buried layer does not affect the optimization of the collector side of the IGBT device, and the compromise relationship between the forward conduction voltage drop, the turn-off loss and the safe working area of the IGBT device can be optimized by adopting structures such as a Field Stop layer (FS), a transparent collector and the like on the collector side of the device.

Drawings

FIG. 1 is a schematic structural diagram of a conventional NPT-IGBT device structure;

fig. 2 is a schematic structural diagram of a first embodiment of a super junction RB-IGBT device structure according to the present invention;

Fig. 3 is a schematic structural diagram of a second embodiment of a super junction RB-IGBT device structure according to the utility model;

fig. 4 is a schematic structural diagram of a super junction RB-IGBT device structure according to a third embodiment of the utility model.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be obtained by a person skilled in the art without making any creative effort based on the embodiments in the present invention, belong to the protection scope of the present invention.

Referring to fig. 1-4, a super junction RB-IGBT device structure includes: a metallized collector layer 1; the P-type collector region 2 is positioned above the metalized collector layer 1; the first N-type epitaxial layer 3 is positioned above the P-type collector region 2; the second N-type epitaxial layer 4 is positioned above the first N-type epitaxial layer 3; the super-junction RB-IGBT device is characterized in that a P-type buried layer 102 is formed in the first N-type epitaxial layer 3 through high-energy ion implantation, P columns 101 are arranged in the first N-type epitaxial layer 3 and spaced from the P-type buried layer 102, and the P columns 101 are formed through deep groove etching and backfilling processes. When the device is in a reverse cut-off state, a transverse electric field is still generated by a super junction structure formed by the P column in the first N-type epitaxial layer 3 and the N-type epitaxial layer, but a longitudinal electric field is formed by the first N-type epitaxial layer 3, the P-type buried layer 102 and the P-type collector region together, so that the device has the capability of bearing reverse withstand voltage. The floating P-type buried layer 102 can be completely depleted or partially depleted during reverse voltage resistance, and the design of the P-type buried layer 102 is optimized so that depletion layers generated by two adjacent P-type buried layers 102 can shield the P-type collector region 2, and therefore the P-type collector region 2 can not participate in voltage resistance during reverse voltage resistance. Therefore, the design of the P-type collector region can adopt various optimized structures, and the electrical performance and the reliability of the super-junction RB-IGBT device can be improved.

Further, a trench gate 5 is formed in the second N-type epitaxial layer 4 through reactive ion etching, a gate oxide layer 6 is formed on the surface of the trench gate 5 through thermal growth, and heavily doped polysilicon 7 is deposited in the trench gate 5.

Further, a P-type body region 8 is formed above the second N-type epitaxial layer 4 by self-aligned process ion implantation annealing.

Furthermore, heavily doped N-type emitter regions 9 are arranged on two sides of one end, away from the first N-type epitaxial layer 3, of the trench gate 5, borophosphosilicate glass 10 is deposited above the second N-type epitaxial layer 4, and an upper surface metalized emitter 11 is arranged above the borophosphosilicate glass 10.

Further, the thickness and the doping concentration of the P-type buried layer 102 are adjusted according to the device, the position of the P-type buried layer 102 relative to the P-type collector region 2 is adjusted according to the device structure, and the width of the P-type buried layer 102 is determined by the P-pillars 101 in the first N-type epitaxial layer 3.

Further, when the device framework is an NPT structure, the P-type buried layer 102 is arranged in a floating mode, and the P-type buried layer 102 is connected with the P-type collector region 2;

when the device structure is an FS structure, the P-type buried layer 102 is disposed in a floating manner and above the FS layer.

Further, the P pillars 101 in the first N-type epitaxial layer 3 are not connected to the P-type body regions 8 in the second N-type epitaxial layer 4.

The number of devices and the scale of the processes described herein are intended to simplify the description of the utility model, and applications, modifications and variations of the utility model will be apparent to those skilled in the art.

While embodiments of the utility model have been described above, it is not intended to be limited to the details shown, described and illustrated herein, but is to be accorded the widest scope consistent with the principles and novel features herein disclosed, and to such extent that such modifications are readily available to those skilled in the art, and it is not intended to be limited to the details shown and described herein without departing from the general concept as defined by the appended claims and their equivalents.

Claims

1. A super junction RB-IGBT device structure, comprising:

a metallized collector layer (1);

a P-type collector region (2), wherein the P-type collector region (2) is positioned above the metalized collector layer (1);

the first N-type epitaxial layer (3) is positioned above the P-type collector region (2);

the second N-type epitaxial layer (4), the second N-type epitaxial layer (4) is positioned above the first N-type epitaxial layer (3);

the first N-type epitaxial layer (3) is internally provided with a P-type buried layer (102) through high-energy ion implantation, P columns (101) are arranged in the first N-type epitaxial layer (3) and spaced from the P-type buried layer (102), and the P columns (101) are formed through deep trench etching and backfilling processes.

2. A super junction RB-IGBT device structure according to claim 1, characterized in that the second N-type epitaxial layer (4) is formed with trench gates (5) by reactive ion etching, the surface of the trench gates (5) is thermally grown with a gate oxide layer (6), and heavily doped polysilicon (7) is deposited inside the trench gates (5).

3. A super junction RB-IGBT device structure according to claim 1, characterized in that a P-type body region (8) is formed above said second N-type epitaxial layer (4) by self-aligned process ion implantation annealing.

4. A super junction RB-IGBT device structure according to claim 2, characterized in that both sides of one end of the trench gate (5) far away from the first N-type epitaxial layer (3) are provided with heavily doped N-type emitter regions (9), and a borophosphosilicate glass (10) is deposited on top of the second N-type epitaxial layer (4), and an upper surface metalized emitter (11) is arranged on top of the borophosphosilicate glass (10).

5. A super junction RB-IGBT device structure according to claim 1, wherein the thickness and doping concentration of the P-type buried layer (102) are adjusted according to the device, and the position of the P-type buried layer (102) relative to the P-type collector region (2) is adjusted according to the device structure, the width of the P-type buried layer (102) being determined by the P-pillars (101) in the first N-type epitaxial layer (3).

6. The super-junction RB-IGBT device structure according to claim 5, characterized in that when the device structure is NPT structure, the P-type buried layer (102) is arranged in a floating mode, and the P-type buried layer (102) is connected with the P-type collector region (2);

when the device structure is an FS structure, the P-type buried layer (102) is arranged in a floating mode and is located above an FS layer.

7. A super junction RB-IGBT device structure according to claim 3, characterized in that the P-pillars (101) in the first N-type epitaxial layer (3) are unconnected to the P-type body regions (8) in the second N-type epitaxial layer (4).