CN113725282A - Super-junction RB-IGBT device structure and manufacturing method thereof - Google Patents
Super-junction RB-IGBT device structure and manufacturing method thereof Download PDFInfo
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- H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
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- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
- H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
- H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
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Abstract
The invention discloses a super-junction RB-IGBT device structure and a manufacturing method thereof, wherein the super-junction RB-IGBT device structure comprises the following steps: a metallized collector layer; a P-type collector region located above the metalized collector layer; the first N-type epitaxial layer is positioned above the P-type collector region; the second N-type epitaxial layer is positioned above the first N-type epitaxial layer; and a P-type buried layer is formed in the first N-type epitaxial layer through high-energy ion implantation, P columns are arranged in the first N-type epitaxial layer and spaced from the P-type buried layer, and the P columns are formed through deep groove etching and backfilling processes. According to the super-junction RB-IGBT device, the reverse withstand voltage can be borne, various optimized structures can be adopted through the design of the P-type collector region, and the electrical performance and reliability of the super-junction RB-IGBT device are improved.
Description
Technical Field
The invention relates to the technical field of power semiconductors, in particular to a super junction RB-IGBT device structure and a manufacturing method thereof.
Background
An RB-IGBT (Reverse Blocking Insulated Gate Bipolar Transistor) is an IGBT device having Reverse Blocking capability, and has the same level of withstand voltage capability in the forward and Reverse directions. By the development and the demand of a modern digital alternating current system driving and electric energy conversion module, the R B-IGBT is of great importance to electric energy conversion efficiency, energy utilization rate, system reliability and the like. The two RB-IGBTs are connected in anti-parallel to form a bidirectional switch, and the bidirectional switch can control current flowing in two directions. Compared with a traditional bidirectional switch formed by two common IGBTs and two FRDs, the RB-IGBT is used without an additional FRD, the number of components is saved, and the packaging volume is reduced. Therefore, the RB-IGBT is suitable for application in AC-AC conversion devices such as matrix converters, alternating current choppers and the like.
The conventional RB-IGBT is manufactured by adopting a Non-Punch-Through (NPT) IGBT structure. However, NPT-IGBT has no junction termination structure during reverse voltage resistance, and cannot achieve the same voltage resistance as the forward voltage resistance, so the current processing mode is to manufacture heavily doped P-type regions penetrating through the upper and lower parts of the whole chip in the termination region of the device as the termination structure of the reverse voltage resistance (Takei, M; Natio, T; Ueno, K.the R even Blocking IGBT for Matrix Converter With Ultra-Thin Wafer technology. Proceding ISPSD2003, pp.129-132). However, for IGBT devices of 600V or more, the heavily doped P-type region has a complex manufacturing process, occupies a large chip area, and increases manufacturing difficulty and cost. In addition, the NPT structure has adverse effects on the forward conduction voltage drop and turn-off loss of the IGBT device.
Disclosure of Invention
Aiming at the defects in the prior art, the invention aims to provide a super-junction RB-IGBT device structure and a manufacturing method thereof, wherein the super-junction RB-IGBT device structure has the capability of bearing reverse withstand voltage, and a plurality of optimized structures can be adopted through the design of a P-type collector region, so that the electrical performance and the reliability of the super-junction RB-IGBT device are improved. To achieve the above objects and other advantages in accordance with the present invention, there is provided a super junction RB-IGBT device structure and a method of manufacturing the same, including:
a metallized collector layer;
a P-type collector region located above the metalized collector layer;
the first N-type epitaxial layer is positioned above the P-type collector region;
the second N-type epitaxial layer is positioned above the first N-type epitaxial layer;
and a P-type buried layer is formed in the first N-type epitaxial layer through high-energy ion implantation, P columns are arranged in the first N-type epitaxial layer and spaced from the P-type buried layer, and the P columns are formed through deep groove etching and backfilling processes.
Preferably, a groove gate is formed in the second N-type epitaxial layer through reactive ion etching, a gate oxide layer is formed on the surface of the groove gate through thermal growth, and heavily doped polysilicon is deposited in the groove gate.
Preferably, a P-type body region is formed above the second N-type epitaxial layer by self-aligned process ion implantation annealing.
Preferably, heavily doped N-type emitting regions are arranged on two sides of one end, away from the first N-type epitaxial layer, of the groove gate, boron-phosphorus-silicon glass is deposited above the second N-type epitaxial layer, and an upper surface metalized emitter is arranged above the boron-phosphorus-silicon glass.
Preferably, the thickness and the doping concentration of the P-type buried layer are adjusted according to a device, the position of the P-type buried layer relative to the P-type collector region is adjusted according to a device structure, and the width of the P-type buried layer is determined by a P column in the first N-type epitaxial layer.
Preferably, when the device framework is an NPT structure, the P-type buried layer is arranged in a floating mode and is connected with the P-type collector region;
when the device structure is an FS structure, the P-type buried layer is arranged in a floating mode and is located above an FS layer.
Preferably, the P column in the first N-type epitaxial layer is not connected to the P-type body region in the second N-type epitaxial layer.
A manufacturing method of a super junction RB-IGBT device structure comprises the following steps:
s1, forming a P-type collector region and a first N-type epitaxial layer through the wafer by using an epitaxial wafer;
s2, forming a deep groove in the first N-type epitaxial layer through a reactive ion etching process;
s3, forming a P-type doping layer in the first N-type epitaxial layer by using the hard mask as a barrier layer and adopting high-energy ion implantation;
s4, forming a super junction structure P column in the first N type epitaxial layer by adopting a backfill process;
s5, forming a second N-type epitaxial layer through epitaxy, wherein the resistivity of the second N-type epitaxial layer is larger than that of the first N-type epitaxial layer;
s6, forming a groove gate in the second N-type epitaxial layer through reactive ion etching;
s7, thermally growing a gate oxide layer on the surface of the groove gate in a dry oxidation mode;
s8, depositing heavily doped polysilicon in the trench gate and etching back to form a gate;
s9, forming a P-type body region above the second N-type epitaxial layer through a self-alignment process, ion implantation and high-temperature drive-in, and finally forming a P-type buried layer through diffusion of the P-type doped layer;
s10, forming an emitting region in the P-type body region through photoetching injection;
s11, depositing boron-phosphorus-silicon glass above the groove grid, refluxing at high temperature, carrying out contact hole photoetching, etching silicon with the thickness of 3000-;
and S12, turning the wafer and thinning the wafer, and depositing a metal layer to form a collector.
Compared with the prior art, the invention has the beneficial effects that: the super junction structure is manufactured by adopting deep groove etching and backfilling processes, so that the forward conduction voltage drop of the device can be reduced, and the switching speed is improved. The reverse blocking capability of the device is obtained by manufacturing the P-type buried layer through high-energy ion implantation after the deep groove is etched, the manufacturing process is simple, the extra area is not occupied, and the chip cost is saved. The floating design of the P-type buried layer does not affect the optimization of the collector side of the IGBT device, and the compromise relationship between the forward conduction voltage drop, the turn-off loss and the safe working area of the IGBT device can be optimized by adopting structures such as a Field Stop layer (FS), a transparent collector and the like on the collector side of the device.
Drawings
FIG. 1 is a schematic structural diagram of a conventional NPT-IGBT device structure and a method for fabricating the same;
fig. 2 is a schematic structural view of a first embodiment of a super junction RB-IGBT device structure and a method of manufacturing the same according to the present invention;
fig. 3 is a schematic structural diagram of a second embodiment of a super junction RB-IGBT device structure and a manufacturing method thereof according to the present invention;
fig. 4 is a schematic structural diagram of a third embodiment of a super junction RB-IGBT device structure and a manufacturing method thereof according to the present invention;
fig. 5-1 to 5-12 are manufacturing flow structures of steps of a super junction RB-IGBT device structure and a method of manufacturing the same according to the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Referring to fig. 1-4, a super junction RB-IGBT device structure and a method of manufacturing the same includes: a metallized collector layer 1; the P-type collector region 2 is positioned above the metalized collector layer 1; the first N-type epitaxial layer 3 is positioned above the P-type collector region 2; the second N-type epitaxial layer 4 is positioned above the first N-type epitaxial layer 3; the super-junction RB-IGBT device is characterized in that a P-type buried layer 102 is formed in the first N-type epitaxial layer 3 through high-energy ion implantation, P columns 101 are arranged in the first N-type epitaxial layer 3 and spaced from the P-type buried layer 102, and the P columns 101 are formed through deep groove etching and backfilling processes. When the device is in a reverse cut-off state, a transverse electric field is still generated by a super junction structure formed by the P column in the first N-type epitaxial layer 3 and the N-type epitaxial layer, but a longitudinal electric field is formed by the first N-type epitaxial layer 3, the P-type buried layer 102 and the P-type collector region together, so that the device has the capability of bearing reverse withstand voltage. The floating P-type buried layer 102 can be completely or partially depleted during reverse voltage resistance, and the design of the P-type buried layer 102 is optimized so that depletion layers generated by two adjacent P-type buried layers 102 shield the P-type collector region 2, so that the P-type collector region 2 does not participate in voltage resistance during reverse voltage resistance. Therefore, the design of the P-type collector region can adopt various optimized structures, and the electrical performance and the reliability of the super-junction RB-IGBT device can be improved.
Further, a groove gate 5 is formed in the second N-type epitaxial layer 4 through reactive ion etching, a gate oxide layer 6 is formed on the surface of the groove gate 5 through thermal growth, and heavily doped polysilicon 7 is deposited in the groove gate 5.
Further, a P-type body region 8 is formed above the second N-type epitaxial layer 4 by self-aligned process ion implantation annealing.
Furthermore, heavily doped N-type emitting regions 9 are arranged on two sides of one end, away from the first N-type epitaxial layer 3, of the trench gate 5, borophosphosilicate glass 10 is deposited above the second N-type epitaxial layer 4, and an upper surface metalized emitting electrode 11 is arranged above the borophosphosilicate glass 10.
Further, the thickness and the doping concentration of the P-type buried layer 102 are adjusted according to the device, the position of the P-type buried layer 102 relative to the P-type collector region 2 is adjusted according to the device structure, and the width of the P-type buried layer 102 is determined by the P-pillar 101 in the first N-type epitaxial layer 3.
Further, when the device architecture is an NPT structure, the P-type buried layer 102 is arranged in a floating mode, and the P-type buried layer 102 is connected with the P-type collector region 2;
when the device structure is an FS structure, the P-type buried layer 102 is disposed in a floating manner and above the FS layer.
Further, the P-pillars 101 in the first N-type epitaxial layer 3 are not connected to the P-type body regions 8 in the second N-type epitaxial layer 4.
Referring to fig. 5-1 to 5-12, a method for manufacturing a super junction RB-IGBT device structure includes the steps of:
s1, forming a P-type collector region 2 and a first N-type epitaxial layer 3 through a wafer by using epitaxial wafers;
s2, forming a deep groove in the first N-type epitaxial layer 3 through a reactive ion etching process;
s3, forming a P-type doped layer in the first N-type epitaxial layer 3 by using the hard mask as a barrier layer and adopting high-energy ion implantation;
s4, forming a super junction structure P column 101 in the first N type epitaxial layer 3 by adopting a backfill process;
s5, forming a second N-type epitaxial layer 4 through epitaxy, wherein the resistivity of the second N-type epitaxial layer 4 is larger than that of the first N-type epitaxial layer 3;
s6, forming a groove gate 5 in the second N-type epitaxial layer 4 through reactive ion etching;
s7, thermally growing a gate oxide layer 6 on the surface of the groove gate 5 in a dry oxidation mode;
s8, depositing heavily doped polysilicon 7 in the trench gate 5 and etching back to form a gate;
s9, forming a P-type body region 8 above the second N-type epitaxial layer 4 through a self-alignment process, ion implantation and high-temperature drive-in, and diffusing the P-type doped layer to finally form a P-type buried layer 102;
s10, forming an emitter region 9 in the P-type body region 8 through photoetching injection;
s11, depositing boron-phosphorus-silicon glass 10 above the groove gate 5, performing high-temperature reflux, performing contact hole photoetching, etching silicon with the thickness of 3000-;
and S12, turning the wafer and thinning the wafer, and depositing a metal layer to form the collector 1.
The number of devices and the scale of the processes described herein are intended to simplify the description of the invention, and applications, modifications and variations of the invention will be apparent to those skilled in the art.
While embodiments of the invention have been described above, it is not limited to the applications set forth in the description and the embodiments, which are fully applicable in various fields of endeavor to which the invention pertains, and further modifications may readily be made by those skilled in the art, it being understood that the invention is not limited to the details shown and described herein without departing from the general concept defined by the appended claims and their equivalents.
Claims (8)
1. A super junction RB-IGBT device structure, comprising:
a metallized collector layer (1);
a P-type collector region (2), wherein the P-type collector region (2) is positioned above the metalized collector layer (1);
the first N-type epitaxial layer (3), wherein the first N-type epitaxial layer (3) is positioned above the P-type collector region (2);
the second N-type epitaxial layer (4), the second N-type epitaxial layer (4) is positioned above the first N-type epitaxial layer (3);
a P-type buried layer (102) is formed in the first N-type epitaxial layer (3) through high-energy ion implantation, P columns (101) are arranged in the first N-type epitaxial layer (3) and spaced from the P-type buried layer (102), and the P columns (101) are formed through deep groove etching and backfilling processes.
2. A super junction RB-IGBT device structure according to claim 1, wherein the second N-type epitaxial layer (4) is formed with a trench gate (5) by reactive ion etching, the surface of the trench gate (5) is thermally grown to form a gate oxide layer (6), and the trench gate (5) is deposited with a heavily doped polysilicon (7).
3. A super junction RB-IGBT device structure according to claim 1, wherein a P-type body region (8) is formed over the second N-type epitaxial layer (4) by a self-aligned process ion implantation anneal.
4. A super junction RB-IGBT device structure according to claim 2, characterized in that the trench gate (5) is provided with heavily doped N-type emitter regions (9) on both sides of the end far away from the first N-type epitaxial layer (3), and a borophosphosilicate glass (10) is deposited on the second N-type epitaxial layer (4), and an upper surface metalized emitter (11) is provided on the borophosphosilicate glass (10).
5. A super junction RB-IGBT device structure according to claim 1, wherein the thickness and doping concentration of the P-type buried layer (102) are adjusted according to the device, and the position of the P-type buried layer (102) relative to the P-type collector region (2) is adjusted according to the device structure, and the width of the P-type buried layer (102) is determined by the P-pillars (101) in the first N-type epitaxial layer (3).
6. The super junction RB-IGBT device structure of claim 5, characterized in that when the device structure is NPT structure, the P type buried layer (102) is arranged in floating mode, and the P type buried layer (102) is connected with the P type collector region (2);
when the device structure is an FS structure, the P-type buried layer (102) is arranged in a floating mode and is located above the FS layer.
7. A super junction RB-IGBT device structure and its manufacturing method according to claim 3, characterized in that the P-columns (101) in the first N-type epitaxial layer (3) are not connected with the P-type body regions (8) in the second N-type epitaxial layer (4).
8. The manufacturing method of the super junction RB-IGBT device structure of claim 1, characterized by comprising the following steps:
s1, forming a P-type collector region (2) and a first N-type epitaxial layer (3) through a wafer by using an epitaxial wafer;
s2, forming a deep groove in the first N-type epitaxial layer (3) through a reactive ion etching process;
s3, forming a P-type doped layer in the first N-type epitaxial layer (3) by using the hard mask as a barrier layer and adopting high-energy ion implantation;
s4, forming a super junction structure P column (101) in the first N type epitaxial layer (3) by adopting a backfill process;
s5, forming a second N-type epitaxial layer (4) through epitaxy, wherein the resistivity of the second N-type epitaxial layer (4) is larger than that of the first N-type epitaxial layer (3);
s6, forming a groove gate (5) in the second N-type epitaxial layer (4) through reactive ion etching;
s7, thermally growing a gate oxide layer (6) on the surface of the trench gate (5) in a dry oxidation mode;
s8, depositing heavily doped polysilicon (7) in the groove gate (5) and reversely etching to form a gate;
s9, forming a P-type body region (8) above the second N-type epitaxial layer (4) through a self-alignment process, ion implantation and high-temperature drive-in, and diffusing the P-type doped layer to finally form a P-type buried layer (102);
s10, forming an emitter region (9) in the P-type body region (8) through photoetching injection;
s11, depositing boron phosphorus silicon glass (10) above the groove gate (5), reflowing at high temperature, carrying out contact hole photoetching, etching silicon with the thickness of 3000-5000A, and depositing upper surface metal to form an emitter (11);
and S12, turning the wafer and thinning the wafer, and depositing a metal layer to form a collector (1).
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| CN116364772A (en) * | 2023-04-11 | 2023-06-30 | 上海超致半导体科技有限公司 | Super-junction IGBT power device and preparation method |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116364772A (en) * | 2023-04-11 | 2023-06-30 | 上海超致半导体科技有限公司 | Super-junction IGBT power device and preparation method |
| CN116364772B (en) * | 2023-04-11 | 2024-01-30 | 上海超致半导体科技有限公司 | Super-junction IGBT power device and preparation method |
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