CN109148566A - Silicon carbide MOSFET device and its manufacturing method - Google Patents
Silicon carbide MOSFET device and its manufacturing method Download PDFInfo
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- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 title claims abstract description 323
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 19
- 238000000034 method Methods 0.000 claims abstract description 67
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- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 71
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 9
- 239000010703 silicon Substances 0.000 claims description 9
- 229910052760 oxygen Inorganic materials 0.000 claims description 8
- 239000001301 oxygen Substances 0.000 claims description 8
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- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 7
- 229910003978 SiClx Inorganic materials 0.000 claims description 7
- 229910052799 carbon Inorganic materials 0.000 claims description 7
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- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 2
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 238000011160 research Methods 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 230000001052 transient effect Effects 0.000 description 2
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 1
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System
- H01L29/1608—Silicon carbide
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
Abstract
The present invention provides a kind of silicon carbide MOSFET device and its manufacturing method, and the present invention is directed to Conventional silicon carbide UMOSFET structure, proposes how sub- rectifying device integration mode, include the implementation method of Schottky contacts and Si/SiC heterojunction.The invention realizes the integrated of how sub- rectifying device, to greatly optimize device third quadrant working performance while effectively improving tradition carbonization UMOSFET fundamental characteristics, optimised devices permanent application reliability.It realizes technique and Conventional silicon carbide UMOSFET process compatible to the structure, has the characteristics that be easy to make.
Description
Technical field
The invention belongs to power semiconductor technologies, in particular to a kind of metal oxide semiconductor field-effect
(MOSFET) device architecture and preparation method thereof.
Background technique
Energy resources are the important material bases that the mankind depended on and realized development for existence, are that the mankind carry out the dynamic of production and living
Power source.Many energy resources are inexhaustible, nexhaustible, such as wind energy, solar energy and tide energy.However in production and living
Used main energy sources are non-renewable energy resources, including fossil energy, coal and natural gas etc., have thus caused complete
Ball energy crisis.Since the 21th century from the mankind, which more attracts people's attention.How to reduce in production and living not
How necessary energy loss improves the utilization rate of energy resources, be the important means for alleviating global energy crisis.Electric energy is made
It is indispensable already in life for one of the energy that the mankind can directly use.Electric system be human use's electric energy and
The necessary ways of electric energy service efficiency are improved, electric system transports electric energy, manages and the height of service efficiency, embodies electricity
The up-to-dateness of Force system, and then the mankind are embodied for the height of energy resources utilization efficiency.And according to statistics, in the world
90% or more electric energy passes through electric power system control by power device.For certain angle, the control electric energy of power device
The height of efficiency, concerning human kind sustainable development.
Power device is dominated by silicon-based power devices instantly, mainly with thyristor, power P IN device, power bipolar junction
Based on device, Schottky barrier diode, power MOSFET and isolated-gate field effect transistor (IGFET), in full power range
To being widely applied, the master of power semiconductor has been captured with its long history, mature designing technique and technology
Lead market.
Silicon carbide MOSFET device is the generation semiconductor devices manufactured with semiconductor material with wide forbidden band silicon carbide.Carbonization
The many attracting characteristics of silicon materials, critical breakdown electric field intensity, high thermal conductivity, the big forbidden band of such as 10 times of silicon materials are wide
Degree and high electronics saturation drift velocity etc. make SiC material become the research hotspot of power semiconductor in the world, and
High power applications occasion, such as high-speed railway, hybrid vehicle, intelligent high-pressure direct current transportation, silicon carbide device are endowed
Very high expectation.Silicon carbide power device is significant to the reducing effect of power loss simultaneously, so that silicon carbide power device quilt
It is described as " green energy resource " device of drive " new energy revolution ".However because the undesirable of MOS channel leads to MOS channel mobility
It is too low, significantly limit silicon carbide MOSFET on state current density.Therefore, bigger with higher gully density, to have
The extensive concern and research that the silicon carbide trench MOSFET of on state current density is subject to.Although silicon carbide trench MOSFET has
There are lower on state resistance and more compact cellular layout to give silicon carbide ditch due to the problem that bottom gate electric field across oxide is excessively high
Groove profile MOSFET, which is used for a long time, brings integrity problem, leads to device poor robustness.Conventional silicon carbide UMOSFET structure such as Fig. 1
It is shown.
Silicon carbide MOSFET device is in the application, it usually needs uses with a diode inverse parallel.It can there are two types of mode
To reach this purpose.One is directly using the device silicon carbide p-type base area and silicon carbide N-Drift region, silicon carbide N+substrate
The parasitic diode of formation.The parasitism silicon carbide diode conduction voltage drop is big (silicon carbide PN junction conduction voltage drop is about 3.1V), and
Reverse recovery characteristic poor (drift region conductance modulation injects excessive carrier when forward conduction) causes high power loss,
It is unfavorable for its popularization in power market；Cause working efficiency low because operating rate is low simultaneously, for silicon carbide
MOSFET element is totally unfavorable in the application such as inverter circuit, chopper circuit；The second is by the way that device is anti-with external diode
It is used in parallel.This method increase metal number of interconnections, increase stray inductance, are unfavorable for the promotion of system reliability；Meanwhile
Due to the increase of device count, system bulk is caused to increase, matched radiating requirements are also promoted, packaging cost also on
It rises.The above variety of problems makes popularization of the silicon carbide MOSFET device in numerous practical applications receive certain obstruction.
Summary of the invention
The present invention needs to solve, i.e., in view of the above-mentioned problems, proposing a kind of silicon carbide MOSFET device that can optimize in inversion
Device poor robustness caused by gate dielectric layer electric field present in the application such as circuit, chopper circuit is excessively high, power loss are high, work
The silicon carbide MOSFET device and its manufacturing method of the problems such as low efficiency, higher production cost.Specifically, the present invention by
On the basis of Conventional silicon carbide UMOSFET structure (as shown in Figure 1), by improving device architecture, near grid and silicon carbide P
+ contact zone is formed about silicon carbide depth P doped region, and the processes such as etched, deposit are formed near the contact zone former silicon carbide P+
The deposit of Schottky contact metal or polysilicon.The Schottky contact metal or polysilicon directly connect with silicon carbide N-extension
Touching, ultimately forms Schottky contacts or heterojunction with rectification characteristic.When the material of deposit is metal, it is formed by
Contact, barrier height can be adjusted by changing metal material, technology controlling and process and silicon carbide N-extension concentration, finally
Form the Schottky contacts compared with low conduction voltage drop (Von).Usual contact Von is in the range of 0.8V~2V.To realize just
It is internal integrated better than the Schottky diode of parasitic diode to working performance.Since the diode is how sub- device, reversely
Since there is no few sub- storage in recovery process, there is faster reverse recovery time, lower reverse recovery loss and more
The Reverse recovery reliability added has more preferably Reverse recovery performance compared with parasitic diode.The improvement is relative to external
The mode of one diode of inverse parallel, significantly reduces power electronic system volume, reduces encapsulation and spends.Simultaneously because not having
There is the metal lead wire between diode, avoid metal lead wire bring ghost effect, so that it is reliable to improve system application
Property.Meanwhile the mode relative to numerous internal single-chip integration diodes, structure of the invention have more compact cell density.
Cell density after integrated diode is identical with Conventional silicon carbide depth P doping MOSFET, while not influencing MOSFET element
Basic performance.Therefore structure of the invention advantage with good performance.When the material of deposit is polysilicon, being formed by contact is
Heterojunction.Its characteristic is approximate with Schottky contacts: being all how sub- device, while also having rectification characteristic.Its forward conduction
Pressure drop Von is about 1.1V, better than the parasitic diode characteristic of silicon carbide MOSFET, for optimised devices third quadrant working characteristics
Equally have the function of splendid.In addition, the area silicon carbide P+ below Schottky contact metal material or polysilicon is to Xiao Te
While base contact metal material or polysilicon play a protective role, device gate dielectric electric field is also significantly reduced, device is optimized
Part field distribution improves the resistance to voltage levels of device；The area JFET Effective Doping can be promoted further simultaneously, that is, effectively reduce device
Part ratio leads Ron.sp。
To achieve the above object, the invention adopts the following technical scheme:
A kind of silicon carbide MOSFET device, including set gradually from bottom to top drain metal 1, silicon carbide N+Substrate 2 and
Silicon carbide N-Epitaxial layer 3；The silicon carbide N-3 upper left side of epitaxial layer has active groove, and source groove is with the shallow lake of Schottky contact metal 12
Product filling；There is silicon carbide depth P doped region 4 below the Schottky contact metal 12；The Schottky contact metal 12 and carbon
SiClx N-Epitaxial layer 3 is directly contacted in channel bottom side wall, forms the Schottky contacts with rectification characteristic, the silicon carbide N-
3 upper right side of epitaxial layer has silicon carbide depth P doped region 4, and the silicon carbide depth P of 12 lower section of depth and Schottky contact metal is adulterated
Area 4 is identical；The silicon carbide N-The upper left side of the silicon carbide depth P doped region 4 in 3 upper right side of epitaxial layer, silicon carbide N-On epitaxial layer 3
Side has gate structure；The gate structure includes gate dielectric layer 5, polysilicon gate 6 and gate electrode 10；Polysilicon gate 6 is by grid
Dielectric layer 5 surrounds, and top is drawn by gate electrode 10, and the gate structure bottom is not less than Schottky contact metal 12, institute
It states on the left of gate structure, there is mesa structure on the right side of Schottky contact metal 12, the mesa structure includes the area silicon carbide Pbase
7 and silicon carbide N+source region 8, the silicon carbide N+source region 8 is located at 7 top of the area silicon carbide Pbase, 7 bottom of the area the silicon carbide Pbase
Portion is higher than gate structure bottom；Device surface is covered by one layer of source metal 9, and the source metal and gate metal 10 are by boron phosphorus
Silica glass BPSG11 is separated by.
It is preferred that carbofrax material Si, Ge, GaAs, GaN, diamond, SiGe, gallium oxide semiconductor material
Instead of.
It is preferred that 12 region of Schottky contact metal is polysilicon 13.
It is preferred that exceeding the right margin of silicon carbide depth P doped region 4 on the right side of the Schottky contact metal 12, no
It is only contacted in bottom sidewall with silicon carbide N-epitaxial layer 3, bottom part region is contacted with silicon carbide N-epitaxial layer 3 simultaneously.
It is preferred that 4 region of silicon carbide depth P doped region of 12 lower section of Schottky contact metal is dielectric layer
15, the dielectric layer and 12 lower section silicon carbide depth P doped region 4 of Schottky contact metal are in the same size.
It is preferred that the source beneath trenches have discontinuous groove in Z-direction, trench depth is less than or waits
In 4 depth of the first silicon carbide depth P doped region, trench interiors are filled with Schottky contact metal 12, and channel bottom is silicon carbide
N-Epitaxial layer 3.
It is preferred that there is the silicon carbide depth P doped region 4 in convex distribution, and carbon below the gate structure
The recess of SiClx depth P doped region 4 has Split-gate structure together with the bottom of gate structure entire in X-direction.
Further, a kind of silicon carbide MOSFET device, used in width, narrow bandgap material is not limited only to be carbonized
Silicon, silicon materials, for other by wide, the combination of narrow bandgap material is equally applicable.
A kind of manufacturing method of silicon carbide MOSFET device, comprising the following steps:
Step 1: choosing silicon carbide plate, that is, is used as subsequent silicon carbide N+substrate 2, silicon carbide N-epitaxial layer 3；
Step 2: by energetic ion injection technology, Al ion implantation is carried out, forms the area silicon carbide Pbase 7；Or by outer
The mode of prolonging forms the area silicon carbide Pbase 7, then forms the device behind the area silicon carbide Pbase 7；
Step 3: by photoetching, ion injecting process, carrying out phosphonium ion injection using NSD mask plate, formed silicon carbide N+
Source region 8；
Step 4: by photoetching, energetic ion injection process, Al ion implantation is carried out, forms silicon carbide depth P doped region 4；
Or by trench etch process, the groove of specified size is etched using Trench mask plate, and use extension, etching technics,
Form silicon carbide depth P doped region 4；
Step 5: by trench etch process, the groove of specified size is etched using Trench mask plate；
Step 6: by deposit and etching technics, in source, channel bottom deposits one layer of metal, forms Schottky contact metal
12, extra metal is removed by etching；
Step 7: by trench etch process, the gate groove of specified size is etched using Trench mask plate；
Step 8: gate dielectric layer 5 is formed by dry-oxygen oxidation technique；
Step 9: by deposit and etching technics, one layer of polysilicon is deposited in gate groove, polysilicon gate 6 is formed, passes through
Etching removes extra polysilicon；
Step 10: gate electrode 10 is formed by deposit, photoetching and etching technics；
Step 11: boron-phosphorosilicate glass BPSG11 is formed by deposit, photoetching and etching technics；
Step 12: source metal 9, drain metal 1 are formed by deposit, photoetching and etching technics respectively；So far, device
It completes.
Further, in step 6, the source trench schottky contact metal 12 deposited also can be replaced 13 material of polysilicon
Material；
Further, gate groove can also be initially formed, and after completing gate structure, re-form source groove；
Further, during step 5 etching groove, etching dynamics can be increased, to form broader groove；
Further, when step 5 forms source groove, etching dynamics can be increased, to form deeper etching groove.And
Be described below by step 4 replacement: by deposit, etching technics, in source, channel bottom deposits to form certain thickness oxide layer.
Etched technique forms the dielectric layer 15 that apparent height is lower than the area silicon carbide Pbase 7；
Further, after step 5 forms source groove, it can be further added by primary etching, formed not in former source channel bottom
Continuous groove.Secondarily etched trench depth is equal to 4 depth of silicon carbide depth P doped region；
Further, after step 5 forms source groove, it can be further added by primary etching, formed not in former source channel bottom
Continuous groove.Secondarily etched trench depth is less than 4 depth of silicon carbide depth P doped region；
Further, before step 4 forms silicon carbide depth P doped region 4, thus it is possible to vary mask parameters make rectangular under grid
At the silicon carbide depth P doped region 4 that convex is distributed, and in subsequent etching gate groove technique, by increasing etching dynamics, obtain more
Deep groove, and split-gate structure is formed in channel bottom, as shown in Figure 10；
Present invention is alternatively directed to Conventional silicon carbide UMOSFET to propose another improvement project.Specifically, the present invention passes through
On the basis of silicon carbide UMOSFET structure (as shown in Figure 1), groove is carried out by improving device architecture, and in specified region
Etching, deposit metal or polysilicon.The metal or polysilicon deposited is equally directly contacted with silicon carbide N-extension, and formation has
The Schottky contacts or Si/SiC heterojunction of rectification characteristic.When the material of deposit is metal, it is formed by contact, gesture
Building height can be adjusted by changing metal material, technology controlling and process and silicon carbide N-extension concentration, be ultimately formed lower
The Schottky contacts of conduction voltage drop (Von).Usual contact Von is in the range of 0.5V~1.8V.To realize positive work
Performance is internal integrated better than the Schottky diode of parasitic diode.Since the diode is how sub- device, Reverse recovery mistake
Since there is no few sub- storage in journey, there is faster reverse recovery time, lower reverse recovery loss and more anti-
To reliability is restored, compared with parasitic diode, there is more preferably Reverse recovery performance.The improvement is relative to external inverse parallel
The mode of one diode significantly reduces power electronic system volume, reduces packaging cost.Simultaneously because not having and two
Metal lead wire between pole pipe avoids metal lead wire bring ghost effect, to improve system application reliability.Together
When, relative to the mode of numerous monolithically integrated diodes in vivo, structure of the invention has more compact cell density.Integrated two
Cell density after pole pipe is identical with the double depth P doping MOSFET of silicon carbide, while not influencing MOSFET element basic performance.
Therefore structure of the invention advantage with good performance.When the material of deposit is polysilicon, it is formed by contact and is connect for hetero-junctions
Touching.Its characteristic is approximate with Schottky contacts: being all how sub- device, while also having rectification characteristic.Its forward conduction voltage drop Von is about
1V or so equally has optimised devices third quadrant working characteristics better than the parasitic diode characteristic of silicon carbide MOSFET
Good effect.Similarly, the improvement of the device there is effective optimization to make the basic performance of silicon carbide UMOSFET
With.
To achieve the above object, the invention adopts the following technical scheme:
The structure cell of a kind of silicon carbide MOSFET device, basic structure is as shown in figure 24, comprising: from bottom to top successively
The drain metal 1 of setting, silicon carbide N+Substrate 2 and silicon carbide N-Epitaxial layer 3；The silicon carbide N-3 top of epitaxial layer is right from a left side
It is respectively provided with the identical Schottky contact metal 12 of two depth, is had below left side Schottky contact metal 12 and schottky junctions
Touch the first silicon carbide depth P doped region 4 of same size of metal 12；12 lower section of right side Schottky contact metal, left side and lower left
With silicon carbide depth P doped region 4, the semiconductor surface is respectively provided with first grid structure, second grid structure from left to right
And third gate structure, 3 gate structures discontinuously arrange and depth is consistent, and 3 gate structure depth are all shallower than Schottky
Metal 12 is contacted, the gate structure includes gate dielectric layer 5, polysilicon gate 6 and gate electrode 10, and polysilicon gate 6 is situated between by grid
Matter layer 5 surrounds, and top is drawn by gate electrode 10, and 12 two sides of Schottky contact metal in left side are respectively first grid knot
Structure, second grid structure, respectively with the first table top knot between the Schottky contact metal 12 and the first, second gate structure in left side
Structure, the second mesa structure are separated by；There is third gate structure, the Xiao Te on right side on the right side of the Schottky contact metal 12 on the right side
It is separated by between base contact metal 12 and third gate structure with third mesa structure；3 mesa structure depth first are shallower than grid
Structure, is also shallower than Schottky contact metal 12, and 3 mesa structures include the area silicon carbide Pbase 7 and silicon carbide N+source region
The area 8, the silicon carbide Pbase 7 and silicon carbide N+source region 8 closely connect with gate structure and Schottky contact metal 12 respectively
Touching, the second grid structure right side and bottom part region are contacted with right side Schottky contact metal 12, the device surface
With one layer of source metal 9, the source metal 9 is mutually isolated by boron-phosphorosilicate glass BPSG11 with gate electrode 10.
It is preferred that carbofrax material Si, Ge, GaAs, GaN, diamond, SiGe, gallium oxide semiconductor material
Instead of.
It is preferred that 12 region of Schottky contact metal is now replaced into polysilicon 13, the two depth and width
It is completely the same.
It is preferred that it is medium that the silicon carbide depth P doped region 4 of 12 lower section of left side Schottky contact metal, which substitutes,
Layer 15, the two width and depth are completely the same.
It is preferred that second Schottky contact metal of right side 12 is with silicon carbide N-epitaxial layer 3 not only in groove
Side wall forms contact, while also contacting with the formation of silicon carbide N-epitaxial layer 3 in bottom part region.
It is preferred that 12 lower section of Schottky contact metal has discontinuous groove, trench depth etc. in Z-direction
In or less than the second Schottky contact metal of left side 12 silicon carbide depth P doped region 4 depth, trench interiors are with Schottky contacts
The deposit filling of metal 12, channel bottom are silicon carbide N-epitaxial layer 3.
It is preferred that having the silicon carbide depth P doped region 4 in convex distribution, silicon carbide below the gate structure
The recess of deep P doped region 4 has Split-gate structure together with the bottom of gate structure entire in X-direction.
Further, a kind of silicon carbide MOSFET device, used in width, narrow bandgap material is not limited only to be carbonized
Silicon, silicon materials, for other by wide, the combination of narrow bandgap material is equally applicable.
A kind of manufacturing method of silicon carbide MOSFET device, comprising the following steps:
Step 1: choosing silicon carbide plate, that is, is used as subsequent silicon carbide N+substrate 2, silicon carbide N-epitaxial layer 3；Such as Figure 34 institute
Show；
Step 2: by energetic ion injection technology, carrying out Al ion implantation, forms the area silicon carbide Pbase 7, or by outer
The mode of prolonging forms the area silicon carbide Pbase 7；Device after forming the area silicon carbide Pbase 7 is as shown in figure 35；
Step 3: by photoetching, ion injecting process, carrying out phosphonium ion injection using NSD mask plate, formed silicon carbide N+
Source region 8；As shown in figure 36；
Step 4: by photoetching, energetic ion injection process, Al ion implantation is carried out, forms silicon carbide depth P doped region 4；
Or by trench etch process, the groove of specified size is etched using Trench mask plate, and use extension, etching technics,
Form silicon carbide depth P doped region 4；As shown in figure 37；
Step 5: by trench etch process, the first, second groove is etched using Trench mask plate；As shown in figure 38
(right from a left side in figure is respectively the first, second groove)；
Step 6: by deposit and etching technics, depositing one layer of metal in channel bottom, form Schottky contact metal 12,
Extra metal is removed by etching；As shown in figure 39；
Step 7: by trench etch process, the gate groove of specified size is etched using Trench mask plate；Such as Figure 40
It is shown；
Step 8: gate dielectric layer 5 is formed by dry-oxygen oxidation technique；As shown in figure 41；
Step 9: by deposit and etching technics, one layer of polysilicon is deposited in gate groove, polysilicon gate 6 is formed, passes through
Etching removes extra polysilicon；As shown in figure 42；
Step 10: gate electrode 10 is formed by deposit, photoetching and etching technics；As shown in figure 43.
Step 11: boron-phosphorosilicate glass BPSG11 is formed by deposit, photoetching and etching technics；As shown in figure 44.
Step 12: source metal 9, drain metal 1 are formed by deposit, photoetching and etching technics respectively；So far, device
It completes.As shown in figure 45.
Further, in step 6, the trench schottky contact metal 12 deposited can also be 13 material of polysilicon；
Further, gate groove can also be initially formed, and after completing gate structure, re-form source groove；
Further, during step 5 etching groove, etching dynamics can be increased, to form broader second groove (i.e.
It is deposited in step 6 and to form broader second Schottky contact metal 12)；
Further, when step 5 forms groove, etching dynamics can be increased, to form deeper first groove etching.
And it is described below for substituting step 4: by deposit, etching technics, depositing to form certain thickness oxygen in first groove bottom
Change layer.Etched technique forms the dielectric layer 15 that apparent height is lower than the area silicon carbide Pbase 7；
Further, after step 5 forms groove, it can be further added by primary etching, formed discontinuously in two channel bottoms
Groove.Secondarily etched trench depth is equal to 4 depth of silicon carbide depth P doped region；
Further, after step 5 forms groove, it can be further added by primary etching, formed discontinuously in two channel bottoms
Groove.Secondarily etched trench depth is less than 4 depth of silicon carbide depth P doped region；
Further, before step 4 forms silicon carbide depth P doped region 4, thus it is possible to vary mask parameters make rectangular under grid
At the silicon carbide depth P doped region 4 that convex is distributed, and in subsequent etching gate groove technique, by increasing etching dynamics, obtain more
Deep groove, and split-gate structure is formed in channel bottom, as shown in figure 32；
The principle of the invention set forth below.Silicon carbide MOSFET device is required to anti-with a diode in numerous applications
It is used in parallel.If not considering monolithically integrated in vivo, this purpose can achieve there are two types of mode.One is directly using carbonization
The parasitic silicon carbide PiN bis- that silicon MOSFET element silicon carbide p-type base area and silicon carbide N-epitaxial layer 3, silicon carbide N+substrate 2 are formed
Pole pipe.Parasitism silicon carbide PiN forward conduction voltage drop Von is commonly referred to be 3.1V, and great forward conduction voltage drop is for low pressure
Under power using totally unfavorable, device on-state loss will be increased significantly.Simultaneously as the device belongs to bipolar device,
The accumulation of few son will be generated because conductance modulation acts in on-state.Although the accumulation of few son can reduce on-state voltage drop in the on-state,
But for switching transient, it is especially off transient state, the turn-off time as caused by few sub- storage increases, turn-off power loss increases, anti-
The problems such as increasing to peak point current and turning off reliability decrease, causes the very poor reverse recovery characteristic of the parasitic diode.
Therefore for antiparallel diode, it should with low conduction voltage drop Von, the basic demand restored fastly；The second is by by device
The diode inverse parallel of part and device exterior uses.Although this method reached low conduction voltage drop Von, wanting substantially of restoring fastly
It asks, but this method causes production cost because of many factors such as device number increases, power system increases, cooling requirements promotions
The reduction of reliability after rising and metal connecting line increase, so that the selection of parallel connection outside diode and non-optimal.This also promotes
Other formation for realizing anti-paralleled diode method.The present invention passes through in Conventional silicon carbide UMOSFET structure (as shown in Figure 1)
On the basis of, by improving device architecture, near grid and the contact zone silicon carbide P+ is formed about silicon carbide depth P doped region, and
The processes such as etched near the contact zone former silicon carbide P+, deposit form the deposit of Schottky contact metal or polysilicon.It is described
Schottky contact metal or polysilicon are directly contacted with silicon carbide N-extension, ultimately form the Schottky contacts with rectification characteristic
Or heterojunction.Wherein, Schottky contacts are as shown in Figure 2；Heterojunction is as shown in Figure 3.
When institute's inventive structure is in MOSFET blocking work, since device pressure part is by silicon carbide depth P doped region 4 and carbon
SiClx N- epitaxial layer 3 provides, and the improvement of device improves Conventional silicon carbide UMOSFET pressure resistance, therefore proposed device architecture has
Higher resistance to voltage levels, simultaneously because the shielding action in the area silicon carbide P+, the electric leakage of Schottky contacts or heterojunction are able to
It is greatly reduced, while reducing component grid oxidizing layer electric field, to improve the permanent application reliability of device.When device is in just
When under to working condition, since the area silicon carbide P+ is to the promotion of device avalanche breakdown pressure resistance and to the protection of gate dielectric layer, device
JFET region doping can do more, so that reducing MOSFET ratio leads value, optimize break-over of device performance.Structure of the invention pair
There is great optimization function in the work of device third quadrant.When the material deposited is Schottky contact metal, institute above
The barrier height mentioned can be by adjusting the modes such as metal species, process conditions and silicon carbide N-extension, and forming Von is about
The Schottky contacts of 0.6V~2V；Simultaneously because the defencive function of silicon carbide depth P doped region 4, so that Schottky contacts interface is leaked
Electricity is smaller.It has been generally acknowledged that the Von of silicon carbide PiN diode is 3.1V or so.The insertion of Schottky barrier diode, substantially reduces
The lower on-state loss of device third quadrant work, while Schottky barrier diode belongs to how sub- device, since there is no lacking
Sub- storage effect, with shorter reverse recovery time, lower turn-off power loss, lower Reverse recovery peak point current, more
The reliability of device in good reversely restoring process；In addition, since Schottky barrier diode integrated in vivo is to device area
Almost without increase, make invention device there is compact cellular to arrange, to have bigger on state current.When what is deposited
When material is polysilicon, polysilicon and silicon carbide N-extension 3 are in source channel bottom side wall formation Si/SiC heterojunction.According to phase
Document report is closed, which equally has rectification characteristic.Its forward conduction voltage drop Von is about 1.1V.Equally relative to parasitism
Diode pair has in the work of device third quadrant is extremely improved effect.Simultaneously as it is similarly how sub- device, with Xiao Te
Based diode is similar, equally has splendid Reverse recovery performance；In order to promote device third quadrant working characteristics, the present invention is also
Increase 12 lateral dimension of Schottky contact metal in device architecture.The increase of the part is conducive to device third quadrant workability
The optimization of energy；To further increase device third quadrant working performance, institute's inventive structure also proposed another optimization structure.I.e.
By continuing etching source channel bottom, discontinuous groove structure is formed inside silicon carbide depth P doped region 4.The groove structure
Equally with Schottky contact metal 12 or the deposit filling of polysilicon 13.The depth of secondary etching groove is equal to or less than silicon carbide
Deep 4 depth of P doped region reaches the mesh of optimised devices third quadrant working performance to increase Schottky/heterojunction area
's.In order to optimize to device dynamic characteristic, the present invention also provides form discontinuous Split- in gate structure bottom
Gate structure, such as Figure 10, shown in Figure 11.The structure significantly reduces device gate-drain positive area, reduces device and opened
Necessary grid electric charge number improves devices switch speed to optimize devices switch characteristic in journey.It is described to be directed to carbonization
Second set of improvement project of silicon-carbon-silicon carbide UMOSFET, principle is identical as first set improvement project, therefore details are not described herein again.
In conclusion the invention has the benefit that
One, structure of the invention has been obviously improved the resistance to voltage levels of Conventional silicon carbide UMOSFET device, while significantly reducing grid
Dielectric layer maximum electric field, so that the permanent application reliability of device is improved；Reducing device ratio leads Ron.sp simultaneously；
Two, structure of the invention realizes the integrated of internal how sub- rectifying device, so that institute's invention device is in third quadrant work
Make section, relative to device inside parasitic diode, there is more preferably Reverse recovery performance, when including shorter Reverse recovery
Between, lower turn-off power loss, lower Reverse recovery peak point current, more preferably in reversely restoring process device reliability.Institute
Integrated how sub- rectifying device has the characteristics that electric leakage is low；
Three, relative to the mode of external anti-paralleled diode, structure of the invention reduces metal lead wire interconnection quantity, reduces
System parasitic inductance；System device number is reduced, system bulk is reduced；Reduce the requirement to cooling system volume；
Packaging cost is reduced simultaneously.Generally speaking, it while institute's inventive structure promotes device reliability, also reduces device and is applied to
This；
Four, there is structure of the invention compact cellular to arrange, relative to Conventional silicon carbide UMOSFET area almost without increasing
Add, so that device production cost further decreases；
Five, structure of the invention is compatible with Conventional silicon carbide UMOSFET device production process, has the characteristics that be readily produced.
Six, the present invention is while optimizing silicon carbide MOSFET device basic performance, also directed to device third quadrant work
Further optimization has been carried out as performance, has obtained more preferably MOSFET third quadrant application performance；
Seven, the present invention reduces device miller capacitance, to increase devices switch speed by reducing grid leak positive area
Degree, optimizes device dynamic performance.
Detailed description of the invention
Fig. 1 is Conventional silicon carbide UMOSFET device cellular structural schematic diagram；
Fig. 2 is the basic structure cell schematic diagram of a kind of silicon carbide MOSFET device that embodiment 1 provides；
Fig. 3 is the basic structure cell schematic diagram of a kind of silicon carbide MOSFET device that embodiment 2 provides；
Fig. 4 is the basic structure cell schematic diagram of a kind of silicon carbide MOSFET device that embodiment 3 provides；
Fig. 5 is the basic structure cell schematic diagram of a kind of silicon carbide MOSFET device that embodiment 4 provides；
Fig. 6 is the region 1 structure of embodiment " Region A " Z-direction schematic diagram；
Fig. 7 is the basic structure cell schematic diagram of a kind of silicon carbide MOSFET device that embodiment 5 provides；
Fig. 8 is the basic structure cell schematic diagram of a kind of silicon carbide MOSFET device that embodiment 6 provides；
Fig. 9 is a kind of its " Region B " region XZ of the basic structure cell of silicon carbide MOSFET device of the offer of embodiment 1
Floor map；
Figure 10 is the basic structure cell schematic diagram of a kind of silicon carbide MOSFET device that embodiment 7 provides；
Figure 11 is that certain explanation is made to embodiment 7；
Figure 12 is the silicon carbide substrates schematic diagram that the embodiment of the present invention 8 provides；
Figure 13 is the offer of the embodiment of the present invention 8 by ion implantation technology formation 7 schematic diagram of the area silicon carbide Pbase；
Figure 14 is the offer of the embodiment of the present invention 8 by processes such as photoetching, ion implantings, and NSD mask plate is utilized to carry out phosphorus
Ion implanting forms 8 schematic diagram of silicon carbide N+source region；
Figure 15 is the offer of the embodiment of the present invention 8 by photoetching, ion implantation technology, forms silicon carbide depth P doped region 4 and shows
It is intended to；
Figure 16 is the offer of the embodiment of the present invention 8 by trench etch process, is etched using Trench mask plate specified
The source groove schematic diagram of size；
Figure 17 is the offer of the embodiment of the present invention 8 by deposit and etching technics, and in source, channel bottom deposits one layer of metal,
Form 12 schematic diagram of Schottky contact metal；
Figure 18 is the offer of the embodiment of the present invention 8 by trench etch process, is etched using Trench mask plate specified
The gate groove schematic diagram of size；
Figure 19 is the offer of the embodiment of the present invention 8 by dry-oxygen oxidation technique formation 5 schematic diagram of gate dielectric layer；
Figure 20 is being illustrated by deposit, photoetching and etching technics formation polysilicon gate 6 for the offer of the embodiment of the present invention 8
Figure；
Figure 21 is the offer of the embodiment of the present invention 8 by deposit, photoetching and etching technics formation 10 schematic diagram of grid；
Figure 22 is the offer of the embodiment of the present invention 8 by deposit, photoetching and etching technics formation BPSG11 schematic diagram；
Figure 23 is forming source electrode 9 by deposit, photoetching and etching technics, draining and illustrate for the offer of the embodiment of the present invention 8
Figure.
Figure 24 is the basic structure cell schematic diagram of a kind of silicon carbide MOSFET device that embodiment 9 provides；
Figure 25 is the basic structure cell schematic diagram of a kind of silicon carbide MOSFET device that embodiment 10 provides；
Figure 26 is the basic structure cell schematic diagram of a kind of silicon carbide MOSFET device that embodiment 11 provides；
Figure 27 is the basic structure cell schematic diagram of a kind of silicon carbide MOSFET device that embodiment 12 provides；
Figure 28 is the region 9 structure of embodiment " Region A " Z-direction schematic diagram；
Figure 29 is the basic structure cell schematic diagram of a kind of silicon carbide MOSFET device that embodiment 13 provides；
Figure 30 is the basic structure cell schematic diagram of a kind of silicon carbide MOSFET device that embodiment 14 provides；
Figure 31 is a kind of its " Region B " region XZ of the basic structure cell of silicon carbide MOSFET device of the offer of embodiment 9
Floor map；
Figure 32 is the basic structure cell schematic diagram of a kind of silicon carbide MOSFET device that embodiment 15 provides；
Figure 33 is that certain explanation is made to embodiment 15；
Figure 34 is the silicon carbide substrates schematic diagram that the embodiment of the present invention 16 provides；
Figure 35 is the offer of the embodiment of the present invention 16 by ion implantation technology formation 7 schematic diagram of the area silicon carbide Pbase；
Figure 36 is the offer of the embodiment of the present invention 16 by processes such as photoetching, ion implantings, and NSD mask plate is utilized to carry out phosphorus
Ion implanting forms 8 schematic diagram of silicon carbide N+source region；
Figure 37 is the offer of the embodiment of the present invention 16 by photoetching, ion implantation technology, forms the double depth P doped regions of silicon carbide
4 schematic diagrames；
Figure 38 is the offer of the embodiment of the present invention 16 by trench etch process, is etched using Trench mask plate specified
The groove schematic diagram of size；
Figure 39 is the offer of the embodiment of the present invention 16 by deposit and etching technics, deposits one layer of metal in channel bottom,
Form 12 schematic diagram of Schottky contact metal；
Figure 40 is the offer of the embodiment of the present invention 16 by trench etch process, is etched using Trench mask plate specified
The gate groove schematic diagram of size；
Figure 41 is the offer of the embodiment of the present invention 16 by dry-oxygen oxidation technique formation 5 schematic diagram of gate dielectric layer；
Figure 42 is being illustrated by deposit, photoetching and etching technics formation polysilicon gate 6 for the offer of the embodiment of the present invention 16
Figure；
Figure 43 is the offer of the embodiment of the present invention 16 by deposit, photoetching and etching technics formation 10 schematic diagram of grid；
Figure 44 is the offer of the embodiment of the present invention 16 by deposit, photoetching and etching technics formation BPSG11 schematic diagram；
Figure 45 is being shown by deposit, photoetching and etching technics formation source electrode 9, drain electrode 1 for the offer of the embodiment of the present invention 16
It is intended to.
Label declaration used in attached drawing:
1 is drain metal, and 2 be silicon carbide N+substrate, and 3 be silicon carbide N-epitaxial layer, and 4 be silicon carbide depth P doped region, and 5 are
Gate dielectric layer, 6 be polysilicon gate, and 7 be the area silicon carbide Pbase, and 8 be silicon carbide N+source region, and 9 be source metal, and 10 be gate electrode,
11 be boron-phosphorosilicate glass BPSG, and 12 be Schottky contact metal, and 13 be polysilicon, and 14 be split-gate polysilicon, and 15 be Jie
Matter layer；16 be the contact zone silicon carbide P+.
Specific embodiment
Illustrate embodiments of the present invention below by way of specific specific example, those skilled in the art can be by this specification
Other advantages and efficacy of the present invention can be easily understood for disclosed content.The present invention can also pass through in addition different specific realities
The mode of applying is embodied or practiced, the various details in this specification can also based on different viewpoints and application, without departing from
Various modifications or alterations are carried out under spirit of the invention.
Below in conjunction with attached drawing, this part is by taking the silicon carbide MOSFET device of 1200V a kind of as an example, detailed description of the present invention
Technical solution, while the principle of the present invention and characteristic are described further.The given examples are served only to explain the present invention, not
For limiting the scope of the invention.
Embodiment 1:
The structure cell of a kind of silicon carbide MOSFET device, basic structure is as shown in Figure 2.Including successively setting from bottom to top
The drain metal 1 set, silicon carbide N+Substrate 2 and silicon carbide N-Epitaxial layer 3；The silicon carbide N-3 upper left side of epitaxial layer has source ditch
Slot, source groove are deposited with Schottky contact metal 12 and are filled；There is silicon carbide depth P doping below the Schottky contact metal 12
Area 4；The Schottky contact metal 12 and silicon carbide N-Epitaxial layer 3 is directly contacted in channel bottom side wall, and being formed has rectification
The Schottky contacts of characteristic, the silicon carbide N-3 upper right side of epitaxial layer has silicon carbide depth P doped region 4, depth and Schottky
The silicon carbide depth P doped region 4 for contacting 12 lower section of metal is identical；The silicon carbide N-The silicon carbide depth P in 3 upper right side of epitaxial layer is adulterated
The upper left side in area 4, silicon carbide N-There is gate structure above epitaxial layer 3；The gate structure includes gate dielectric layer 5, polysilicon
Grid 6 and gate electrode 10；Polysilicon gate 6 is surrounded by gate dielectric layer 5, and top is drawn by gate electrode 10, the gate structure
Bottom is not less than Schottky contact metal 12, has mesa structure on the right side of the gate structure left side, Schottky contact metal 12,
The mesa structure includes the area silicon carbide Pbase 7 and silicon carbide N+source region 8, and the silicon carbide N+source region 8 is located at silicon carbide
7 top of the area Pbase, 7 bottom of the area the silicon carbide Pbase is higher than gate structure bottom；Device surface is covered by one layer of source metal 9
Lid, the source metal are separated by with gate metal 10 by boron-phosphorosilicate glass BPSG11.Wherein, drain metal 1 with a thickness of 0.5 μm~
2 μm, width is 2~6 μm, and gate electrode 10 is with a thickness of 0.5 μm~2 μm, and width is 0.2~0.5 μm, and source metal 9 is with a thickness of 4 μm
~6 μm, width is 2~6 μm；For silicon carbide N+substrate 2 with a thickness of 1~3 μm, concentration is 1e18~1e19cm-3；Silicon carbide N-extension
3 with a thickness of 6~10 μm, and concentration is 1e15~1e16cm-3；For silicon carbide depth P doped region 4 with a thickness of 1~2 μm, width is 0.5~2 μ
M, concentration are 1e17~6e17cm-3；With a thickness of 0.3~0.8 μm, width is 0.5~1.1 μm in the area silicon carbide Pbase 7, and concentration is
6e16~4e17cm-3；For silicon carbide N+source region 8 with a thickness of 0.2~0.4 μm, width is 0.2~0.3 μm, concentration be 2e18~
1e19cm-3；Gate dielectric layer 5 is with a thickness of 20~70nm；For polysilicon gate 6 with a thickness of 0.4~1 μm, width is 0.4~1 μm.Schottky
Metal 12 is contacted with a thickness of 1~2 μm, width is 0.4~1.5 μm.A kind of silicon carbide MOSFET provided by the invention, by internal
Integrated Schottky contacts or heterojunction also optimize device third while realizing optimization to device basic performance
Quadrant jobs performance reduces power system application cost.
Embodiment 2:
The present embodiment makes modification to a certain extent for embodiment 1, and structure is roughly the same with embodiment 1, different
Place is that used 12 region of Schottky contact metal is with the replacement of polysilicon 13, as shown in Figure 3.Equally in source trench bottom
Portion's side wall and silicon carbide N-epitaxial layer 3 form the Si/SiC heterojunction structure with rectifying contact.The positive guide of the heterojunction structure
Logical pressure drop Von is about 1.1V, equally has biggish castering action for the work of device third quadrant.Simultaneously as this is heterogeneous
Knot belongs to how sub- device, so that diode has good Reverse recovery performance.
Embodiment 3:
This embodiment differs from embodiment 1 in that the Schottky contact metal 12 has bigger lateral dimension,
It is as shown in Figure 4: to exceed the right margin of silicon carbide depth P doped region 4 on the right side of the Schottky contact metal 12, not only in bottom sidewall
It is contacted with silicon carbide N-epitaxial layer 3, bottom part region is contacted with silicon carbide N-epitaxial layer 3 simultaneously.Bigger schottky junctions
12 width of metal is touched, schottky junction contact area is increased, there is further meaning for the optimization of device third quadrant.
Embodiment 4:
This embodiment differs from embodiment 1 in that the silicon carbide depth P doped region of 12 lower section of spy's base contact metal
4 regions are with the replacement of dielectric layer 15, as shown in figure 5, the dielectric layer and 12 lower section silicon carbide depth P doped region of Schottky contact metal
4 is in the same size.The introducing of dielectric layer 15, for device surface structure, including gate structure and Schottky contact structure, Si/
SiC heterojunction structure has good protective effect.
Embodiment 5:
This embodiment differs from embodiment 1 in that the source beneath trenches have discontinuous groove in Z-direction,
Its trench depth is equal to 4 depth of the first silicon carbide depth P doped region, and trench interiors are filled with Schottky contact metal 12, groove
Bottom is silicon carbide N-Epitaxial layer 3, as shown in Figure 7.1 source beneath trenches structure " Region A " region Z-direction such as Fig. 6 of embodiment
It is shown.Relative to embodiment 1, the present embodiment optimizes the on state current density when work of device third quadrant.
Embodiment 6:
The present embodiment makes modification to a certain extent for embodiment 5, and structure is roughly the same with embodiment 5, different
Place is that trench depth is less than 4 depth of the first silicon carbide depth P doped region, as shown in Figure 8.For embodiment 5,
The present embodiment has the electric leakage under lower blocking state, so that the diode of insertion has more preferably reliability.
Embodiment 7:
Its structure of the present embodiment is roughly the same with embodiment 1, the difference is that, have below the gate structure in convex
The silicon carbide depth P doped region 4 of type distribution, and the recess of silicon carbide depth P doped region 4 is together with gate structure entire in X-direction
Bottom has Split-gate structure.As shown in Figure 10.Which significantly reduces device gate-drain positive area, to reduce
Miller capacitance improves device turn-off speed, optimizes device dynamic characteristic.Wherein, " Region B " XZ plane of embodiment 1
Schematic diagram is as shown in figure 9, Split-gate structure X/Y plane schematic diagram is as shown in figure 11；
Embodiment 8:
The present embodiment is equally by taking the silicon carbide MOSFET device manufacturing method of 1200V as an example, to above-mentioned 1~7 embodiment
Specific implementation is illustrated, and according to common sense in the field, can prepare the device of different performance parameter according to actual needs.
Step 1: choosing the silicon carbide plate of suitable resistivity and thickness, that is, is used as subsequent silicon carbide N+substrate 2, silicon carbide
N- epitaxial layer 3, as shown in figure 12.Wherein, for silicon carbide N+substrate 2 with a thickness of 1~3 μm, concentration is 1e18~1e19cm-3；Carbonization
For silicon N- epitaxial layer 3 with a thickness of 6~10 μm, concentration is 1e15~1e16cm-3；
Step 2: by energetic ion injection technology, Implantation Energy is about 1500~1900keV, carries out Al ion implantation,
Form the area silicon carbide Pbase 7.The step can also be formed by extensional mode with a thickness of 0.3~0.8 μm, and width is 0.5~
1.1 μm, concentration is 6e16~4e17cm-3The area silicon carbide Pbase 7.Device after forming the area silicon carbide Pbase 7 is as shown in figure 13；
Step 3: by processes such as photoetching, ion implantings, phosphonium ion injection is carried out using NSD mask plate, Implantation Energy is about
For 1300~1700keV.With a thickness of 0.2~0.4 μm, width is 0.2~0.3 μm, and concentration is 2e18~1e19cm-3Formation carbon
SiClx N+ source region 8, as shown in figure 14；
Step 4: by processes such as photoetching, ion implantings, carrying out Al ion implantation, and Implantation Energy is 1700~2000keV,
It is formed with a thickness of 1~2 μm, width is 0.5~2 μm, and concentration is 1e17~6e17cm-3Silicon carbide depth P doped region 4.Such as Figure 15
It is shown.The technique can also form silicon carbide depth P doped region 4 by etching, epitaxy technique；
Step 5: by trench etch process, being etched using Trench mask plate with a thickness of 1~2 μm, and width is 0.4~
1.5 μm of source groove, as shown in figure 16；
Step 6: by deposit and etching technics, in source, channel bottom deposits one layer of metal, is formed with a thickness of 1~2 μm, wide
The Schottky contact metal 12 that degree is 0.4~1.5 μm removes extra metal by etching.As shown in figure 17；
Step 7: it by trench etch process, is etched using Trench mask plate with a thickness of 0.4~1 μm, width 0.4
~1 μm of gate groove, as shown in figure 18；
Step 8: about 1000 DEG C~1400 DEG C at a temperature of, by dry-oxygen oxidation technique formed with a thickness of 20~70nm's
Gate dielectric layer 5, as shown in figure 19；
Step 9: by deposit and etching technics, depositing one layer of polysilicon in gate groove, is formed with a thickness of 0.4~1 μm,
The polysilicon gate 6 that width is 0.4~1 μm removes extra polysilicon by etching.As shown in figure 20；
Step 10: it is formed by deposit, photoetching and etching technics with a thickness of 0.5 μm~2 μm, width is 0.2~0.4 μm
Gate electrode 10, as shown in figure 21.
Step 11: boron-phosphorosilicate glass BPSG11 is formed by deposit, photoetching and etching technics, as shown in figure 22.
Step 12: it is formed respectively by deposit, photoetching and etching technics with a thickness of 4 μm~6 μm, width is 2~6 μm
Source metal 9, with a thickness of 0.5 μm~2 μm, drain metal 1 that width is 2~6 μm.So far, element manufacturing is completed, such as Figure 23 institute
Show.
Further, the polysilicon 13 deposited in step 9, either N-type polycrystalline silicon, is also possible to p-type polycrystalline
Silicon；
Further, gate groove can also be initially formed, and after completing gate structure technique, re-form source groove；
Further, in step 6, the source trench schottky contact metal 12 deposited also can be replaced 13 material of polysilicon
Material；The polysilicon is same either N-type polycrystalline silicon, is also possible to p-type polysilicon；
Further, when step 5 etches source groove, etching width can be increased, make step 6 deposit Schottky contacts gold
Belong to or when polysilicon, not only the channel bottom side wall in source is epitaxially formed with silicon carbide N-and contacts the material deposited, while in source
Channel bottom partial region, which is also epitaxially formed with silicon carbide N-, to be contacted；
Further, when step 5 forms source groove, etching dynamics can be increased, to form deeper etching groove.And
Step 4 is substituted for following technique: by deposit, etching technics, in source, channel bottom deposits to be formed with a thickness of with a thickness of 1~2 μ
The oxide layer of m.Etched technique forms the dielectric layer 15 that apparent height is lower than the area silicon carbide Pbase 7；
Further, after step 5 forms source groove, it can be further added by primary etching, formed not in former source channel bottom
Continuous groove.Secondarily etched trench depth is equal to 4 depth of silicon carbide depth P doped region formed in the later period, i.e., with a thickness of 1~2 μ
m；
Further, after step 5 forms source groove, it can be further added by primary etching, formed not in former source channel bottom
Continuous groove.Secondarily etched trench depth is less than 4 depth of silicon carbide depth P doped region formed in the later period, i.e. thickness is most slight
In 1um, maximum is less than 2um；
Further, before step 4 forms silicon carbide depth P doped region 4, thus it is possible to vary mask parameters make rectangular under grid
At the silicon carbide depth P doped region 4 that convex is distributed, and in subsequent etching gate groove technique, by increasing etching dynamics, obtain more
Deep groove, and split-gate structure is formed in channel bottom, as shown in Figure 10；
Embodiment 9:
The structure cell of a kind of silicon carbide MOSFET device, basic structure is as shown in figure 24, comprising: from bottom to top successively
The drain metal 1 of setting, silicon carbide N+Substrate 2 and silicon carbide N-Epitaxial layer 3；The silicon carbide N-3 top of epitaxial layer is right from a left side
It is respectively provided with the identical Schottky contact metal 12 of two depth, is had below left side Schottky contact metal 12 and schottky junctions
Touch the first silicon carbide depth P doped region 4 of same size of metal 12；12 lower section of right side Schottky contact metal, left side and lower left
With silicon carbide depth P doped region 4, the semiconductor surface is respectively provided with first grid structure, second grid structure from left to right
And third gate structure, 3 gate structures discontinuously arrange and depth is consistent, and 3 gate structure depth are all shallower than Schottky
Metal 12 is contacted, the gate structure includes gate dielectric layer 5, polysilicon gate 6 and gate electrode 10, and polysilicon gate 6 is situated between by grid
Matter layer 5 surrounds, and top is drawn by gate electrode 10, and 12 two sides of Schottky contact metal in left side are respectively first grid knot
Structure, second grid structure, respectively with the first table top knot between the Schottky contact metal 12 and the first, second gate structure in left side
Structure, the second mesa structure are separated by；There is third gate structure, the Xiao Te on right side on the right side of the Schottky contact metal 12 on the right side
It is separated by between base contact metal 12 and third gate structure with third mesa structure；3 mesa structure depth first are shallower than grid
Structure, is also shallower than Schottky contact metal 12, and 3 mesa structures include the area silicon carbide Pbase 7 and silicon carbide N+source region
The area 8, the silicon carbide Pbase 7 and silicon carbide N+source region 8 closely connect with gate structure and Schottky contact metal 12 respectively
Touching, the second grid structure right side and bottom part region are contacted with right side Schottky contact metal 12, the device surface
With one layer of source metal 9, the source metal 9 is mutually isolated by boron-phosphorosilicate glass BPSG11 with gate electrode 10.Wherein, it leaks
For pole metal 1 with a thickness of 0.5 μm~2 μm, width is 4~12 μm, gate metal 10 with a thickness of 0.5 μm~2 μm, width is 0.2~
0.5 μm, for source metal 9 with a thickness of 4 μm~6 μm, width is 4~12 μm；With a thickness of 1~3 μm, concentration is silicon carbide N+substrate 2
1e18~1e19cm-3；For silicon carbide N-epitaxial layer 3 with a thickness of 6~10 μm, concentration is 1e15~1e16cm-3；Silicon carbide depth P doping
With a thickness of 1~2 μm, width is 0.5~2 μm in area 4, and concentration is 1e17~6e17cm-3；The area silicon carbide Pbase 7 with a thickness of 0.3~
0.8 μm, width is 0.5~1.1 μm, and concentration is 6e16~4e17cm-3；Silicon carbide N+source region 8 is with a thickness of 0.2~0.4 μm, width
It is 0.2~0.3 μm, concentration is 2e18~1e19cm-3；Gate dielectric layer 5 is with a thickness of 20~80nm；Polysilicon gate 6 with a thickness of 0.4~
1 μm, width is 0.4~1 μm.For Schottky contact metal 12 with a thickness of 1~2 μm, width is 0.4~1.5 μm.It is provided by the invention
A kind of silicon carbide MOSFET is having the same of certain optimization function to device basic performance by internal integrated diode functional block
When, good optimization function also is played to device third quadrant workability.
Embodiment 10:
The present embodiment makes modification to a certain extent for embodiment 9, and structure is roughly the same with embodiment 9, different
Place is that used Schottky contact metal 12 is with the replacement of polysilicon 13, as shown in figure 25.Equally in Schottky contacts gold
Belong to 12 bottom sidewalls and silicon carbide N-epitaxial layer 3 forms the Si/SiC heterojunction structure with rectifying contact.The heterojunction structure
Forward conduction voltage drop Von is about 1V, equally has biggish castering action for the work of device third quadrant.Simultaneously as should
Hetero-junctions belongs to how sub- device, so that diode has good Reverse recovery performance.
Embodiment 11:
The present embodiment difference from Example 9 is that the first silicon carbide depth P doped region 4 is replaced with dielectric layer 15,
As shown in figure 26.The introducing of dielectric layer 15, for device surface structure, including gate structure and Schottky contact structure, Si/
SiC heterojunction structure has good protective effect.
Embodiment 12:
The present embodiment difference from Example 9 is that second Schottky contact metal 12 has bigger transverse direction
Size, as shown in figure 27, second Schottky contact metal of right side 12 is with silicon carbide N-epitaxial layer 3 not only in trenched side-wall shape
It is also contacted with the formation of silicon carbide N-epitaxial layer 3 at contact, while in bottom part region, bigger Schottky contact metal 12 is wide
Degree, increases schottky junction contact area, has further meaning for the optimization of device third quadrant.
Embodiment 13:
The present embodiment difference from Example 9 is: 12 lower section of Schottky contact metal has discontinuous in Z-direction
Groove, trench depth are equal to or less than the depth of the silicon carbide depth P doped region 4 of the second Schottky contact metal of left side 12, ditch
It is deposited and is filled with Schottky contact metal 12 inside slot, channel bottom is silicon carbide N-epitaxial layer 3, as shown in figure 29.Embodiment 9
12 rectangular structure of Schottky contact metal is as shown in figure 28.Relative to embodiment 9, the present embodiment optimizes device third quadrant work
On state current density when making.
Embodiment 14:
The present embodiment makes modification to a certain extent for embodiment 13, and structure is roughly the same with embodiment 13, no
It is with place, trench depth is less than the depth of the silicon carbide depth P doped region 4 of the second Schottky contact metal of left side 12, such as
Shown in Figure 30.For embodiment 13, the present embodiment has the electric leakage under lower blocking state, so that the diode of insertion
With performance of more preferably leaking electricity.
Embodiment 15:
The present embodiment is roughly the same with embodiment 9, the difference is that, there is the carbon in convex distribution below gate structure
The recess of SiClx depth P doped region 4, silicon carbide depth P doped region 4 has Split- together with the bottom of gate structure entire in X-direction
Gate structure, as shown in figure 32.The region embodiment 9 " Region B " XZ plane is as shown in figure 31, the XY of Split-gate structure
Plane is as shown in figure 33.Which significantly reduces device gate-drain positive area, to reduce miller capacitance, improves device
Turn-off speed optimizes device dynamic characteristic.
Embodiment 16:
The present embodiment is equally by taking the silicon carbide MOSFET device manufacturing method of 1200V as an example, to above-mentioned 9~15 embodiment
Specific implementation is illustrated, and according to common sense in the field, can prepare the device of different performance parameter according to actual needs.
Step 1: choosing the silicon carbide plate of suitable resistivity and thickness, that is, is used as subsequent silicon carbide N+substrate 2, silicon carbide
N- epitaxial layer 3, as shown in figure 31.Wherein, for silicon carbide N+substrate 2 with a thickness of 1~3 μm, concentration is 1e18~1e19cm-3；Carbonization
For silicon N- epitaxial layer 3 with a thickness of 6~10 μm, concentration is 1e15~1e16cm-3；
Step 2: by energetic ion injection technology, Implantation Energy is about 1500~2000keV, carries out Al ion implantation,
Form the area silicon carbide Pbase 7.The step can also be formed by extensional mode with a thickness of 0.3~0.8 μm, and width is 0.5~
1.1 μm, concentration is 6e16~4e17cm-3The area silicon carbide Pbase 7.Device after forming the area silicon carbide Pbase 7 is as shown in figure 32；
Step 3: by processes such as photoetching, ion implantings, phosphonium ion injection is carried out using NSD mask plate, Implantation Energy is about
For 1300~1700keV.With a thickness of 0.2~0.4 μm, width is 0.2~0.3 μm, and concentration is 2e18~1e19cm-3Formation carbon
SiClx N+ source region 8, as shown in figure 33；
Step 4: by processes such as photoetching, ion implantings, carrying out Al ion implantation, and Implantation Energy is 1700~2000keV,
It is formed with a thickness of 1~2 μm, width is 0.5~2 μm, and concentration is 1e17~6e17cm-3Silicon carbide depth P doped region 4.Such as Figure 34
It is shown.The technique can also form silicon carbide depth P doped region 4 by etching, epitaxy technique；
Step 5: by trench etch process, being etched using Trench mask plate with a thickness of 1~2 μm, and width is 0.4~
1.5 μm of double grooves, as shown in figure 35；
Step 6: by deposit and etching technics, depositing one layer of metal in double channel bottoms, formed with a thickness of 1~2 μm, wide
The Schottky contact metal 12 that degree is 0.4~1.5 μm removes extra metal by etching.As shown in figure 36；
Step 7: it by trench etch process, is etched using Trench mask plate with a thickness of 0.4~1 μm, width 0.4
~1 μm of gate groove, as shown in figure 37；
Step 8: about 1000 DEG C~1400 DEG C at a temperature of, by dry-oxygen oxidation technique formed with a thickness of 20~80nm's
Gate dielectric layer 5, as shown in figure 38；
Step 9: by deposit and etching technics, depositing one layer of polysilicon in gate groove, is formed with a thickness of 0.4~1 μm,
The polysilicon gate 6 that width is 0.4~1 μm removes extra polysilicon by etching.As shown in figure 39；
Step 10: it is formed by deposit, photoetching and etching technics with a thickness of 0.5 μm~2 μm, width is 0.2~0.4 μm
Gate electrode 10, as shown in figure 40.
Step 11: boron-phosphorosilicate glass BPSG11 is formed by deposit, photoetching and etching technics, as shown in figure 41.
Step 12: it is formed respectively by deposit, photoetching and etching technics with a thickness of 4 μm~6 μm, width is 4~12 μm
Source metal 9, with a thickness of 0.5 μm~2 μm, drain metal 1 that width is 4~12 μm.So far, element manufacturing is completed, and is such as schemed
Shown in 42.
Further, the polysilicon 13 deposited in step 9, either N-type polycrystalline silicon, is also possible to p-type polycrystalline
Silicon；
Further, gate groove can also be initially formed, and after completing gate structure, re-form source groove；
Further, in step 6, the Schottky contact metal 12 deposited also can be replaced 13 material of polysilicon；This is more
Crystal silicon is same either N-type polycrystalline silicon, is also possible to p-type polysilicon；
Further, it in step 5 etching groove, can etch in two times.It is bigger using dynamics when etching second trenches
Etching groove when making step 6 deposit Schottky contact metal or polysilicon, formed sediment with formation width bigger second groove
Long-pending material is not only epitaxially formed with silicon carbide N-in second groove bottom sidewall and contacts, while in second groove base portion subregion
Domain is also epitaxially formed with silicon carbide N-and contacts；
Further, it when step 5 forms groove, can etch in two times.When etching first groove, etching can be increased
Dynamics, to form deeper etching groove；Etching second trenches do not change then.Step 4 is substituted for following technique simultaneously: logical
Deposit, etching technics are crossed, deposits the oxide layer to be formed with a thickness of with a thickness of 1~2 μm in first groove bottom.Etched technique shape
It is lower than the dielectric layer 15 in the area silicon carbide Pbase 7 at apparent height；
Further, after step 5 forms groove, it can be further added by primary etching, formed in channel bottom discontinuous
Groove.Secondarily etched trench depth is equal to 4 depth of silicon carbide depth P doped region formed in the later period, i.e., with a thickness of 1~2 μm；
Further, after step 5 forms groove, it can be further added by primary etching, formed in channel bottom discontinuous
Groove.Secondarily etched trench depth is less than 4 depth of silicon carbide depth P doped region formed in the later period, i.e. thickness minimum is less than 1um,
Maximum is less than 2um；
Further, before step 4 forms silicon carbide depth P doped region 4, thus it is possible to vary mask parameters make rectangular under grid
At the silicon carbide depth P doped region 4 that convex is distributed, and in subsequent etching gate groove technique, by increasing etching dynamics, obtain more
Deep groove, and split-gate structure is formed in channel bottom, as shown in figure 32；
Need to declare simultaneously: this field engineers and technicians are according to this field basic knowledge it is recognised that the present invention
In a kind of silicon carbide power MOSFET element structure, p-type polysilicon used can also be realized using N-type polycrystalline silicon,
It can also be realized by p type single crystal silicon, can also be realized certainly by n type single crystal silicon；Dielectric material used is in addition to that can use two
Silica (SiO2) realize, it can also be by using silicon nitride (Si3N4), hafnium oxide (HfO2), aluminum oxide (Al2O3) contour
K dielectric material is realized；The carbofrax material can also use gallium nitride, and the wide-band gap materials such as diamond replace.Meanwhile manufacturing work
The specific embodiment of skill can also be adjusted according to actual needs.
The above-described embodiments merely illustrate the principles and effects of the present invention, and is not intended to limit the present invention.It is any ripe
The personage for knowing this technology all without departing from the spirit and scope of the present invention, carries out modifications and changes to above-described embodiment.Cause
This, all those of ordinary skill in the art are completed without departing from the spirit and technical ideas disclosed in the present invention
All equivalent modifications or change, should be covered by the claims of the present invention.
Claims (10)
1. a kind of silicon carbide MOSFET device, it is characterised in that: including set gradually from bottom to top drain metal (1), carbonization
Silicon N+Substrate (2) and silicon carbide N-Epitaxial layer (3)；The silicon carbide N-Epitaxial layer (3) upper left side have active groove, source groove with
Schottky contact metal (12) deposit filling；There is silicon carbide depth P doped region (4) below the Schottky contact metal (12)；
The Schottky contact metal (12) and silicon carbide N-Epitaxial layer (3) is directly contacted in channel bottom side wall, and being formed has rectification
The Schottky contacts of characteristic, the silicon carbide N-Epitaxial layer (3) upper right side has silicon carbide depth P doped region (4), depth and Xiao
The silicon carbide depth P doped region (4) that Te Ji is contacted below metal (12) is identical；The silicon carbide N-The carbon in epitaxial layer (3) upper right side
The upper left side of SiClx depth P doped region (4), silicon carbide N-There is gate structure above epitaxial layer (3)；The gate structure includes grid
Dielectric layer (5), polysilicon gate (6) and gate electrode (10)；Polysilicon gate (6) is surrounded by gate dielectric layer (5), and top passes through grid
Electrode (10) is drawn, and the gate structure bottom is not less than Schottky contact metal (12), the gate structure left side, Schottky
Contacting has mesa structure on the right side of metal (12), the mesa structure includes the area silicon carbide Pbase (7) and silicon carbide N+source region
(8), the silicon carbide N+source region (8) is located above the area silicon carbide Pbase (7), and the area the silicon carbide Pbase (7) bottom is higher than
Gate structure bottom；Device surface is covered by one layer of source metal (9), and the source metal and gate metal (10) are by boron phosphorus silicon
Glass BPSG (11) is separated by.
2. a kind of silicon carbide MOSFET device, structure cell includes: the drain metal (1) set gradually from bottom to top, carbonization
Silicon N+Substrate (2) and silicon carbide N-Epitaxial layer (3)；The silicon carbide N-Above epitaxial layer (3) from a left side and the right side is respectively provided with two depths
Identical Schottky contact metal (12) is spent, is had and Schottky contact metal (12) below left side Schottky contact metal (12)
First silicon carbide depth P doped region (4) of same size；Right side Schottky contact metal (12) lower section, left side and lower left have
Silicon carbide depth P doped region (4), the semiconductor surface be respectively provided with from left to right first grid structure, second grid structure with
And third gate structure, 3 gate structures discontinuously arrange and depth is consistent, and 3 gate structure depth are all shallower than schottky junctions
It touches metal (12), the gate structure includes gate dielectric layer (5), polysilicon gate (6) and gate electrode (10), polysilicon gate
(6) it is surrounded by gate dielectric layer (5), top is drawn by gate electrode (10), Schottky contact metal (12) two sides point in left side
Not Wei first grid structure, second grid structure, between the Schottky contact metal (12) in left side and the first, second gate structure
It is separated by respectively with the first mesa structure, the second mesa structure；There is third on the right side of the Schottky contact metal (12) on the right side
Gate structure is separated by between the Schottky contact metal (12) and third gate structure on right side with third mesa structure；3 table tops
Constructional depth first is shallower than gate structure, is also shallower than Schottky contact metal (12), and 3 mesa structures include silicon carbide
The area Pbase (7) and silicon carbide N+source region (8), the area the silicon carbide Pbase (7) and silicon carbide N+source region (8) respectively with grid knot
Structure and Schottky contact metal (12) are in close contact, on the right side of the second grid structure and bottom part region and right side Xiao Te
Base contacts metal (12) contact, and the device surface has one layer of source metal (9), the source metal (9) and gate electrode
(10) mutually isolated by boron-phosphorosilicate glass BPSG (11).
3. according to claim 1 or a kind of silicon carbide MOSFET device as claimed in claim 2, it is characterised in that: silicon carbide material
Material is replaced with Si, Ge, GaAs, GaN, diamond, SiGe, gallium oxide semiconductor material.
4. a kind of silicon carbide MOSFET device according to any one of claims 1 to 3, it is characterised in that: the Xiao Te
It is polysilicon (13) that base, which contacts metal (12) region,.
5. a kind of silicon carbide MOSFET device described in any one according to claim 1, it is characterised in that: the schottky junctions
The right margin for exceeding silicon carbide depth P doped region (4) on the right side of metal (12) is touched, not only in bottom sidewall and silicon carbide N-epitaxial layer
(3) it contacts, bottom part region is contacted with silicon carbide N-epitaxial layer (3) simultaneously.
6. a kind of silicon carbide MOSFET device according to claim 2 any one, it is characterised in that: the right side second
Schottky contact metal (12) is not only contacted in trenched side-wall formation with silicon carbide N-epitaxial layer (3), while in base portion subregion
Domain also forms with silicon carbide N-epitaxial layer (3) and contacts.
7. a kind of silicon carbide MOSFET device according to claim 1, it is characterised in that: the source beneath trenches are in the side Z
To with discontinuous groove, trench depth is less than or equal to first silicon carbide depth P doped region (4) depth, trench interiors tool
There is Schottky contact metal (12) filling, channel bottom is silicon carbide N-Epitaxial layer 3.
8. a kind of silicon carbide MOSFET device according to claim 1, it is characterised in that: have below the gate structure
In the silicon carbide depth P doped region (4) that convex is distributed, and the recess of silicon carbide depth P doped region (4) is together with grid entire in X-direction
The bottom of pole structure has Split-gate structure.
9. a kind of silicon carbide MOSFET device according to claim 2, it is characterised in that: have below the gate structure
In the silicon carbide depth P doped region (4) that convex is distributed, the recess of silicon carbide depth P doped region (4) is together with grid knot entire in X-direction
The bottom of structure has Split-gate structure.
10. a kind of manufacturing method of silicon carbide MOSFET device according to claim 1, which is characterized in that including following
Step:
Step 1: choosing silicon carbide plate, that is, is used as subsequent silicon carbide N+substrate (2), silicon carbide N-epitaxial layer (3)；
Step 2: by energetic ion injection technology, Al ion implantation is carried out, is formed the area silicon carbide Pbase (7)；Or pass through extension
Mode forms the area silicon carbide Pbase (7), then forms the device after the area silicon carbide Pbase (7)；
Step 3: by photoetching, ion injecting process, phosphonium ion injection is carried out using NSD mask plate, forms silicon carbide N+source region
(8)；
Step 4: by photoetching, energetic ion injection process, Al ion implantation is carried out, is formed silicon carbide depth P doped region (4)；Or
By trench etch process, the groove of specified size is etched using Trench mask plate, and uses extension, etching technics, shape
At silicon carbide depth P doped region (4)；
Step 5: by trench etch process, the groove of specified size is etched using Trench mask plate；
Step 6: by deposit and etching technics, in source, channel bottom deposits one layer of metal, is formed Schottky contact metal (12),
Extra metal is removed by etching；
Step 7: by trench etch process, the gate groove of specified size is etched using Trench mask plate；
Step 8: gate dielectric layer (5) are formed by dry-oxygen oxidation technique；
Step 9: by deposit and etching technics, one layer of polysilicon is deposited in gate groove, is formed polysilicon gate (6), passes through quarter
Etching off removes extra polysilicon；
Step 10: gate electrode (10) are formed by deposit, photoetching and etching technics；
Step 11: boron-phosphorosilicate glass BPSG (11) are formed by deposit, photoetching and etching technics；
Step 12: source metal (9), drain metal (1) are formed by deposit, photoetching and etching technics respectively；So far, device
It completes.
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Application publication date: 20190104 Assignee: Zhuhai Gree Electronic Components Co.,Ltd. Assignor: University of Electronic Science and Technology of China Contract record no.: X2023980042422 Denomination of invention: Silicon carbide MOSFET devices and their manufacturing methods Granted publication date: 20201113 License type: Common License Record date: 20230928 |