CN106024895A - Accumulating type shield grid MOSFET integrating schottky diodes - Google Patents
Accumulating type shield grid MOSFET integrating schottky diodes Download PDFInfo
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- CN106024895A CN106024895A CN201610481043.5A CN201610481043A CN106024895A CN 106024895 A CN106024895 A CN 106024895A CN 201610481043 A CN201610481043 A CN 201610481043A CN 106024895 A CN106024895 A CN 106024895A
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- 229920005591 polysilicon Polymers 0.000 claims abstract description 40
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 38
- 229910052751 metal Inorganic materials 0.000 claims abstract description 36
- 239000002184 metal Substances 0.000 claims abstract description 36
- 239000000758 substrate Substances 0.000 claims abstract description 7
- 238000009825 accumulation Methods 0.000 claims description 23
- 238000000034 method Methods 0.000 abstract description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 7
- 229910052710 silicon Inorganic materials 0.000 abstract description 7
- 239000010703 silicon Substances 0.000 abstract description 7
- 230000005684 electric field Effects 0.000 abstract description 3
- 239000004065 semiconductor Substances 0.000 abstract description 3
- 238000005516 engineering process Methods 0.000 abstract description 2
- 230000015556 catabolic process Effects 0.000 abstract 1
- 230000015572 biosynthetic process Effects 0.000 description 6
- 238000002360 preparation method Methods 0.000 description 4
- 230000005611 electricity Effects 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 238000000407 epitaxy Methods 0.000 description 2
- 238000001465 metallisation Methods 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 230000001360 synchronised effect Effects 0.000 description 2
- 238000000927 vapour-phase epitaxy Methods 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000000945 filler Substances 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 238000005036 potential barrier Methods 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000000992 sputter etching Methods 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7827—Vertical transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7803—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device
- H01L29/7806—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device the other device being a Schottky barrier diode
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
- H01L29/407—Recessed field plates, e.g. trench field plates, buried field plates
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/872—Schottky diodes
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Abstract
The invention belongs to semiconductor technology, and specifically relates to an accumulating type shield grid MOSFET integrating a schottky diode. A shield grid MOSFET area formed on a silicon substrate is separated from and adjacent to a schottky diode forming area. The accumulating type shield grid MOSFET has a shield grid structure, and the schottky diode has a groove structure identical to that of the shield grid MOSFET, and the schottky diode is filled in the top of the groove through source electrode metal to form a schottky contact on the side surface of the groove to reduce a chip occupied area. The forming process of the schottky diode is compatible with the forming process of MOSFET, thereby reducing process steps. When the schottky diode is reversely biased, an electric field exists between a polysilicon 7 in the groove 14 and N+ drift region 2, the N+ drift region 2 generates depletion, and the depletion area extends to the N+ drift region 2 until complete depletion. The breakdown of schottky junctions is prevented, and reverse current leakage of schottky diode is minimized.
Description
Technical field
The invention belongs to technical field of semiconductors, particularly to the accumulation type shield grid MOSFET of a kind of integrated schottky diode.
Background technology
Synchronous rectification in high performance converters design is most important for low-voltage, the application of high electric current, this is because by by Xiao
Special base rectification replaces with synchronous rectification MOSFET and can significantly improve efficiency and power density.In actual applications, synchronize whole
The power attenuation of stream MOSFET is mainly made up of conduction loss, switching loss and body diode conduction loss etc..Such as, exist
In DC-DC change-over circuit, in the power attenuation of the power switch on low limit, the conduction loss of body diode still affects MOSFET's
Overall loss.Along with power switch application medium-high frequency and the raising of the requirement of big electric current, the demand reducing power attenuation receives more
Carry out the most attention.
In order to reduce the power attenuation of power MOSFET body diode, use mode in parallel with Schottky diode for MOSFET,
Owing to the forward cut-in voltage (about 0.35V) of Schottky diode is less than the Built-in potential of PN junction diode (about 0.7V),
Therefore reduce body diode forward cut-in voltage, reduce the loss of body diode dead band.
In the MOSFET of traditional integrated schottky diode, source metal contacts formation Schottky diode, example with N-type drift region
Such as United States Patent (USP) No.6531, proposing in No. 102 patents, the doping content of drift region needs to be adjusted to and source metal shape
Become Schottky barrier.In order to obtain lower conducting resistance, 7400, No. 014 patent of US proposes a kind of accumulation type MOSFET collection
Become Schottky diode, as in figure 2 it is shown, drift zone resistance is minimized.But in this patent, Schottky diode is reverse-biased
Time leakage current relatively big, meanwhile, extra schottky trench 34 and groove 36 occupy bigger chip area, and processing step
Complex.
Summary of the invention
The purpose of the present invention, it is simply that in order to solve to leak electricity relatively greatly when Schottky diode is reverse-biased, and the problem that processing step is complicated,
Proposing the accumulation type shield grid MOSFET of a kind of integrated schottky diode, technique is relatively easy and is easily controlled, and also a saving
Chip area.
Technical scheme: the accumulation type shield grid MOSFET of a kind of integrated schottky diode, as it is shown in figure 1, include
MOSFET region 12 and schottky area 13；Described MOSFET region 12 and schottky area 13 all include the most successively
The first metal layer 11, N++ type heavy doping substrate 1, N+ type drift region 2, N-type doped region 3 and the second metal level that stacking is arranged
10；The N-type doped region 3 of described MOSFET region 12 has the first groove 5 and N+ type heavily doped region 4；Described N+ type is heavily doped
Upper surface and second metal level 10 in miscellaneous district 4 contact；Described first groove 5 is between N+ type heavily doped region 4, and the first groove 5
Lower end extend in N+ type drift region 2；Upper surface and second metal level 10 of described first groove 5 contact, described first groove 5
In be filled with medium 6, described first groove 5 also has the first polysilicon 7 and the second polysilicon 8, described first polysilicon 7 He
Second polysilicon 8 is respectively positioned in medium 6, and the second polysilicon 8 is positioned at the top of the first polysilicon 7；Described schottky area
Having the second groove 14 in the N-type doped region 3 of 13, the lower end of described second groove 14 extends in N+ type drift region 2；Described
Upper surface and second metal level 10 of two grooves 14 contact, and the top of the second groove 14 is filled with metal 9, the bottom of the second groove 14
It is filled with medium 6, and the junction depth of metal 9 is less than the junction depth of N-type doped region 3；Medium 6 in described second groove 14 has
First polysilicon 7；Described second metal level 10 is connected with source electrode, and described first polysilicon 7 is connected with source electrode, and described
Two polysilicons 8 are connected with gate electrode, and described the first metal layer 11 is connected with drain electrode；The doping of described N+ type drift region 2 is dense
Degree is less than two orders of magnitude of doping content of N++ type heavy doping substrate 1；The doping content of described N-type doped region 3 is less than N+
One to two orders of magnitude of the doping content of type drift region 2.
The technical scheme that the present invention is total, relative to traditional structure, the MOSFET of the present invention has shielded gate structure, reduces grid
Pole electric charge.Meanwhile, the conducting resistance of accumulation type MOSFET is less, and there is not the most sub-storage effect, improves switching speed；
Meanwhile, the formation process of Schottky diode is compatible with MOSFET formation process, decreases processing step.Meanwhile, it is positioned at Xiao Te
Polysilicon 7 below based diode is connected with source electrode, when Schottky diode turns on, forms accumulation in polysilicon 7 both sides
Layer, reduces the conduction voltage drop of Schottky diode.During Schottky diode reverse bias, polysilicon 7 and N+ type drift region it
Between there is electric field, N+ type drift region produces and exhausts, and depletion region extends in N+ type drift region, the most completely depleted, has protected Xiao
Puncturing of special base junction, reduces leakage current
Described medium 6 can be silicon dioxide, different at its thickness of diverse location.When being positioned at polysilicon 8 both sides, thickness is
5nn-100nm, the thickness between polysilicon 7 and polysilicon 8 is 200nm-400nm, between polysilicon 7 and metal level 9
Thickness be 200nm-400nm.
Further, described schottky area is separated with MOSFET region and adjacent.
The invention have the benefit that and improve switching speed, reduce the conduction voltage drop of Schottky diode, Schottky two pole
During pipe reverse bias, protect puncturing of schottky junction, reduced leakage current.
Accompanying drawing explanation
Fig. 1 is the structural representation of the accumulation type shield grid MOSFET of a kind of integrated schottky diode provided by the present invention；
Fig. 2 is the structural representation that the MOSFET of a kind of accumulation type that patent No. US 7400,014 provides combines Schottky diode；
Fig. 3 is that the accumulation type shield grid MOSFET of a kind of integrated schottky diode provided by the present invention leads at Schottky diode
Map of current time logical；
Fig. 4 is that the accumulation type shield grid MOSFET of a kind of integrated schottky diode provided by the present invention is anti-at Schottky diode
Time partially be positioned at schottky diode area N+ type drift region exhaust line chart；
Fig. 5 is the laying out pattern of the accumulation type shield grid MOSFET of a kind of integrated schottky diode provided by the present invention；
Fig. 6-9 is the work of the committed step of the accumulation type shield grid MOSFET of a kind of integrated schottky diode provided by the present invention
Process flow figure.
Detailed description of the invention
Below in conjunction with the accompanying drawings the present invention is described in detail.
The accumulation type shield grid MOSFET of a kind of integrated schottky diode of the present invention, as it is shown in figure 1, include MOSFET
Region 12 and schottky area 13；Described MOSFET region 12 and schottky area 13 all include stacking gradually from bottom to up and set
The first metal layer 11, N++ type heavy doping substrate 1, N+ type drift region 2, N-type doped region 3 and the second metal level 10 put；Institute
State and the N-type doped region 3 of MOSFET region 12 has the first groove 5 and N+ type heavily doped region 4；Described N+ type heavily doped region 4
Upper surface and the second metal level 10 contact；Described first groove 5 is between N+ type heavily doped region 4, and the first groove 5 times
End extends in N+ type drift region 2；Upper surface and second metal level 10 of described first groove 5 contact, in described first groove 5
It is filled with medium 6, described first groove 5 also has the first polysilicon 7 and the second polysilicon 8, described first polysilicon 7 and
Two polysilicons 8 are respectively positioned in medium 6, and the second polysilicon 8 is positioned at the top of the first polysilicon 7；Described schottky area 13
N-type doped region 3 in there is the second groove 14, the lower end of described second groove 14 extends in N+ type drift region 2；Described second
Upper surface and second metal level 10 of groove 14 contact, and the top of the second groove 14 is filled with metal 9, and the bottom of the second groove 14 is filled out
It is filled with medium 6, and the junction depth of metal 9 is less than the junction depth of N-type doped region 3；Medium 6 in described second groove 14 has
One polysilicon 7；Described second metal level 10 is connected with source electrode, and described first polysilicon 7 is connected with source electrode, and described second
Polysilicon 8 is connected with gate electrode, and described the first metal layer 11 is connected with drain electrode；The doping content of described N+ type drift region 2
Two orders of magnitude of doping content less than N++ type heavily doped region 1；The doping content of described N-type doped region 3 is floated less than N+ type
Move one to two orders of magnitude of doping content in district 2.
The operation principle of the present invention is:
The source electrode of the accumulation type shield grid MOSFET, described MOSFET of a kind of integrated schottky diode provided by the present invention is made
For the anode of Schottky diode, the drain electrode at the described MOSFET back side is as the negative electrode of Schottky diode.
During accumulation type MOSFET forward conduction, form one layer of thin electron accumulation layer in the N-drift region of groove 5 both sides, reduce
The forward conduction resistance of MOSFET；Now, the negative electrode of Schottky diode connects high potential relative to anode, and schottky junction is reverse-biased,
Schottky diode is in reverse blocking state.Polysilicon 7 in groove 14 is connected with source electrode, for zero potential, with N-drift region
Between there is transverse electric field, therefore, in N+ drift region, form depletion layer, and depletion layer is along with the increase of voltage is gradually to N-district body
Interior extension, the N-drift region between final groove 14 is completely depleted, has protected puncturing of schottky junction.Therefore the electricity between source and drain
When pressing relatively low, the schottky junction that metal level 9 is formed with N-doped region 3 undertakes pressure, when voltage between source and drain is higher, such as figure
Shown in 4, below schottky junction, N+ type drift region exhausts and bears pressure, when reducing Schottky diode reverse biased leakage electricity
Stream.
During the conducting of schottky junction diode forward, as it is shown on figure 3, its anode connects high potential relative to negative electrode, i.e. accumulation type MOSFET
Source electrode connect high potential relative to drain electrode.Schottky diode turns on, the Schottky formed between metal level 9 and N-doped region 3
Knot is in forward bias, and electronics is crossed potential barrier and entered metal interface from quasiconductor；Polysilicon 7 in groove 14 and source potential phase
Even, when source electrode connects high potential, form electron accumulation layer in groove 14 both sides, reduce Schottky diode forward conduction voltage drop,
Reduce the conduction loss of Schottky diode.
Fig. 5 show the domain of the accumulation type shield grid MOSFET of a kind of integrated schottky diode of the present invention, in domain
Include trench gate mosfet forms region and the formation region of Schottky diode, and area of grid is positioned at trench gate mosfet
Formation region in.As can be seen from Figure 5 MOSFET and Schottky diode adhere to the not same district on die on laying out pattern separately
Territory, the formation region of Schottky diode needs to occupy certain area, but compared to Fig. 2 decreases the region of source electrode field plate,
And the side of groove also serves as Schottky contact area, thus Schottky diode form the chip area energy shared by region
It is substantially reduced.
As a example by the structure shown in Fig. 1, present configuration can prepare using the following method, and processing step is:
1, monocrystal silicon prepares.Using N-type heavy doping monocrystalline substrate 1, crystal orientation is<100>.
2, epitaxial growth.Use method growth certain thickness and the N-type epitaxy layer of doping content such as vapour phase epitaxy VPE, formed
N+ type drift region 2.Continue epitaxial growth, form certain thickness and the N type doped region 3. of doping content
3, the preparation of N+ source region.Arsenic injects preparation N+ type heavily doped region 4.
4, groove 5 and groove 14 etch.The methods such as ion etching are used to etch the groove of certain depth and width in N-type epitaxy layer.
As shown in Figure 6, in N+ type drift region 2, the groove needed for accumulation type MOSFET and schottky junction is etched.
5, the preparation of shield grid electrode.First in whole silicon chip surface deposited oxide layer, certain thickness is then deposited
Polysilicon formed shield grid electrode, finally etch away the polysilicon of silicon chip surface.
6, the preparation of gate electrode.As shown in Figure 8, first in whole silicon chip surface deposited oxide layer, the oxygen in groove 14 is etched away
Change layer.Then depositing polysilicon in groove 5, photoetching, etching form gate electrode 7, finally, continue deposit oxygen at silicon chip surface
Change layer and carry out machinery and polish.
7, front-side metallization anode.Sputtering layer of metal aluminum at whole device surface, the filler metal while of in groove 14, with N-type
Doped region 3 forms Schottky contacts, finally carries out machinery and polishes, as shown in Figure 9.
8, thinning back side, metallization, forms drain electrode 11.
During making devices, can also be used with the semi-conducting materials such as carborundum, GaAs or germanium silicon and substitute body silicon.
Claims (2)
1. an accumulation type shield grid MOSFET for integrated schottky diode, including MOSFET region (12) and schottky region
Territory (13)；Described MOSFET region (12) and schottky area (13) all include first be cascading from bottom to up
Metal level (11), N++ type heavy doping substrate (1), N+ type drift region (2), N-type doped region (3) and the second metal level (10)；
The N-type doped region (3) of described MOSFET region (12) has the first groove (5) and N+ type heavily doped region (4)；Described
The upper surface of N+ type heavily doped region (4) and the second metal level (10) contact；Described first groove (5) is positioned at N+ type heavily doped region
(4) between, and the lower end of the first groove (5) extends in N+ type drift region (2)；The upper surface of described first groove (5) with
Second metal level (10) contacts, and is filled with medium (6) in described first groove (5), also has the in described first groove (5)
One polysilicon (7) and the second polysilicon (8), described first polysilicon (7) and the second polysilicon (8) are respectively positioned on medium (6)
In, and the second polysilicon (8) is positioned at the top of the first polysilicon (7)；The N-type doped region of described schottky area (13)
(3) having the second groove (14) in, the lower end of described second groove (14) extends in N+ type drift region (2)；Described second
The upper surface of groove (14) and the second metal level (10) contact, the top of the second groove (14) is filled with metal (9), the second groove
(14) under-filled has medium (6), and the junction depth of metal (9) is less than the junction depth of N-type doped region (3)；Described second
Medium (6) in groove (14) has the first polysilicon (7)；Described second metal level (10) is connected with source electrode, described
First polysilicon (7) is connected with source electrode, and described second polysilicon (8) is connected with gate electrode, described the first metal layer (11)
It is connected with drain electrode；The doping content of described N+ type drift region (2) doping content two less than N++ type heavy doping substrate (1)
The individual order of magnitude；The doping content of described N-type doped region (3) is less than doping content one to two number of N+ type drift region (2)
Magnitude.
The accumulation type shield grid MOSFET of a kind of integrated schottky diode the most according to claim 1, it is characterised in that
Described schottky area is separated with MOSFET region and adjacent.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610481043.5A CN106024895A (en) | 2016-06-27 | 2016-06-27 | Accumulating type shield grid MOSFET integrating schottky diodes |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610481043.5A CN106024895A (en) | 2016-06-27 | 2016-06-27 | Accumulating type shield grid MOSFET integrating schottky diodes |
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| CN110729345A (en) * | 2019-09-29 | 2020-01-24 | 东南大学 | Trench gate type silicon-on-insulator lateral insulated gate bipolar transistor device |
| CN111430345A (en) * | 2020-03-21 | 2020-07-17 | 上海韦尔半导体股份有限公司 | Shielding gate type MOSFET device, manufacturing method thereof and electronic product |
| CN114551586A (en) * | 2022-04-27 | 2022-05-27 | 成都蓉矽半导体有限公司 | Silicon carbide split gate MOSFET cell integrated with grid-controlled diode and preparation method |
| CN116110796A (en) * | 2023-04-17 | 2023-05-12 | 深圳平创半导体有限公司 | SBD integrated silicon carbide SGT-MOSFET and preparation method thereof |
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| CN117316979A (en) * | 2023-10-17 | 2023-12-29 | 深圳芯能半导体技术有限公司 | Deep-groove charge-shielding silicon carbide field effect transistor and preparation method thereof |
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