CN105810754B - A kind of metal-oxide-semiconductor diode with accumulation layer - Google Patents
A kind of metal-oxide-semiconductor diode with accumulation layer Download PDFInfo
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- CN105810754B CN105810754B CN201610394393.8A CN201610394393A CN105810754B CN 105810754 B CN105810754 B CN 105810754B CN 201610394393 A CN201610394393 A CN 201610394393A CN 105810754 B CN105810754 B CN 105810754B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 28
- 238000009825 accumulation Methods 0.000 title claims abstract description 26
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 15
- 229920005591 polysilicon Polymers 0.000 claims description 14
- 230000005611 electricity Effects 0.000 claims description 11
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 6
- 239000000758 substrate Substances 0.000 claims description 4
- 150000004767 nitrides Chemical class 0.000 claims description 3
- 239000000377 silicon dioxide Substances 0.000 claims description 3
- 230000003647 oxidation Effects 0.000 claims 1
- 238000007254 oxidation reaction Methods 0.000 claims 1
- 230000000903 blocking effect Effects 0.000 abstract description 9
- 230000005684 electric field Effects 0.000 abstract description 8
- 238000009826 distribution Methods 0.000 abstract description 5
- 238000010276 construction Methods 0.000 abstract description 2
- 238000005516 engineering process Methods 0.000 abstract description 2
- 238000010586 diagram Methods 0.000 description 7
- 238000000034 method Methods 0.000 description 4
- 230000004888 barrier function Effects 0.000 description 3
- 230000015556 catabolic process Effects 0.000 description 3
- 238000001465 metallisation Methods 0.000 description 3
- 230000008901 benefit Effects 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 238000000407 epitaxy Methods 0.000 description 2
- 239000007943 implant Substances 0.000 description 2
- 238000011084 recovery Methods 0.000 description 2
- 238000000927 vapour-phase epitaxy Methods 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 239000004411 aluminium Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 230000006698 induction Effects 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 230000005404 monopole Effects 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 238000000992 sputter etching Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
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Abstract
The present invention relates to semiconductor technology, in particular to a kind of metal-oxide-semiconductor diode with accumulation layer.The metal-oxide-semiconductor diode has surface electronic accumulation layer structure and technotron structure, can obtain lower cut-in voltage.Diode since the N-type semiconductor surface being in contact with slot 8 will form internal electron accumulation layer, while using the higher N-type region 3 of doping concentration, device made to have very low forward voltage drop after forward conduction.When device reverse blocking, transverse electric field is formed between N-type region 3 and DOPOS doped polycrystalline silicon 13, exhaust line therefore is extended into 3 body of N-type region, makes the field distribution of drift region in distributed rectangular, improves the reverse BV of device.Therefore, new construction proposed by the present invention has high voltage and low conducting voltage simultaneously.
Description
Technical field
The present invention relates to semiconductor technologies, particularly in a kind of metal-oxide-semiconductor diode with accumulation layer.
Background technique
Diode is one of most common electronic component, and traditional rectifier diode is mainly Schottky rectifier and PN junction
Rectifier.Wherein, PN junction diode is able to bear higher reverse BV, and stability is preferable, but its forward conduction pressure
Drop larger, reverse recovery time is longer.Schottky diode is the metal-semiconductor junction formed using metal and semiconductor contact
Principle production, on-state voltage drop is lower.Due to being monopole current-carrying subconductivity, Schottky diode is in forward conduction without surplus
Minority carrier accumulation, Reverse recovery is very fast.But the breakdown reverse voltage of Schottky diode is lower, reverse leakage current compared with
Greatly, temperature characterisitic is poor.
In order to improve the performance of diode, domestic and international researchers always strive to combine two pole of PN junction diode and Schottky
The advantages of pipe, proposes PiN diode, Junction Barrier Controlled rectifier JBS (JBS:Junction Barrier Schottky
Rectifier), MOS controls diode MCD (MCD:MOS Controlled Diode), trench MOS barrier Schottky diode
The devices such as TMBS (TMBS:Trench MOS Barrier Shcotty Diode).Patent " shallow slot MOS diode
(CN 102064201A) " proposes a kind of novel semiconductor diode device, combines electron accumulation layer and junction field
Pipe structure obtains low-down conduction voltage drop, substantially increases breakdown voltage and reduces leakage current.However, shallow slot
MOS diode is more subtype devices, the raising of reverse withstand voltage and forward conduction voltage drop as Schottky diode
Reduction there are contradictions, improve the reverse withstand voltage of device, it is necessary to which the thickness for increasing drift region, the doping for reducing drift region are dense
Degree, these factors can all increase forward conduction voltage drop, which has limited the device mesohigh application field application.
Summary of the invention
The purpose of the present invention, exactly the forward conduction pressure in order to solve shallow slot MOS diode in mesohigh field
Higher problem is dropped, makes device while guaranteeing higher reverse withstand voltage, realizes low forward conduction voltage drop.
Technical solution of the present invention: a kind of metal-oxide-semiconductor diode with accumulation layer, including from top to bottom according to
The secondary anode electrode 9 being stacked, N- doped region 4, N-type region 3, N-type heavy doping monocrystalline substrate 2 and cathode electrode 1；The sun
The both ends of pole electrode 9 are extended into vertically downward in N- doped region 4, between the part that N- doped region 4 and anode electrode 9 extend downwardly
With N-type heavily doped region 5；4 upper surface of N- doped region between the N-type heavily doped region 5 of two sides has planar gate structure, described flat
Face grid structure is located in anode electrode 1, and the planar gate structure includes gate oxide 10 and positioned at the more of 10 upper surface of oxide layer
Crystal silicon gate electrode 11,10 lower surface of oxide layer are contacted with 5 upper surface of part N-type heavily doped region；The anode electrode 9 extends downwardly
Partial lower section has the slot 8 and p-type heavily doped region 6 for being mutually juxtaposed setting, and the portion of upper surface and N-type of p-type heavily doped region 6
Heavily doped region 5 contacts；The slot 8 extends vertically into N-type region 3, and dielectric layer 12, the dielectric layer 12 are filled in the slot 8
In have polysilicon 13；There is p type buried layer 7, and p-type is buried between 3 upper surface of lower surface and N-type region of the p-type heavily doped region 6
The side of layer 7 is connect with slot 8.
The doping concentration of the p type buried layer 7 is greater than two orders of magnitude of doping concentration of N- doped region 4.The N-type region 3
Doping concentration is greater than one to two orders of magnitude of doping concentration of N- doped region 4.
The gate oxide 10 is thin gate oxide, with a thickness of 5nm-100nm.
Filled media layer 12 uses silica, nitride, high K dielectric in the slot, with a thickness of 200nm-500nm.
The invention has the benefit that there is surface electronic accumulation layer structure and junction field structure first, due to electricity
The gate oxide of sub- accumulation layer is very thin and the doping concentration of N- doped region 4 is lower, and diode can obtain lower unlatching electricity
Pressure；Diode is after forward conduction, since the N-type semiconductor surface being in contact with slot 8 will form internal electron accumulation layer, simultaneously
Using the higher N-type region 3 of doping concentration, make device that there is very low forward voltage drop.When device reverse blocking, N-type region 3 with mix
Transverse electric field is formed between miscellaneous polysilicon 13, exhaust line therefore is extended into 3 body of N-type region, makes the field distribution of drift region in square
Shape distribution improves the reverse blocking electricity of device；Therefore, new construction proposed by the present invention has high voltage and low electric conduction simultaneously
Pressure.
Detailed description of the invention
Fig. 1 is a kind of cross-section structure of the metal-oxide-semiconductor diode with accumulation layer provided by embodiment 1
Schematic diagram；
Fig. 2 is a kind of metal-oxide-semiconductor diode with accumulation layer provided by embodiment 1 in outer plus zero electricity
Line schematic diagram is exhausted when pressure；
Fig. 3 is a kind of metal-oxide-semiconductor diode with accumulation layer provided by embodiment 1 in applied voltage
When reaching cut-in voltage, line and current path schematic diagram are exhausted；
Fig. 4 is a kind of metal-oxide-semiconductor diode with accumulation layer provided by embodiment 1 outer plus reversed
Line schematic diagram and drift region longitudinal electric field distribution schematic diagram are exhausted when voltage；
Fig. 5 exhausts line when being patent " shallow slot MOS diode (CN 102064201A) " additional backward voltage and shows
It is intended to and drift region longitudinal electric field distribution schematic diagram；
Fig. 6 is a kind of cross-section structure of the metal-oxide-semiconductor diode with accumulation layer provided by embodiment 2
Schematic diagram.
Specific embodiment
The present invention is described in detail with reference to the accompanying drawing.
Diode of the invention has two coordination electrodes of cathode and anode.
Embodiment 1
As shown in Figure 1, the metal-oxide-semiconductor diode of this example, including the anode being cascading from top to bottom
Electrode 9, N- doped region 4, N-type region 3, N-type heavy doping monocrystalline substrate 2 and cathode electrode 1；It hangs down at the both ends of the anode electrode 9
It directly extends down into N- doped region 4, there is N-type heavily doped region between the part that N- doped region 4 and anode electrode 9 extend downwardly
5；4 upper surface of N- doped region between the N-type heavily doped region 5 of two sides has planar gate structure, and the planar gate structure is located at sun
In pole electrode 1, the planar gate structure includes gate oxide 10 and the polygate electrodes 11 positioned at 10 upper surface of oxide layer, oxygen
Change 10 lower surface of layer to contact with 5 upper surface of part N-type heavily doped region；The lower section of 9 downward extension portion of anode electrode has
It is mutually juxtaposed the slot 8 and p-type heavily doped region 6 of setting, and the portion of upper surface of p-type heavily doped region 6 is contacted with N-type heavily doped region 5；
The slot 8 extends vertically into N-type region 3, and dielectric layer 12 is filled in the slot 8, has polysilicon 13 in the dielectric layer 12；
There is p type buried layer 7, and the side of p type buried layer 7 and slot 8 between 3 upper surface of lower surface and N-type region of the p-type heavily doped region 6
Connection.
The doping concentration of the p type buried layer 7 is greater than two orders of magnitude of doping concentration of N- doped region 4.The N-type region 3
Doping concentration is greater than one to two orders of magnitude of doping concentration of N- doped region 4.
The gate oxide 10 is thin gate oxide, with a thickness of 5nm-100nm.
Filled media layer 12 uses silica, nitride, high K dielectric in the slot, with a thickness of 200nm-500nm.
The working principle of this example are as follows:
(1) forward conduction of device:
Metal-oxide-semiconductor diode provided by the present invention with cylinder accumulation layer, electricity when forward conduction
Pole connection type are as follows: 9 high potential of anode electrode, cathode electrode 1 connect low potential.
When anode 9 is relative to cathode 1 plus no-voltage, since the doping concentration of p type buried layer 7 is much higher than N- doped region 4
Doping concentration is formed by PN junction Built-in potential and makes electricity between two p type buried layers 7 between p type buried layer 7 and N- doped region 4
Sub-channel is closed since the depletion region on both sides is connected, meanwhile, 4 surface of N- doped region under gate oxide 10 is located at
The N-type region 3 of 8 two sides of slot and the boundary part of slot 8 are also due to the work function difference and oxide layer positive charge of grid and semiconductor
It acts on and is depleted, dotted line is depletion region boundary in Fig. 2.Therefore it is flowed through in diode without electric current at this time.
Depletion region when anode 9 is relative to cathode 1 plus very small positive voltage, between p type buried layer 7 and N- doped region 4
It is gradually reduced, while the depletion region of 10 lower section of thin gate oxide also reduces.When anode 9 continues to add relative to the positive voltage of cathode 1
When greatly to a certain extent, the PN junction depletion region between p type buried layer 7 and N- doped region 4 is mutually separated, and electronics access generates, and device is opened
It opens, electronics is injected into N-type region 3 by the conductive channel between p type buried layer 7, as shown in figure 3, anode positive voltage at this time is pair
Should diode cut-in voltage.Due to the body bias effect of MOS structure, which has unlatching electricity more lower than conventional diode
Pressure.When added positive voltage continues to increase, electron concentration is higher in the electronics accumulation layer of 10 lower section of thin gate oxide, this is electron stream
It is dynamic to provide a more smooth access.Since polysilicon 13 is connected with anode, have high potential, therefore can with slot 8
The N-type semiconductor surface induction negative electrical charge being in contact, forms internal electron accumulation layer, further decreases on electron flow path diameter
Resistance；Meanwhile compared with patent " shallow slot MOS diode (CN 102064201A) ", the doping concentration ratio of N-type region 3
Big one to two orders of magnitude of the doping concentration of N- doped region 4, thus device has lower forward conduction pressure in forward conduction
Drop.
(2) reverse blocking of device:
Metal-oxide-semiconductor diode provided by the present invention with cylinder accumulation layer, electricity when reverse blocking
Pole connection type are as follows: cathode electrode 1 connects high potential, and anode electrode 9 connects low potential.
When due to zero-bias, the conductive path of electronics is by PN junction depletion region pinch off, when continuing growing backward voltage, p-type
Buried layer 7 and N-type region 3 form reverse biased pn junction, and N-type region 3 will further be exhausted.When reverse blocking, polysilicon 13 and anode etc. are electric
Position, N-type region 3 and cathode equipotential, generate transverse electric field between N-type region 3 and polysilicon 13, exhaust line to 3 downside of N-type region and body
Interior extension is to bear backward voltage, as shown in figure 4, final N-type region 3 is completely depleted.As shown in figure 4, N-type region 3 is by lateral electricity
After field exhausts, which is equivalent to the intrinsic region that net carrier concentration is zero, and according to Poisson's equation, the longitudinal electric field in the region is answered
It is approximate rectangular, and the longitudinal electric field of the N-type region 3 of patent " shallow slot MOS diode (CN 102064201A) " is triangle
Shape is distributed (as shown in Figure 5).Due to the integral that device pressure voltage is its longitudinal electric field, the reverse blocking pressure resistance of embodiment 1
It will be greatly improved.Further, in the case where identical reverse blocking is pressure-resistant, the N-type region 3 of embodiment 1 is adulterated dense
Degree, which compares patent " shallow slot MOS diode (CN 102064201A) ", can be improved, thus the drift region electricity of embodiment 1
Resistance reduces, and reduces forward conduction voltage drop, reduces energy loss when forward conduction.
Embodiment 2
As shown in fig. 6, the structure of this example is on the basis of embodiment 1, to change the shape of polysilicon 13.Polysilicon 13
Shape is wide at the top and narrow at the bottom, is in inverted trapezoidal, and the oxide layer of 8 bottom of slot is thickened compared with embodiment 1.The working principle and 1 class of embodiment of this example
Seemingly, the breakdown at 8 bottom corners of slot can be further prevented, reverse blocking pressure resistance is increased.
By taking embodiment 1 as an example, structure of the invention can be prepared using the following method, processing step are as follows:
1, monocrystalline silicon prepares.Using N-type heavy doping monocrystalline substrate 2, crystal orientation is<100>.
2, epitaxial growth.Using the N-type epitaxy layer of the methods of vapour phase epitaxy VPE growth certain thickness and doping concentration.
3, slot 8 etches.The slot of certain depth and width is etched in N-type epitaxy layer using the methods of ion etching.
4,8 inner medium layer of slot deposits.
5, polysilicon 13 backfills.The depositing polysilicon in slot 8, and carry out p-type doping.
5, it chemically-mechanicapolish polishes.
7, p type buried layer 7 injects.Making the figure of P buried layer 7 by lithography, then high-energy boron ion implanting, implant angle can be according to wanting
Change is asked, by adjusting Implantation Energy and dose change doping concentration and junction depth.
8, grid structure is prepared.Thermally grown gate oxide 10, depositing polysilicon gate electrode.
9, photoetching, etching form gate electrode 11.
10, autoregistration arsenic injection preparation N-type heavily doped region 5.
11, shallow slot etches, p-type heavily-doped implant, forms p-type heavily doped region 6.
12, front-side metallization anode.One layer of metallic aluminium is sputtered in entire device surface, forms metallization anode 9.
13, thinning back side, metallization form cathode 1.
Claims (4)
1. a kind of metal-oxide-semiconductor diode with accumulation layer, including the anode electricity being cascading from top to bottom
Pole (9), N- doped region (4), N-type region (3), N-type heavy doping monocrystalline substrate (2) and cathode electrode (1)；The anode electrode
(9) both ends are extended into vertically downward in N- doped region (4), the part that N- doped region (4) and anode electrode (9) extend downwardly it
Between have N-type heavily doped region (5)；N- doped region (4) upper surface between the N-type heavily doped region (5) of two sides has planar gate knot
Structure, the planar gate structure are located in anode electrode (1), the planar gate structure include gate oxide (10) and be located at gate oxidation
The polygate electrodes (11) of layer (10) upper surface, gate oxide (10) lower surface connects with part N-type heavily doped region (5) upper surface
Touching；The lower section of anode electrode (9) downward extension portion has the slot (8) and p-type heavily doped region (6) for being mutually juxtaposed setting,
And the portion of upper surface of p-type heavily doped region (6) is contacted with N-type heavily doped region (5)；The slot (8) extends vertically into N-type region (3)
In, dielectric layer (12) are filled in the slot (8), there are polysilicon (13) in the dielectric layer (12)；The p-type heavily doped region
(6) there are p type buried layer (7) between lower surface and N-type region (3) upper surface, and the side of p type buried layer (7) is connect with slot (8)；
When device forward conduction, polysilicon (13) is connected with anode electrode (9), has high potential, in the N-type being in contact with slot (8)
Semiconductor surface incudes negative electrical charge, forms internal electron accumulation layer；
The doping concentration of the p type buried layer (7) is greater than two orders of magnitude of doping concentration of N- doped region (4)；The N-type region (3)
Doping concentration be greater than N- doped region (4) one to two orders of magnitude of doping concentration, make device in forward conduction have it is lower
Forward conduction voltage drop.
2. a kind of metal-oxide-semiconductor diode with accumulation layer according to claim 1, which is characterized in that institute
Stating gate oxide (10) is thin gate oxide, with a thickness of 5nm-100nm.
3. a kind of metal-oxide-semiconductor diode with accumulation layer according to claim 2, which is characterized in that institute
The interior filled media layer (12) of slot (8) is stated using one of silica, nitride and high K dielectric, with a thickness of 200nm-
500nm。
4. a kind of metal-oxide-semiconductor diode with accumulation layer according to claim 1 to 3,
It is characterized in that, the shape of the polysilicon (13) is wide at the top and narrow at the bottom, is in inverted trapezoidal.
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| CN106229342A (en) * | 2016-08-22 | 2016-12-14 | 电子科技大学 | A kind of metal-oxide-semiconductor diode of many accumulation layers |
| CN109119489A (en) * | 2018-08-24 | 2019-01-01 | 电子科技大学 | A kind of metal-oxide-semiconductor diode of composite construction |
| CN109119488A (en) * | 2018-08-24 | 2019-01-01 | 电子科技大学 | A kind of metal-oxide-semiconductor diode with polysilicon island |
| CN109585572A (en) * | 2018-12-29 | 2019-04-05 | 矽力杰半导体技术(杭州)有限公司 | Semiconductor devices and its manufacturing method |
| CN111312802B (en) * | 2020-02-27 | 2022-01-28 | 电子科技大学 | Low-starting-voltage and low-on-resistance silicon carbide diode and preparation method thereof |
| CN111415997B (en) * | 2020-03-05 | 2020-11-10 | 江阴新顺微电子有限公司 | MOS structure groove diode device and manufacturing method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000349288A (en) * | 1999-06-09 | 2000-12-15 | Fuji Electric Co Ltd | Vertical mosfet |
| CN101764162A (en) * | 2010-01-15 | 2010-06-30 | 扬州扬杰电子科技有限公司 | Metallic oxide field-effect diode and MOS diode |
| CN102064201A (en) * | 2010-10-22 | 2011-05-18 | 深圳市芯威科技有限公司 | Shallow-slot metal oxide semiconductor diode |
-
2016
- 2016-06-03 CN CN201610394393.8A patent/CN105810754B/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000349288A (en) * | 1999-06-09 | 2000-12-15 | Fuji Electric Co Ltd | Vertical mosfet |
| CN101764162A (en) * | 2010-01-15 | 2010-06-30 | 扬州扬杰电子科技有限公司 | Metallic oxide field-effect diode and MOS diode |
| CN102064201A (en) * | 2010-10-22 | 2011-05-18 | 深圳市芯威科技有限公司 | Shallow-slot metal oxide semiconductor diode |
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