CN103117309A - Horizontal power device structure and preparation method thereof - Google Patents

Horizontal power device structure and preparation method thereof Download PDF

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Publication number
CN103117309A
CN103117309A CN2013100579433A CN201310057943A CN103117309A CN 103117309 A CN103117309 A CN 103117309A CN 2013100579433 A CN2013100579433 A CN 2013100579433A CN 201310057943 A CN201310057943 A CN 201310057943A CN 103117309 A CN103117309 A CN 103117309A
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semiconductor regions
groove
lateral power
preparation
groove structure
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郭宇锋
徐琴
黄示
徐光明
张长春
夏晓娟
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Nanjing Post and Telecommunication University
Nanjing University of Posts and Telecommunications
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Nanjing Post and Telecommunication University
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Abstract

The invention provides a horizontal power device structure and a preparation method thereof. By the structure, the size of a device can be effectively reduced, the integration level of the device can be improved, the density of a drift region can be optimized, and breakdown voltage is improved. As the size of the device is reduced and the optimal value of the density of the drift region is improved, on resistance of the device can be remarkably decreased, and the ratio of the breakdown voltage to the on resistance of the device is integrally increased. In addition, the drift region of the structure can be directly manufactured by the aid of a shallow trench isolation technology, a source region, a channel or a drain region is manufactured into a trench formed by the shallow trench isolation technology, the technology is simple and is completely compatible with a standard CMOS (complementary metal oxide semiconductor) technology, and the manufacturing cost of the device is also reduced.

Description

A kind of lateral power structure and preparation method thereof
Technical field
The invention belongs to semiconductor power device and semiconductor process techniques field, relate in particular to a kind of lateral power structure and preparation method thereof, as horizontal proliferation field-effect transistor LDMOS, horizontal high-voltage diode, landscape insulation bar double-pole-type transistor LIGBT etc.
Background technology
Power device is the core of modern power electronic system, and it plays vital effect to all technical and the performance that improves system.Desirable power device should have following desirable Static and dynamic characteristic: can bear high voltage when cut-off state; Have large electric current and very low pressure drop when conducting state; Has the short open and close time when switch transition.
Power semiconductor can be divided into two classes by working method: a class is traditional bipolar device, and it is current control device, comprises thyristor (SCR), power bipolar transistor (GTR) etc.; Another kind of is novel voltage-controlled device, comprises that metal-oxide semiconductor fieldeffect transistor (MOSFET), insulated gate bipolar transistor (IGBT) and MOS control thyristor (MCT) etc.Power MOS transistor has similar output voltage-current characteristic to power bipolar transistor, but the impact of the not few son storage of power MOS transistor effect, thereby operating frequency is than the height of bipolar transistor; And power MOS transistor is voltage control device, and its drive current is very little, therefore its drive circuit is also simply too much than bipolar device.And power MOS pipe has negative current temperature coefficient, and there is not the secondary-breakdown phenomenon of power bipolar transistor in it, and also the specific power bipolar transistor is wide in its safety operation area.Exactly because power MOS (Metal Oxide Semiconductor) device has the series of advantages that surpasses the power bipolar device, take MOSFET as main voltage-controlled type power device has obtained fast development, obtain a wide range of applications in power electronic equipment.
The MOS power transistor can be divided into two kinds of fundamental types: the MOS of vertical conduction and horizontal high-voltage power MOS.the article that the people such as H.W.Collins delivered in 1979 " Power MOSFET technology " (Proceedings of International Electron Devices Meeting, vertical double diffusion MOS (Vertical Double Diffused Metal Oxide Semiconductor Field Effect Transistor has been proposed pp.79-85), VDMOS), its structure is shown in Figure 1, structural base is the N-shaped semiconductor regions 103 with high-dopant concentration, structural top comprises N-shaped semiconductor regions 104 and a p-type semiconductor regions 101 with high-dopant concentration, semiconductor regions 101 and semiconductor regions 103 separate by a N-shaped semiconductor regions 102 with low doping concentration between both, here, semiconductor regions 104 consists of the source region of VDMOS, semiconductor regions 103 consists of the drain region of VDMOS, semiconductor regions 101 consists of the channel region of VDMOS, semiconductor regions 102 consists of the drift region of VDMOS.Adopt this kind vertical stratification, can reduce device size, reduce the conducting resistance of device.
Although the technique of VDMOS device is simple, but because it adopts vertical stratification, be difficult to be applied in the Planar integration technique of silicon, article " A3D, Physically Based Compact Model for IC VDMOS the Transistors " (Proc.21 that the people such as James Victory delivered in September, 1997 stInternational Conference on Microelecs, vol.1, pp.14-17) in proposed to be applicable to the VDMOS structure of IC integrated technique, as shown in Figure 2.It mainly is comprised of the semiconductor regions 103 of p-type semiconductor substrate region 100, p-type semiconductor regions 101, heavily doped p-type semiconductor regions 105, light dope N-shaped semiconductor regions 102, heavy doping N-shaped, 104 etc.This structure and the main distinction of VDMOS structure are to be connected a deep trench n+ district on the n+ oxygen buried layer of bottom, so that the surface drain contact to be provided, will drain and transfer to device surface bottom device.But the deep trench n+ district of this IC VDMOS structure is difficult to accurate making in actual process, increased complexity and the cost of technique, easily affects simultaneously performance of devices.
Different with the VDMOS device, horizontal proliferation field-effect transistor (Lateral Double Diffused Metal Oxide Semiconductor Field Effect Transistor, LDMOS) be a kind of device architecture fully compatible with integrated circuit technology, as shown in Figure 3.This structure comprises a N-shaped semiconductor regions 103 with high-dopant concentration, 104 and p-type semiconductor regions 101, semiconductor regions 101 and semiconductor regions 103 separate by a N-shaped semiconductor regions 102 with low doping concentration between both, here, semiconductor regions 104 consists of the source region of VDMOS, semiconductor regions 103 consists of the drain region of VDMOS, semiconductor regions 101 consists of the channel region of VDMOS, and semiconductor regions 102 consists of the drift region of VDMOS.The LDMOS structure has solved by horizontal double diffusion technique formation conducting channel district the contradiction that improves between withstand voltage and increase electric current well, is a present class power device very commonly used.
Although LDMOS is easier to be integrated, to compare with VDMOS, its shortcoming is that chip area is large, conducting resistance is large.The invention provides a kind of novel lateral power, it is not only fully compatible with CMOS technique, and adopts the vertical drift district as VDMOS, therefore has advantages of that simultaneously chip area is little, conducting resistance is low.
Summary of the invention
The present invention is directed to the technical problem that exists in the above-mentioned background technology, propose a kind of lateral power structure and preparation method thereof.
The present invention adopts following technical scheme for solving the problems of the technologies described above:
A kind of lateral power structure, described structure comprises that substrate is regional, have a groove structure on the substrate zone, described groove structure has the N-shaped semiconductor regions of a low doping concentration of the N-shaped semiconductor regions of a p-type semiconductor regions and a high-dopant concentration and interval p-type semiconductor regions and N-shaped semiconductor regions; When at this groove structure bottom configuration p-type semiconductor regions, at the N-shaped semiconductor regions of this groove structure top configuration high-dopant concentration; When the N-shaped semiconductor regions at this groove structure bottom configuration high-dopant concentration, at p-type semiconductor regions of this groove structure top configuration.
The N-shaped semiconductor regions of described low doping concentration is as the drift region, and its CONCENTRATION DISTRIBUTION is uniform or laterally varying doping or vertically varying doping or the horizontal and vertical varying doping that is.
Described trench wall is vertical plane or inclined plane or cascaded surface.
Described substrate zone is semi-conducting material or silicon dioxide oxide layer SOI.
The concrete form of described lateral power is horizontal proliferation field-effect transistor LDMOS or horizontal PN diode or landscape insulation bar double-pole-type transistor LIGBT or lateral thyristor.
A kind of preparation method of lateral power structure, the preparation method who adopts the shallow trench isolation technology to combine with CMOS technique, this preparation method comprises the following steps:
Steps A on the p-type backing material, adopts shallow trench isolation from the fabrication techniques silicon oxide groove;
Step B, gluing, photoetching are removed for the manufacture of the silica in vertical drift district groove, prepare groove structure;
Step C adopts standard CMOS process to make the device remainder.
The preparation method of described a kind of lateral power structure in described steps A, specifically comprises following processing step:
The growth of silica separator at P type silicon substrate, is carried out in steps A-1, and deposit silicon nitride;
Steps A-2, photo etched mask, etching window on silica and silicon nitride layer then erodes away the groove of designated depth at the window place;
Steps A-3, the side wall oxidation goes out one deck silicon oxide film in the groove growth inside, then adopts chemical vapour deposition technique (CVD) deposit silicon dioxide in groove;
Steps A-4, by chemical mechanical polishing method (CMP) planarization, silicon nitride and the silica on removal devices surface.
The preparation method of described a kind of lateral power structure in described step C, specifically comprises following processing step:
Step C-1 carries out the N-shaped Implantation in the device active region territory of silicon substrate, forms the intermediate concentration N-shaped doped region higher than substrate concentration, and carries out High temperature diffusion and advance;
Step C-2 utilizes photo etched mask and boron Implantation, preparation p trap, and carry out the high temperature knot;
Step C-3, heat growth grid oxygen, depositing polysilicon, the gluing photoetching forms polysilicon gate;
Step C-4 after polysilicon gate forms, adds mask plate and carries out the gluing photoetching at source-drain area, and the arsenic ion that then carries out the N-shaped source-drain area injects, and forms source-drain area;
Step C-5, gluing make P type source region by lithography, and the boron Implantation forms the contact of p-type body;
Step C-6, deposit field oxygen, then gluing develops, etching, exposes the contact hole zone, forms ohmic contact;
Step C-7, the sputter sial, photoetching and wet etching sial form metal electrode, and then photoetching forms the PAD contact, and then carries out alloy and passivation alloy, forms final device architecture.
The preparation method of described a kind of lateral power structure adopts wet etching or reactive ion etching method to make groove structure on the p-type backing material.
Beneficial effect: a kind of lateral power structure that the present invention proposes and preparation method thereof, adopt not only effective reduction of device size of this structure, improve the integrated level of device, also can optimize drift region concentration simultaneously, the raising puncture voltage.And due to the dwindling and the raising of drift region concentration optimization value of device size, its conducting resistance also can significantly reduce, thereby the whole ratio that has improved puncture voltage and the conducting resistance of device.In addition, the drift region of this structure can directly be made by the shallow trench isolation technology, source region, raceway groove or drain region is made in the groove of shallow ditch groove separation process formation, and technique is simple, and its technique and standard CMOS process are fully compatible, have also reduced the manufacturing cost of device.
Description of drawings
Fig. 1 is the VDMOS structural representation.
Fig. 2 is the VDMOS structural representation that is applicable to integrated circuit.
Fig. 3 is the LDMOS structural representation.
Fig. 4 is the LDMOS device architecture schematic diagram with vertical drift district provided by the invention.
Fig. 5 is the device architecture schematic diagram that employing shallow ditch groove separation process provided by the invention and traditional cmos process combine and make.
Fig. 6 is a kind of form with the LDMOS structure in vertical drift district of the present invention.
Fig. 7 is the vertical drift district PN diode structure schematic diagram that has of the present invention.
Fig. 8 is the vertical drift district LTGBT structural representation that has of the present invention.
Fig. 9 is the conventional LDMOS with same structure parameter, the equipotential lines distribution schematic diagram with LDMOS of vertical drift plot structure.Wherein Fig. 9 a is corresponding to conventional LDMOS structure, and Fig. 9 b is corresponding to the LDMOS structure with vertical drift district.
Figure 10 has the conventional LDMOS of same structure parameter and puncture voltage, the conducting resistance comparison diagram of vertical drift district LDMOS structure.
Embodiment
A kind of lateral power structure of the present invention and preparation method thereof is described below with reference to accompanying drawings in more detail.
The invention provides a kind of lateral power with drift region structure that uses the preparation of shallow trench isolation technology.Fig. 5 is the schematic diagram of this structure, make on p-type substrate zone 100 by the shallow trench isolation technology and obtained groove structure, form the N-shaped semiconductor regions 104 of p-type semiconductor regions 101 and high-dopant concentration at channel bottom, N-shaped semiconductor regions 103 at groove top formation high-dopant concentration, semiconductor regions 101 is connected with the 103 N-shaped semiconductor regions 102 by the trenched side-wall low doping concentration, semiconductor regions 101 is channel region, semiconductor regions 103,104 is respectively drain region and source region, and semiconductor regions 102 is the vertical drift district of LDMOS.
Need to prove:
(1) CONCENTRATION DISTRIBUTION of the semiconductor regions 102 of described N-shaped with low doping concentration can be both uniformly, can be also heterogeneous;
(2) described substrate zone 100 can be lightly doped semiconductor (body silicon), can be also silicon dioxide oxide layer (SOI);
(3) described vertical drift plot structure can also be used for horizontal PN diode (as Fig. 8), LIGBT(such as Fig. 9), lateral thyristor constant power device, with breakdown characteristics and the on state characteristic that improves simultaneously device.
Operation principle of the present invention:
Fig. 9 and Figure 10 are respectively according to the preliminary simulation results conventional LDMOS structure that obtains and equipotential lines distribution comparison diagram and puncture voltage comparison diagram with vertical drift district LDMOS structure.The structural parameters of these two kinds of structures are identical, and its drift region CONCENTRATION DISTRIBUTION is optimized.Can find out from Fig. 9 a, comparatively intensive at the lines such as surface at two ends, drift region for conventional structure, thus cause two ends peak electric field to occur, reduced puncture voltage.And for than the vertical drift plot structure in Fig. 9 b, it is comparatively even that its drift region equipotential lines distributes, and surface field is near constant, thereby improved puncture voltage.Can find out the vertical drift plot structure than conventional structure from Figure 10 a, its puncture voltage increases, and the drift region concentration figure of merit is also higher.And reflect intuitively that from Figure 10 a drift region concentration optimization value significantly improves, and the length of device is significantly reduced with respect to conventional structure due to after LDMOS of the present invention drift region employing shallow ditch groove separation process making vertical drift plot structure.From Figure 10 b as seen, the conventional structure that the conducting resistance of this structure compares has also reached the effect that significantly reduces, and has illustrated that vertical drift plot structure provided by the invention makes its puncture voltage and conducting resistance reach good compromise effect.
According to the vertical drift plot structure of use shallow trench isolation technology preparation provided by the invention, can produce the lateral power of characteristic good, be exemplified below:
1) has the LDMOS structure in vertical drift district, as Fig. 4, Fig. 6.Fig. 4 is the LDMOS device architecture schematic diagram with vertical drift district provided by the invention, this structure has a groove structure on p-type semiconductor substrate region 100: the p-type semiconductor regions 101 that is positioned at channel bottom consists of the channel region of LDMOS, the N-shaped semiconductor regions 104 that has high-dopant concentration on p-type semiconductor regions 101 consists of the source region of LDMOS, the N-shaped semiconductor regions 103 that is positioned at the high-dopant concentration at groove top consists of the drain region of LDMOS, the semiconductor regions 102 of the N-shaped with low doping concentration by the sidewall region low doping concentration between channel region 101 and drain region 103 is connected, semiconductor regions 102 is the drift region of LDMOS.Fig. 6 is a kind of form with the LDMOS structure in vertical drift district of the present invention, this structure has a groove structure on p-type Semiconductor substrate 100: the groove top comprises p-type semiconductor regions 101, the p-type semiconductor regions 105 of a high-dopant concentration, semiconductor regions 104 1 sides of high-dopant concentration N-shaped connect semiconductor regions 101, and opposite side connects semiconductor regions 105; Channel bottom is the N-shaped semiconductor regions 103 of high-dopant concentration; Sidewall region is the N-shaped semiconductor regions 102 with low doping concentration, connects semiconductor regions 101 and semiconductor regions 103.Here, semiconductor regions 102 consists of the drift region of LDMOS, and semiconductor regions 101 consists of the channel region of LDMOS, and semiconductor regions 104 consists of the source region of LDMOS, and semiconductor regions 103 consists of the drain region of LDMOS.
Semiconductor regions 102 is used as the vertical drift district, and its CONCENTRATION DISTRIBUTION formula is uniformly, or laterally varying doping or vertically varying doping, or the horizontal and vertical varying doping that is.
2) has the PN diode structure in vertical drift district, as shown in Figure 7.It comprises Semiconductor substrate 100, comprise a groove structure on substrate, has a p-type semiconductor regions 101 as the anode region at channel bottom, the semiconductor regions 103 that has a high-dopant concentration N-shaped at the groove top is as the cathodic region, and the N-shaped semiconductor regions 102 that has a low doping concentration by one of trench side wall area between the two separates.Semiconductor regions 102 is the vertical drift district of PN diode, and its CONCENTRATION DISTRIBUTION is uniformly, or laterally varying doping or vertically varying doping, or the horizontal and vertical varying doping that is.
3) have the insulator gate bipolar transistor in vertical drift district, be called for short LIGBT, as shown in Figure 8.It comprises a p-type substrate zone 100, has a groove structure above substrate.Comprise the N-shaped semiconductor regions 104 of a p-type semiconductor regions 101, a high-dopant concentration, the p-type semiconductor regions 105 of a high-dopant concentration at channel bottom, comprise the semiconductor regions 103 of a high-dopant concentration N-shaped and the semiconductor regions 106 of a high-dopant concentration p-type at the groove top, semiconductor regions 101 and semiconductor regions 103 have N-shaped semiconductor regions 102 isolation of low doping concentration by one of trench side wall area.Semiconductor regions 101 constituting channel districts wherein, a side is connected with semiconductor regions 104, and opposite side is connected with semiconductor regions 102,104 cathodic regions that consist of devices wherein, 102 consist of the drift region of devices.One side of semiconductor regions 103 is connected with semiconductor regions 102, and opposite side is connected with semiconductor regions 106, and semiconductor regions 106 consists of the anode region of device, and semiconductor regions 105 is as the body contact.The CONCENTRATION DISTRIBUTION of semiconductor regions 102 is uniformly, or laterally varying doping or vertically varying doping, or the horizontal and vertical varying doping that is.
Need to prove, a kind of lateral power structure that the present invention proposes also can be used for other lateral powers that are not listed as such as lateral thyristor, electrostatic induction transistor (SIT) except can being applied to above-mentioned listed a few class lateral powers.

Claims (9)

1. lateral power structure, it is characterized in that, described structure comprises substrate zone (100), have a groove structure on the substrate zone, described groove structure has the N-shaped semiconductor regions (102) of a low doping concentration of the N-shaped semiconductor regions (103) of a p-type semiconductor regions (101) and a high-dopant concentration and interval p-type semiconductor regions (101) and N-shaped semiconductor regions (103); When at this groove structure bottom configuration p-type semiconductor regions (101), configure the N-shaped semiconductor regions (103) of high-dopant concentration in this groove structure top side wall; When the N-shaped semiconductor regions (103) at this groove structure bottom configuration high-dopant concentration, at this groove structure top side wall configuration p-type semiconductor regions (101).
2. a kind of lateral power structure according to claim 1, it is characterized in that, the N-shaped semiconductor regions (102) of described low doping concentration is as the drift region, and its CONCENTRATION DISTRIBUTION is uniform or laterally varying doping or vertically varying doping or the horizontal and vertical varying doping that is.
3. a kind of lateral power structure according to claim 1, is characterized in that, it is vertical plane or inclined plane or cascaded surface that described groove structure is surveyed wall.
4. according to claim 1 and 2 or 3 described a kind of lateral power structures, is characterized in that, substrate zone (100) is semi-conducting material or silicon dioxide oxide layer.
5. a kind of lateral power structure according to claim 1, it is characterized in that, the concrete form of described lateral power is horizontal proliferation field-effect transistor LDMOS or horizontal PN diode or landscape insulation bar double-pole-type transistor LIGBT or lateral thyristor.
6. the preparation method based on lateral power structure claimed in claim 1, is characterized in that, this preparation method comprises the following steps:
Steps A on P type silicon substrate (100), adopts shallow trench isolation STI fabrication techniques silicon oxide groove structure;
Step B, gluing, photoetching are removed for the manufacture of the silica in the groove of groove structure, prepare groove structure;
Step C adopts standard CMOS process to make device.
7. the preparation method of a kind of lateral power structure according to claim 6, is characterized in that, in described steps A, specifically comprises following processing step:
The growth of silica separator on P type silicon substrate (100), is carried out, then deposit silicon nitride on the silica separator in steps A-1;
Steps A-2, photo etched mask, etching window on silica and silicon nitride layer then erodes away the groove of designated depth at the window place;
Steps A-3, the side wall oxidation goes out one deck silicon oxide film in the groove growth inside, then adopts chemical vapour deposition technique CVD deposit silicon dioxide in groove;
Steps A-4, by the chemical mechanical polishing method cmp planarization, silicon nitride and the silica on removal devices surface.
8. the preparation method of a kind of lateral power structure according to claim 6, is characterized in that, in described step C, specifically comprises following processing step:
Step C-1 carries out N-shaped light dope Implantation on p-type silicon substrate (100), form the intermediate concentration N-shaped doped region (102) higher than substrate concentration, and carries out the High temperature diffusion propelling;
Step C-2 utilizes photo etched mask and boron Implantation, preparation p trap (101), and carry out the high temperature knot;
Step C-3, heat growth grid oxygen, depositing polysilicon, the gluing photoetching forms polysilicon gate;
Step C-4 after polysilicon gate forms, adds mask plate and carries out the gluing photoetching at source-drain area, then carries out N-shaped heavy doping arsenic ion and injects, and forms source region (104) and drain region (103);
Step C-5, gluing make P type source region by lithography, carry out heavy doping boron Implantation, form p-type body contact zone (105);
Step C-6, deposit field oxygen, then gluing develops, etching, exposes the contact hole zone, forms ohmic contact;
Step C-7, the sputter sial, photoetching and wet etching sial form metal electrode, complete element manufacturing.
9. the preparation method based on lateral power structure claimed in claim 1, is characterized in that, comprises the steps:
Step (1) adopts wet etching or reactive ion etching method at the upper groove structure of making of p-type substrate (100);
Step (2) adopts standard CMOS process to make device.
CN2013100579433A 2013-02-22 2013-02-22 Horizontal power device structure and preparation method thereof Pending CN103117309A (en)

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CN108962848A (en) * 2018-07-17 2018-12-07 深圳市福来过科技有限公司 A kind of power device and preparation method thereof
CN109585288A (en) * 2013-09-26 2019-04-05 意法半导体(图尔)公司 SCR component with temperature stability characteristic (quality)
CN113035863A (en) * 2021-03-03 2021-06-25 浙江大学 Power integrated chip with longitudinal channel structure

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CN109585288A (en) * 2013-09-26 2019-04-05 意法半导体(图尔)公司 SCR component with temperature stability characteristic (quality)
CN109585288B (en) * 2013-09-26 2022-01-07 意法半导体(图尔)公司 SCR component with temperature stability characteristic and manufacturing method thereof
CN108110042A (en) * 2017-12-13 2018-06-01 深圳市晶特智造科技有限公司 Super-junction structure of semiconductor power device and preparation method thereof
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CN113035863B (en) * 2021-03-03 2022-06-03 浙江大学 Power integrated chip with longitudinal channel structure

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Application publication date: 20130522