CN102130153B - Silicon-on-insulator N-type transverse insulated gate bipolar transistor and preparation method thereof - Google Patents
Silicon-on-insulator N-type transverse insulated gate bipolar transistor and preparation method thereof Download PDFInfo
- Publication number
- CN102130153B CN102130153B CN201010600170A CN201010600170A CN102130153B CN 102130153 B CN102130153 B CN 102130153B CN 201010600170 A CN201010600170 A CN 201010600170A CN 201010600170 A CN201010600170 A CN 201010600170A CN 102130153 B CN102130153 B CN 102130153B
- Authority
- CN
- China
- Prior art keywords
- type
- layer
- epitaxial loayer
- silicon
- oxide
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Abstract
The invention relates to a silicon-on-insulator N-type transverse insulated gate bipolar transistor and a preparation method thereof. The silicon-on-insulator N-type transverse insulated gate bipolar transistor comprises a P-type silicon-on-insulator silicon wafer, wherein the right region of a first P-type epitaxial layer is provided with a P-type buried layer; a second P-type epitaxial layer is arranged above the first P-type epitaxial layer; a P-type high-energy ion-implantation layer and a P-type channel region are arranged in the second P-type epitaxial layer; the left side is provided with an N-type deep well and an N-type drift region; an N-type buffer layer and a P-type anode contact region are arranged in the N-type drift region; an N-type cathode contact region and a P-type body contact region are arranged in the P-type channel region; a first field oxide layer and a gate oxide layer are arranged above the N-type drift region; the gate oxide layer extends rightwards to above the P-type channel region; and polycrystalline silicon is arranged above the gate oxide layer and used as a gate. The preparation method comprises the following steps: carrying out implantation onto the right region of the first P-type epitaxial layer to form the P-type buried layer, and carrying out implantation onto the right region of the second P-type epitaxial layer to form the P-type high-energy ion-implantation layer which is communicated with the P-type buried layer, so that the concentration gradually increases from bottom to top so as to form an electrically conductive path which can effectively inhibit the latch effect.
Description
Technical field
The present invention relates to field of high voltage power semiconductor devices, say more accurately, is about a kind of N type lateral insulated gate bipolar transistor that is applicable to the silicon-on-insulator that has the inhibition latch-up under the high voltage and high power application conditions and preparation method thereof.
Background technology
Along with people's is to the enhancing day by day of modernized life requirement, and the power integrated circuit performance of products more and more receives publicity, and wherein the ability of power integrated circuit handle high voltages, big electric current more and more becomes one of main performance index.The factor of decision power integrated circuit handle high voltages, big current capacity size is except the circuit structure of power integrated circuit own, design and manufacturing process that circuit adopted, and the current capacity that individual devices of the same area can pass through is a key of weighing power integrated circuit performance and cost.
Because the basic electronic component that power semiconductor is a power electronic system carries out energy control and conversion; The semiconductor power device that constantly develops into of power electronic technology has been opened up application fields, and characteristics such as the conducting resistance of semiconductor power device and puncture voltage have then determined key propertys such as the efficient, power consumption of power electronic system.
Recently the silicon-on-insulator manufacturing technology is increasingly mature; With compare through the chip of traditional build substrate silicon wafer production; Separate movable silicon film and build substrate silicon substrate based on insulating barrier in the chip structure of silicon-on-insulator, therefore large-area PN junction will be replaced by dielectric isolation.Various traps can extend downward buried oxide, have effectively reduced leakage current and junction capacitance.Its result must be the speed of service that has increased substantially chip, has widened the temperature range of device work.Along with the appearance of the lateral double-diffused metal-oxide semiconductor device of silicon-on-insulator, it is with the incomparable advantage of common lateral double-diffused metal-oxide semiconductor device (low in energy consumption, antijamming capability is strong, integration density is high, speed is fast) and obtain extensively showing appreciation for somebody of academia and industrial quarters.
Insulated gate bipolar device combines the advantage of bipolar device and isolated gate FET device, and the little and saturation pressure of driving power reduces.Be fit to very much be applied to high-power fields such as converter system such as alternating current machine, frequency converter, Switching Power Supply, lighting circuit, traction transmission.
Yet in insulated gate bipolar device, have a parasitic PNP and NPN triode, thereby when electric current is excessive, can trigger the combination conducting generation latch-up of parasitic triode, cause the device can't operate as normal, even burn device.So how preventing the generation of latch-up or improving the activation threshold value condition all is one of difficult problem that in the application of insulated gate bipolar device, need overcome all the time.Traditional insulated gate bipolar device is to prevent that device generation latch-up from often forming a very dark P trap near the P type adulterate body contact area in P type doped channel regions; Make and to form the low-resistance conductive path to the path of P type adulterate body contact area and be drawn out to P type adulterate body contact zone from burying the oxide layer surface with the hole current that avalanche effect in the body is produced from burying the oxide layer surface; Thereby reduce the hole current that flows through from N type doping negative contact zone below, and then improved the performance that prevents latch-up.But the formation of dark P trap tends to have influence on the impurity concentration of P type doped body region, thereby can improve the threshold voltage and reduction device current capability of device.The present invention is directed to this problem and proposed a kind of modified model igbt, this device architecture can effectively suppress the generation of latch-up under the prerequisite that guarantees other device parameters.
Summary of the invention
The present invention is directed to the deficiency of prior art, propose N type lateral insulated gate bipolar transistor of a kind of silicon-on-insulator that effectively prevents latch-up and preparation method thereof.
The present invention adopts following technical scheme:
A kind of N type lateral insulated gate bipolar transistor of silicon-on-insulator; Comprise: P type substrate; P type substrate is provided with and buries oxide layer, buries oxide layer and is provided with a P type epitaxial loayer, above a P type epitaxial loayer, is provided with the 2nd P type epitaxial loayer; Be provided with N type doping deep trap in the left side of the 2nd P type epitaxial loayer; In N type doping deep trap and part the 2nd P type epitaxial loayer, be provided with N type doped drift region, in N type doped drift region, be provided with N type resilient coating, in N type resilient coating, be provided with P type doping anode contact area; Be provided with P type doped channel regions on the right side of the 2nd P type epitaxial loayer; In P type doped channel regions, be provided with N type doping negative contact zone territory and P type adulterate body contact zone,, be provided with gate oxide in the upper right side of N type doped drift region being provided with the first type field oxide above the N type doped drift region with above the part P type doped channel regions; And gate oxide extends to the top of part P type doped channel regions to the right; Above gate oxide, be provided with polysilicon, as the grid of device, and polysilicon extends to first type field oxide top; Grid field plate as device; Above polysilicon, the first type field oxide and N type doping negative contact zone territory and P type adulterate body contact zone, be coated with the second type field oxide, on P type doping anode contact area, be connected with the anode metal electrode, on N type doping negative contact zone territory and P type adulterate body contact zone, be connected with the cathodic metal layer; It is characterized in that the right side in a P type epitaxial loayer is provided with p type buried layer; The lower surface that right side in the 2nd P type epitaxial loayer is provided with P type energetic ion implanted layer and P type energetic ion implanted layer is communicated with the upper surface of p type buried layer, and said p type buried layer impurity concentration is greater than the impurity concentration of P type energetic ion implanted layer, and the impurity concentration of P type energetic ion implanted layer is greater than P type doped channel regions impurity concentration; The p type buried layer left margin extend at least the first type field oxide right margin under the zone, the left margin of P type energetic ion implanted layer extend to N type doping negative contact zone territory left margin under the zone.
The preparation method of the N type lateral insulated gate bipolar transistor of said silicon-on-insulator is characterized in that,
(1) get a P type SOI, wherein the thickness of a P type epitaxial loayer is 0.5-1 μ m, adopts ion to inject boron fluoride to form the p type buried layer of high-concentration dopant;
(2) epitaxial growth the 2nd P type epitaxial loayer, thickness is 6-7 μ m, adopts high energy particle to inject boron to form P type energetic ion implanted layer then;
(3) adopt ion injection and subsequent annealing technology to form the doping of N type deep-well region, N type doped drift region, P type doped channel regions and N type resilient coating then.Generate the first type field oxide through thermal growth oxide layer technology then;
(4) follow dry oxidation technology growth gate oxide; Deposit polysilicon then; And carry out etching formation polysilicon gate and polysilicon field plate structure, inject formation P type doping anode contact area, N type doping negative contact zone territory and P type adulterate body contact zone through ion then;
(5) the deposit second type field oxide and etch contact hole, deposit aluminium and etching aluminium form anode metal layer and cathodic metal layer then.Carry out the Passivation Treatment of postorder at last.
Compared with prior art, the present invention has following advantage:
(1) the N type lateral insulated gate bipolar transistor of silicon is to prevent that device generation latch-up from often forming a very dark P trap near the P type adulterate body contact area in P type doped channel regions on the traditional high voltage insulator; Make from burying the path formation low-resistance conductive path of oxide layer surface to P type adulterate body contact area; Shunted a part of hole current; Thereby reduce the hole current that flows through from N type doping negative contact zone below, and then improved the performance that prevents latch-up, with reference to Fig. 4.But in order to make the hole conduction via resistance less; The impurity concentration and the annealing that often increase dark P trap push away the trap time; Cause impurity horizontal proliferation to the P type doped channel regions in the dark P trap, and then improved the doping content of channel region, thereby can improve the threshold voltage of device.And employing p type buried layer 4, P type energetic ion implanted layer 6 and P type doped channel regions 9 combining structures among the present invention; With reference to Fig. 3; P type buried layer 4 can well extend to and bury oxide layer 2 surface voids accumulation maximum place, can farthest attract the hole to negative electrode, and p type buried layer 4 concentration is bigger; Form lower low impedance path, strengthened anti-breech lock ability widely.
(2) on the traditional high voltage insulator in the N type lateral insulated gate bipolar transistor of silicon dark P trap inject through ion and form, impurities concentration distribution is unfavorable for burying the conduction of oxide layer 2 surface voids for reducing gradually from top to bottom.And the present invention adopts p type buried layer 4, P type energetic ion implanted layer 6 and P type doped channel regions 9 combining structures, and concentration from top to bottom increases gradually.Because p type buried layer 4 is infused in a P type epitaxial loayer 3 surfaces; But in the process of epitaxial growth the 2nd P type epitaxial loayer 5; Impurity can diffuse to form p type buried layer 42 to a P type epitaxial loayer, in the 2nd P type epitaxial loayer 5, diffuses to form p type buried layer 41, and can be connected with P type energetic ion implanted layer 6; P type energetic ion implanted layer 6 upper surfaces are connected with P type doped channel regions 9, and the three forms p type impurity low-resistance conductive path.With reference to Fig. 3; Because p type buried layer 4 impurity concentrations are bigger; Can so that most of hole current through p type buried layer 4 to negative electrode, reduced the P type doped channel regions 9 of flowing through from the 2nd P type epitaxial loayer 5 zones again to the hole current of negative electrode, thereby made the electric resistance partial pressure of P type doped channel regions 9 of N type doping negative contact zone 13 belows less than PN junction cut-in voltage 0.7V; And then parasitic PNPN structure can conducting, has improved the activation threshold value condition of latch-up.Structure of the present invention is not merely the hole of burying the oxide layer surface sediment a more conductive path of low resistance is provided, and threshold voltage and puncture voltage are had no influence.
Description of drawings
Fig. 1 is the N type lateral insulated gate bipolar transistor structural representation of silicon on the high voltage insulator among the present invention.
Fig. 2 is the N type lateral insulated gate bipolar transistor structural representation that has the conventional high-tension silicon-on-insulator of dark P trap.
Fig. 3 is the N type lateral insulated gate bipolar transistor hole current distribution schematic diagram of silicon on the high voltage insulator among the present invention.
Fig. 4 is the N type lateral insulated gate bipolar transistor hole current distribution schematic diagram that has the conventional high-tension silicon-on-insulator of dark P trap.
Fig. 5 is the anti-breech lock ability comparison diagram of the N type lateral insulated gate bipolar transistor of silicon on the high voltage insulator of three kinds of different structures, and the trigger voltage of visible structure of the present invention is the highest.
Fig. 6-Figure 10 is a device preparing process flow chart among the present invention.
Embodiment
With reference to Fig. 1; A kind of N type lateral insulated gate bipolar transistor of silicon-on-insulator; Comprise: P type substrate 1; P type substrate 1 is provided with and buries oxide layer 2, buries oxide layer 2 and is provided with a P type epitaxial loayer 3, above a P type epitaxial loayer 3, is provided with the 2nd P type epitaxial loayer 5; Be provided with N type doping deep trap 7 in the left side of the 2nd P type epitaxial loayer 5; In N type doping deep trap 7 and part the 2nd P type epitaxial loayer 5, be provided with N type doped drift region 8, in N type doped drift region 8, be provided with N type resilient coating 10, in N type resilient coating 10, be provided with P type doping anode contact area 11; Be provided with P type doped channel regions 9 on the right side of the 2nd P type epitaxial loayer 5; In P type doped channel regions 9, be provided with N type doping negative contact zone territory 13 and P type adulterate body contact zone 12,, be provided with gate oxide 14 in the upper right side of N type doped drift region 8 being provided with the first type field oxide 16 above the N type doped drift region 8 with above the part P type doped channel regions 9; And gate oxide 14 extends to the top of part P type doped channel regions 9 to the right; Above gate oxide 14, be provided with polysilicon 15, as the grid of device, and polysilicon 15 extends to the first type field oxide, 16 tops; Grid field plate as device; Above polysilicon 15, the first type field oxide 16 and N type doping negative contact zone territory 13 and P type adulterate body contact zone 12, be coated with the second type field oxide 17, on P type doping anode contact area 11, be connected with anode metal electrode 18, on N type doping negative contact zone territory 13 and P type adulterate body contact zone 12, be connected with cathodic metal layer 19; It is characterized in that the right side in a P type epitaxial loayer 3 is provided with p type buried layer 4; The lower surface that right side in the 2nd P type epitaxial loayer 5 is provided with P type energetic ion implanted layer 6 and P type energetic ion implanted layer 6 is communicated with the upper surface of p type buried layer 4, and said p type buried layer 4 impurity concentration are greater than the impurity concentration of P type energetic ion implanted layer 6, and the impurity concentration of P type energetic ion implanted layer 6 is greater than P type doped channel regions 9 impurity concentration; P type buried layer 4 left margins extend at least the first type field oxide 16 right margin under the zone, the left margin of P type energetic ion implanted layer 6 extend to N type doping negative contact zone territory 13 left margins under the zone.
The preparation method of the N type lateral insulated gate bipolar transistor of silicon-on-insulator according to the invention is characterized in that,
(1) get a P type SOI, wherein the thickness of a P type epitaxial loayer 3 is 0.5-1 μ m, adopts ion to inject boron fluoride to form the p type buried layer 4 of high-concentration dopant;
(2) epitaxial growth the 2nd P type epitaxial loayer 5, thickness is 6-7 μ m, adopts high energy particle to inject boron to form P type energetic ion implanted layer 6 then;
(3) adopt ion injection and subsequent annealing technology to form N type doping deep-well region 7, N type doped drift region 8, P type doped channel regions 9 and N type resilient coating 10 then.Generate the first type field oxide 16 through thermal growth oxide layer technology then;
(4) follow dry oxidation technology growth gate oxide 14; Deposit polysilicon then; And carry out etching formation polysilicon gate and polysilicon field plate structure 15, inject formation P type doping anode contact area 11, N type doping negative contact zone territory 13 and P type adulterate body contact zone 12 through ion then;
(5) the deposit second type field oxide 17 and etch contact hole, deposit aluminium and etching aluminium form anode metal layer 18 and cathodic metal layer 19 then, carry out the Passivation Treatment of postorder at last.
Also adopt following technical measures to come further to improve performance of the present invention in the present embodiment:
In the described device architecture p type buried layer 4 left margins extend at least the first type field oxide 16 left margin under the zone.
In the described device architecture left margin of P type energetic ion implanted layer 6 to extend to N type doping negative contact zone territory 13 left margins under the zone.
P type buried layer 4 in the described device architecture, P type energetic ion implanted layer 6 and P type doped channel regions 9 guarantee to communicate with each other after diffusion of impurities and are one.
P type adulterate body contact area 12 in the described device architecture keeps a determining deviation, 0.5-1.5 μ m with N type negative contact zone territory 13.
Impurity in the described device architecture in the p type buried layer 4 adopts boron fluoride, to reduce the diffusion to two P type epitaxial loayer 5 of p type impurity in the postorder annealing process.
The present invention adopts following method to prepare:
1, get a P type SOI, wherein the thickness of a P type epitaxial loayer 3 is 0.5-1 μ m, adopts ion to inject boron fluoride to form the p type buried layer 4 of high concentration then;
2, epitaxial growth the 2nd P type epitaxial loayer 5, thickness is 6-7 μ m, adopts high energy particle to inject boron to form P type energetic ion implanted layer 6 then, annealing makes p type buried layer 4 and P type energetic ion implanted layer 6 be communicated with then;
3, adopt ion injection and subsequent annealing technology to form N type doping deep-well region 7 then; Then ion injects and forms N type doped drift region 8 and P type doped channel regions 9 and N type resilient coating 10.Generate the first type field oxide 16 through thermal growth oxide layer technology then;
4, the gate oxide 14 of then growing, deposit polysilicon, and carry out etching and form polysilicon gate and polysilicon field plate structure 15 injects through ion then and forms P type doping anode contact area 11, N type doping negative contact zone territory 13 and P type adulterate body contact zone 12;
5, through the deposit second type field oxide 17 and etch contact hole, deposit aluminium and etching aluminium form anode metal layer 18 and cathodic metal layer 19 then, carry out the Passivation Treatment of postorder at last.
Claims (4)
1. the N type lateral insulated gate bipolar transistor of a silicon-on-insulator; Comprise: P type substrate (1); P type substrate (1) is provided with and buries oxide layer (2); Bury oxide layer (2) and be provided with a P type epitaxial loayer (3); Be provided with the 2nd P type epitaxial loayer (5) in a P type epitaxial loayer (3) top; Be provided with N type doping deep trap (7) in the left side of the 2nd P type epitaxial loayer (5); In N type doping deep trap (7) and part the 2nd P type epitaxial loayer (5), be provided with N type doped drift region (8); In N type doped drift region (8), be provided with N type resilient coating (10); In N type resilient coating (10), be provided with P type doping anode contact area (11), be provided with P type doped channel regions (9), in P type doped channel regions (9), be provided with N type doping negative contact zone territory (13) and P type adulterate body contact zone (12) on the right side of the 2nd P type epitaxial loayer (5); Be provided with the first type field oxide (16) in the top of N type doped drift region (8) and the top of part P type doped channel regions (9); Be provided with gate oxide (14) in the upper right side of N type doped drift region (8), and gate oxide (14) extends to the top of part P type doped channel regions (9) to the right, be provided with polysilicon (15) in the top of gate oxide (14); Grid as device; And polysilicon (15) extends to the first type field oxide (16) top, as the grid field plate of device, is coated with the second type field oxide (17) in polysilicon (15), the first type field oxide (16) and N type doping negative contact zone territory (13) and top, P type adulterate body contact zone (12); On P type doping anode contact area (11), be connected with anode metal electrode (18); On N type doping negative contact zone territory (13) and P type adulterate body contact zone (12), be connected with cathodic metal layer (19), it is characterized in that the right side in a P type epitaxial loayer (3) is provided with p type buried layer (4), the lower surface that the right side in the 2nd P type epitaxial loayer (5) is provided with P type energetic ion implanted layer (6) and P type energetic ion implanted layer (6) is communicated with the upper surface of p type buried layer (4); Said p type buried layer (4) impurity concentration is greater than the impurity concentration of P type energetic ion implanted layer (6); The impurity concentration of P type energetic ion implanted layer (6) is greater than P type doped channel regions (9) impurity concentration, p type buried layer (4) left margin extend at least the first type field oxide (16) right margin under the zone, the left margin of P type energetic ion implanted layer (6) extend to N type doping negative contact zone territory (13) left margin under the zone.
2. the N type lateral insulated gate bipolar transistor of silicon-on-insulator according to claim 1 is characterized in that, the upper surface of P type energetic ion implanted layer (6) is communicated with the lower surface of P type doped channel regions (9).
3. the preparation method of the N type lateral insulated gate bipolar transistor of the said silicon-on-insulator of claim 1 is characterized in that,
(1) get a P type SOI, wherein the thickness of a P type epitaxial loayer (3) is 0.5-1 μ m, adopts ion to inject boron fluoride to form the p type buried layer (4) of high-concentration dopant;
(2) epitaxial growth the 2nd P type epitaxial loayer (5), thickness is 6-7 μ m, adopts high energy particle to inject boron to form P type energetic ion implanted layer (6) then;
(3) adopt ion injection and subsequent annealing technology to form N type doping deep-well region (7) then; N type doped drift region (8); P type doped channel regions (9) and N type resilient coating (10) generate the first type field oxide (16) through thermal growth oxide layer technology then;
(4) follow dry oxidation technology growth gate oxide (14); Deposit polysilicon then; And carry out etching and form polysilicon gate and polysilicon field plate structure (15); Inject through ion then and form P type doping anode contact area (11), N type doping negative contact zone territory (13) and P type adulterate body contact zone (12);
(5) the deposit second type field oxide (17) and etch contact hole, deposit aluminium and etching aluminium form anode metal layer (18) and cathodic metal layer (19) then, carry out the Passivation Treatment of postorder at last.
4. the preparation method of the N type lateral insulated gate bipolar transistor of silicon-on-insulator according to claim 3; It is characterized in that; P type buried layer (4), P type energetic ion implanted layer (6) and P type doped channel regions (9) three form the low-resistance conductive path in hole through the postorder annealing process because of diffusion of impurities can be interconnected.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201010600170A CN102130153B (en) | 2010-12-22 | 2010-12-22 | Silicon-on-insulator N-type transverse insulated gate bipolar transistor and preparation method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201010600170A CN102130153B (en) | 2010-12-22 | 2010-12-22 | Silicon-on-insulator N-type transverse insulated gate bipolar transistor and preparation method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102130153A CN102130153A (en) | 2011-07-20 |
| CN102130153B true CN102130153B (en) | 2012-09-19 |
Family
ID=44268144
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201010600170A Expired - Fee Related CN102130153B (en) | 2010-12-22 | 2010-12-22 | Silicon-on-insulator N-type transverse insulated gate bipolar transistor and preparation method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102130153B (en) |
Families Citing this family (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103094124B (en) * | 2011-11-04 | 2015-08-19 | 上海华虹宏力半导体制造有限公司 | The structure of fetron and manufacture method |
| CN103094319B (en) * | 2011-11-04 | 2015-10-14 | 上海华虹宏力半导体制造有限公司 | Binary channels fetron reduces structure and the manufacture method of pinch-off voltage |
| CN103178087B (en) * | 2011-12-26 | 2016-02-10 | 上海华虹宏力半导体制造有限公司 | Superhigh pressure LDMOS device structure and preparation method |
| CN105226089B (en) * | 2015-10-29 | 2019-05-07 | 株洲南车时代电气股份有限公司 | A kind of igbt chip and preparation method thereof |
| CN108269841B (en) * | 2016-12-30 | 2020-12-15 | 无锡华润上华科技有限公司 | Lateral diffusion metal oxide semiconductor field effect transistor |
| CN109148586B (en) * | 2018-08-16 | 2021-05-18 | 中国电子科技集团公司第十三研究所 | Gallium oxide field effect transistor |
| CN113314600B (en) * | 2021-06-22 | 2022-04-15 | 珠海市浩辰半导体有限公司 | Buried layer terminal structure and preparation method thereof |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6191453B1 (en) * | 1999-12-13 | 2001-02-20 | Philips Electronics North America Corporation | Lateral insulated-gate bipolar transistor (LIGBT) device in silicon-on-insulator (SOI) technology |
| CN1685518A (en) * | 2002-09-30 | 2005-10-19 | 皇家飞利浦电子股份有限公司 | Lateral insulated gate bipolar PMOS device |
| CN201904340U (en) * | 2010-12-22 | 2011-07-20 | 东南大学 | N type lateral insulating gate bipolar transistor of silicon on insulator |
-
2010
- 2010-12-22 CN CN201010600170A patent/CN102130153B/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6191453B1 (en) * | 1999-12-13 | 2001-02-20 | Philips Electronics North America Corporation | Lateral insulated-gate bipolar transistor (LIGBT) device in silicon-on-insulator (SOI) technology |
| CN1685518A (en) * | 2002-09-30 | 2005-10-19 | 皇家飞利浦电子股份有限公司 | Lateral insulated gate bipolar PMOS device |
| CN201904340U (en) * | 2010-12-22 | 2011-07-20 | 东南大学 | N type lateral insulating gate bipolar transistor of silicon on insulator |
Also Published As
| Publication number | Publication date |
|---|---|
| CN102130153A (en) | 2011-07-20 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102130153B (en) | Silicon-on-insulator N-type transverse insulated gate bipolar transistor and preparation method thereof | |
| CN102903746B (en) | High-current-density lateral ultra-thin insulated gate bipolar transistor | |
| CN102201406B (en) | Bipolar CMOS DMOS (BCD) integrated device based on N type extension layer and manufacture method thereof | |
| CN103035521B (en) | Realize the process of few groove-shaped IGBT of sub-accumulation layer | |
| CN109065607A (en) | A kind of bipolar-type power semiconductor device and preparation method thereof | |
| CN110504310A (en) | A kind of RET IGBT and preparation method thereof with automatic biasing PMOS | |
| CN103762230B (en) | N-channel injection efficiency reinforced insulation grid bipolar transistor | |
| CN101764150B (en) | Silicon-on-insulator lateral insulated gate bipolar transistor and process manufacturing method | |
| CN107507861B (en) | Schottky contact injection enhanced SiC PNM-IGBT device and preparation method thereof | |
| CN102779839A (en) | Insulated gate bipolar transistor (IGBT) with deep energy level impurity implantation | |
| CN101834202B (en) | N-type lateral insulated gate bipolar device capable of reducing hot carrier effect | |
| CN105633142B (en) | A kind of tunneling field-effect transistor inhibiting off-state current | |
| CN103855206A (en) | Insulated gate bipolar transistor and manufacturing method thereof | |
| CN109065608A (en) | A kind of lateral bipolar power semiconductor and preparation method thereof | |
| CN101819993B (en) | P type lateral insulated gate bipolar device for reducing hot carrier effect | |
| CN110504313B (en) | Transverse groove type insulated gate bipolar transistor and preparation method thereof | |
| CN201904340U (en) | N type lateral insulating gate bipolar transistor of silicon on insulator | |
| CN103117309A (en) | Horizontal power device structure and preparation method thereof | |
| CN110473917A (en) | A kind of transversal I GBT and preparation method thereof | |
| CN201667336U (en) | N-type lateral insulated-gate bipolar device for reducing hot carrier effect | |
| CN113782586A (en) | Multi-channel super-junction IGBT device | |
| CN103779404B (en) | P Channeling implantation enhanced efficiency insulated gate bipolar transistor | |
| CN103094100B (en) | A kind of method forming Schottky diode | |
| CN201638820U (en) | P type lateral isolation gate bipolar device for reducing hot carrier effect | |
| CN102263127B (en) | MOS (Metal Oxide Semiconductor) type power device and manufacturing method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| EE01 | Entry into force of recordation of patent licensing contract |
Application publication date: 20110720 Assignee: TAIZHOU HAITIAN SEMICONDUCTOR Co.,Ltd. Assignor: Southeast University Contract record no.: 2014320000095 Denomination of invention: Silicon-on-insulator N-type transverse insulated gate bipolar transistor and preparation method thereof Granted publication date: 20120919 License type: Exclusive License Record date: 20140228 |
|
| LICC | Enforcement, change and cancellation of record of contracts on the licence for exploitation of a patent or utility model | ||
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20120919 Termination date: 20211222 |