CN108269841B - Lateral diffusion metal oxide semiconductor field effect transistor - Google Patents

Lateral diffusion metal oxide semiconductor field effect transistor Download PDF

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CN108269841B
CN108269841B CN201611265906.1A CN201611265906A CN108269841B CN 108269841 B CN108269841 B CN 108269841B CN 201611265906 A CN201611265906 A CN 201611265906A CN 108269841 B CN108269841 B CN 108269841B
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oxide layer
channel region
substrate
effect transistor
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CN108269841A (en
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张广胜
张森
胡小龙
吴肖
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CSMC Technologies Fab2 Co Ltd
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CSMC Technologies Fab2 Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/063—Reduced surface field [RESURF] pn-junction structures
    • H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
    • H01L29/42368—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform

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Abstract

The invention relates to a lateral diffusion metal oxide semiconductor field effect transistor, which comprises a substrate of a second conduction type, a drift region of a first conduction type on the substrate, a channel region of the second conduction type on the substrate, a drain region of the first conduction type on the surface of the drift region, a source region on the surface of the channel region, a first field oxide layer between the drain region and the source region, and a second field oxide layer positioned on one side of the channel region far away from the drain region. The invention can reduce the crosstalk of the leakage current of the device on the peripheral control circuit under the condition of high-temperature operation.

Description

Lateral diffusion metal oxide semiconductor field effect transistor
Technical Field
The invention relates to the field of semiconductor manufacturing, in particular to a lateral diffusion metal oxide semiconductor field effect transistor.
Background
In a conventional ultra-high voltage lateral diffusion metal oxide semiconductor field effect transistor (LDMOS), when a Single-reduction surface electric field (Single Resurf), a Double-reduction surface electric field (Double Resurf), a Triple-reduction surface electric field (Triple Resurf) and a multiple-reduction surface electric field (multiple Resurf) LDMOS device with a conventional structure works at high temperature, electron-hole pairs are generated due to lattice scattering and collision, so that leakage current is collected by a substrate, crosstalk between the LDMOS and control logic is caused, and the product performance of the LDMOS is affected.
Disclosure of Invention
In view of the above, there is a need for a lateral diffused metal oxide semiconductor field effect transistor capable of reducing crosstalk of leakage current of the device to a peripheral control circuit under high temperature operation conditions.
A laterally diffused metal oxide semiconductor field effect transistor comprises a substrate of a second conduction type, a drift region of the first conduction type on the substrate, a channel region of the second conduction type on the substrate, a drain region of the first conduction type on the surface of the drift region, a source region on the surface of the channel region, a first field oxide layer between the drain region and the source region, and a second field oxide layer located on one side, far away from the drain region, of the channel region, wherein the laterally diffused metal oxide semiconductor field effect transistor is further provided with an isolation groove penetrating from the second field oxide layer downwards into the substrate, the conductivity of a filler in the isolation groove is smaller than those of the substrate, the drift region and the channel region, and the first conduction type and the second conduction type are opposite conduction types.
In one embodiment, the filler is polysilicon or an oxide layer.
In one embodiment, the channel region is disposed on a surface of the drift region, the isolation trench penetrates the drift region downward and then reaches the substrate, the source region includes a first-conductivity-type doped region and a second-conductivity-type doped region, the first-conductivity-type doped region is closer to the first field oxide layer than the second-conductivity-type doped region, and the laterally diffused metal oxide semiconductor field effect transistor further includes a gate extending from the first-conductivity-type doped region to the first field oxide layer.
In one embodiment, the channel region includes a first channel region located between the first field oxide layer and the second field oxide layer, and a second channel region located below the first field oxide layer and in the drift region, and the first-conductivity-type doped region and the second-conductivity-type doped region are located in the first channel region.
In one embodiment, the first channel region and the second channel region are formed in the same step.
In one embodiment, the second channel region is a plurality of discrete structures, and the discrete structures are arranged more densely closer to the source region.
In one embodiment, the semiconductor device further comprises a buried oxide layer located in the drift region and below the first field oxide layer.
In one embodiment, a voltage-resistant trench extending downwards from the surface of the drift region on the side of the drain region far away from the source region is further provided, and the conductivity of a filler in the voltage-resistant trench is smaller than that of the substrate, the drift region and the channel region.
In one embodiment, the top of the voltage-resistant trench is arranged between the drain region and the third field oxide layer on the side of the drain region far away from the source region.
In one embodiment, the voltage-resistant trench and the isolation trench are formed in the same step.
The transverse diffusion metal oxide semiconductor field effect transistor is provided with the isolation groove with enough depth at the periphery of the source region of the device, which is equivalent to forming a barrier layer of a current path, so that the hole current formed by electron holes generated when the device works at high temperature can be ensured to flow to the substrate and collected by the substrate without crosstalk with a control circuit in a chip. And the source voltage of the device can float to a certain voltage value due to the isolation of the isolation trench, so that the defect of the non-isolated LDMOS source voltage operation is overcome.
Drawings
FIG. 1 is a schematic structural view of a lateral diffused metal oxide semiconductor field effect transistor of example 1;
FIG. 2 is a schematic structural view of a lateral diffused metal oxide semiconductor field effect transistor of example 2;
FIG. 3 is a schematic structural view of a lateral diffused metal oxide semiconductor field effect transistor of example 3;
FIG. 4 is a schematic structural view of a lateral diffused metal oxide semiconductor field effect transistor of example 4;
FIG. 5 is a schematic structural view of a lateral diffused metal oxide semiconductor field effect transistor of example 5;
FIG. 6 is a schematic structural view of a lateral diffused metal oxide semiconductor field effect transistor according to example 6;
FIG. 7 is a schematic structural view of a lateral diffused metal oxide semiconductor field effect transistor according to example 7;
fig. 8 is a schematic structural view of a lateral diffused metal oxide semiconductor field effect transistor according to embodiment 8.
Detailed Description
To facilitate an understanding of the invention, the invention will now be described more fully with reference to the accompanying drawings. Preferred embodiments of the present invention are shown in the drawings. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.
As used herein, the term semiconductor is used in the art to distinguish between P-type and N-type impurities, and for example, P + type represents P-type with heavy doping concentration, P-type represents P-type with medium doping concentration, P-type represents P-type with light doping concentration, N + type represents N-type with heavy doping concentration, N-type represents N-type with medium doping concentration, and N-type represents N-type with light doping concentration.
Example 1:
fig. 1 is a schematic structural diagram of a lateral diffusion metal oxide semiconductor field effect transistor in embodiment 1, which includes a substrate 101 of a second conductivity type, a drift region 102 of a first conductivity type on the substrate 101, a channel region 103 of the second conductivity type on the substrate 101, a drain region 110 of the first conductivity type on a surface of the drift region 102, a source region (including a first-conductivity-type doped region 111 and a second-conductivity-type doped region 112 in this embodiment) on a surface of the channel region 103, a first field oxide layer 104 between the drain region 110 and the source region, and a second field oxide layer 104a on a side of the channel region 103 away from the drain region 110. It should be noted that the side of the channel region 103 away from the drain region 110 referred to in the present specification and claims is described with respect to the structure in one cell, that is, the channel region 103 and the drain region 110 refer to the structure in the same cell. The ldmos fet is further provided with an isolation trench 108 penetrating from the second field oxide layer 104a down to the substrate 101. The conductivity of the fill within the isolation trench 108 is less than the conductivity of the substrate 101, the drift region 102 and the channel region 103. The first conductivity type and the second conductivity type are opposite conductivity types, and in this embodiment, the first conductivity type is an N-type and the second conductivity type is a P-type.
In the lateral diffusion metal oxide semiconductor field effect transistor, the isolation groove 108 with enough depth is arranged at the periphery of the source region of the device, which is equivalent to a barrier layer for forming a current path, so that the hole current formed by electron holes generated when the device works at high temperature can be ensured to flow to the substrate and be collected by the substrate without crosstalk with a control circuit in a chip. And the source voltage of the device can float to a certain voltage value due to the isolation of the isolation trench 108, so that the defect of the non-isolated LDMOS source voltage operation is overcome.
In the embodiment shown in fig. 1, the first conductive-type doped region 111 and the second conductive-type doped region 112 are connected to the source metal 107 as source leads; the drain region 110 is connected to the drain metal 106 as a drain lead. The channel region 103 is disposed on the surface of the drift region 102, and the isolation trench 108 penetrates the drift region 102 downward and reaches the substrate 101. The first conductive type doping region 111 is disposed adjacent to the first field oxide layer 104, and the second conductive type doping region 112 is disposed adjacent to the second field oxide layer 104 a. The ldmos field effect transistor further includes a gate electrode 105 extending from the first conductive type doping region 111 to the first field oxide layer 104. In the present embodiment, the gate 105 is a polysilicon gate.
In the embodiment shown in fig. 1, the substrate 101 is a silicon substrate, and the filling material in the isolation trench 108 is polysilicon or an oxide layer (e.g., silicon oxide, such as silicon dioxide). The depth of the isolation trench 108 into the substrate 101 is 20% to 80% of the substrate 101. The drain region 110 is an N + region, the first conductive type doping region 111 is an N + region, and the second conductive type doping region 112 is a P + region.
If the structure is applied to the ultra-high voltage LDMOS, the substrate 101 can be depleted by using a substrate material with higher resistivity, so that higher breakdown voltage can be obtained. The drift region 102 may be formed by ion implantation followed by high temperature drive-in, after which the junction depth must reach a certain depth to ensure the device substrate depletion and current conduction path.
The doping concentration of the channel region 103 may affect the depletion of the drift region 102 and the turn-on voltage of the device. In other embodiments, an auxiliary depletion structure may be provided in the drift region 102 between the source region and the drain region 110 to assist the depletion of the drift region 102, thereby increasing the N-type impurity concentration in the drift region 102 and reducing the on-resistance of the device. Three auxiliary depletion structures are provided below by examples 2-4.
Example 2:
fig. 2 is a schematic structural diagram of a lateral diffusion mosfet of embodiment 2, which is different from embodiment 1 mainly in that a channel region 103a is disposed in the drift region 102 below the first field oxide layer 104 in addition to the channel region 103 between the first field oxide layer 104 and the second field oxide layer 104a (a source region is disposed in the channel region 103). The channel region 103a is arranged to assist the depletion of the drift region 102, so that the N-type impurity concentration in the drift region 102 is increased, and the on-resistance of the device is reduced.
In the present embodiment, the channel region 103 and the channel region 103a are formed in the same step to save the manufacturing process and the number of photolithography tools.
Example 3:
fig. 3 is a schematic structural diagram of a lateral diffused metal oxide semiconductor field effect transistor in embodiment 3, which is different from embodiment 2 mainly in that the channel region 103a is a plurality of discrete structures. Since the need for depletion of the auxiliary drift region 102 is greater closer to the source region, in other words, the need for depletion of the auxiliary drift region 102 is lower closer to the drain region 110, the channel region 103a does not need to be provided with a strip as in embodiment 2, but a structure in which the doping concentration (i.e., the concentration of the P-type impurity) gradually decreases from the source region to the drain region 110 may be provided as the corresponding channel region. In consideration of implementation difficulty in manufacturing, the channel regions 103a of the discrete structures may be disposed more densely as the discrete structures are closer to the source region. In particular, when fabricating a reticle, a plurality of stripe-shaped windows may be provided as implantation windows of the channel region 103a, and the closer these implantation windows are to the drain region 110, the longer the length and the longer the distance therebetween are. P-type ions are implanted into the window and then thermally diffused to obtain the channel region 103a shown in fig. 3.
Example 4:
fig. 4 is a schematic structural diagram of a lateral diffused metal oxide semiconductor field effect transistor in embodiment 4, which is mainly different from embodiment 1 in that a buried oxide layer 113 is disposed in a drift region 102 below a first field oxide layer 104. The buried oxide layer 113 also serves to assist depletion of the drift region 102, thereby increasing the N-type impurity concentration in the drift region 102 and reducing the on-resistance of the device.
Example 5:
fig. 5 is a schematic structural diagram of the ldmos field effect transistor of embodiment 5, which includes a substrate 201 of a second conductivity type, a drift region 202 of a first conductivity type on the substrate 201, a channel region 203 of the second conductivity type on the substrate 201, a drain region 210 of the first conductivity type on a surface of the drift region 202, a source region on a surface of the channel region 203, a first field oxide layer 204 between the drain region 210 and the source region, and a second field oxide layer 204a on a side of the channel region 203 away from the drain region 210. The LDMOS is further provided with an isolation trench 208 penetrating from the second field oxide layer 204a down to the substrate 201, and a voltage-resistant trench 209 extending down from the surface of the drift region 202 on the side of the drain region 210 away from the source region. Similarly, the side of the drain region 210 away from the source region is also described with respect to the structure in one cell, i.e., the drain region 210 and the source region refer to the structure in the same cell. The conductivity of the filler in isolation trench 208 and pressure resistant trench 209 is less than the conductivity of substrate 201, drift region 202, and channel region 203. The first conductivity type and the second conductivity type are opposite conductivity types, and in this embodiment, the first conductivity type is an N-type and the second conductivity type is a P-type.
Shown in fig. 5 is a cell structure of a device, which may be in the form of an array of cells as in the structure shown in fig. 1.
The width of the withstand voltage trench 209 (i.e., the dimension in the lateral direction in fig. 5) is adjusted according to the specific device design withstand voltage, and the higher the withstand voltage of the device, the wider the withstand voltage trench 209 should be designed. For designing an LDMOS with higher withstand voltage, a longer drift region is generally required to meet the withstand voltage requirement in the prior art. After the voltage-resistant trench 209 is provided, since the voltage resistance of the voltage-resistant trench 209 itself is high, the shorter drift region 202 can be designed, so that the area of the LDMOS can be reduced, the cost can be reduced, and the on-resistance of the device can be reduced.
In one embodiment, the same filler as that in the isolation trench 208 may be used as the filler in the voltage-resistant trench 209. Since the oxide layer has a high withstand voltage, silicon oxide (e.g., silicon dioxide) may be used as a filler when a high demand is placed on the withstand voltage of the LDMOS. In order to save cost, isolation trench 208 and dielectric trench 209 may be formed in the same step, and the filling in isolation trench 208 and dielectric trench 209 may be filled in the same step.
Examples 6 to 8 each provide an auxiliary depletion structure. An auxiliary depletion structure is provided in the drift region 202 between the source region and the drain region 210 to assist depletion of the drift region 202, thereby increasing the N-type impurity concentration in the drift region 202 and reducing the on-resistance of the device.
Example 6:
fig. 6 is a schematic structural diagram of a lateral diffusion mosfet of embodiment 6, which is different from embodiment 5 mainly in that a channel region 203a is also provided in the drift region 202 below the first field oxide layer 204 in addition to the channel region 203 between the first field oxide layer 204 and the second field oxide layer 204a (the source region is provided in the channel region 203). The channel region 203a is provided to assist the depletion of the drift region 202, so as to increase the N-type impurity concentration in the drift region 202 and reduce the on-resistance of the device.
In the present embodiment, the channel region 203 and the channel region 203a are formed in the same step, so as to save the manufacturing process and the number of photolithography masks.
Example 7:
fig. 7 is a schematic structural diagram of a lateral diffused metal oxide semiconductor field effect transistor in example 7, which is different from example 6 mainly in that the channel region 203a is a plurality of discrete structures. Since the need for depletion of the auxiliary drift region 202 is greater closer to the source region, in other words, the need for depletion of the auxiliary drift region 202 is lower closer to the drain region 210, the channel region 203a does not need to be provided with a strip as in embodiment 6, but a structure in which the doping concentration (i.e., the concentration of the P-type impurity) gradually decreases from the source region to the drain region 210 may be provided as the corresponding channel region. In consideration of implementation difficulty in manufacturing, the channel regions 203a of the discrete structures may be disposed more densely as the discrete structures are closer to the source region. In particular, when fabricating the reticle, a plurality of stripe-shaped windows may be disposed as the implantation windows of the channel region 203a, and the closer the implantation windows are to the drain region 210, the longer the length and the longer the distance therebetween are. P-type ions are implanted into the window and then thermally diffused to obtain the channel region 203a shown in fig. 7.
Example 8:
fig. 8 is a schematic structural diagram of a lateral diffused metal oxide semiconductor field effect transistor in embodiment 8, which is mainly different from embodiment 5 in that a buried oxide layer 213 is disposed in a drift region 202 below a first field oxide layer 204. The buried oxide layer 213 also serves to assist depletion of the drift region 202, thereby increasing the N-type impurity concentration in the drift region 202 and reducing the on-resistance of the device.
The technical features of the embodiments described above may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the embodiments described above are not described, but should be considered as being within the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above-mentioned embodiments only express several embodiments of the present invention, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the inventive concept, which falls within the scope of the present invention. Therefore, the protection scope of the present patent shall be subject to the appended claims.

Claims (5)

1. A laterally diffused metal oxide semiconductor field effect transistor is characterized by comprising a substrate of a second conduction type, a drift region of the first conduction type on the substrate, a channel region of the second conduction type on the substrate, a drain region of the first conduction type on the surface of the drift region, a source region on the surface of the channel region, a first field oxide layer between the drain region and the source region, and a second field oxide layer positioned on one side, far away from the drain region, of the channel region, wherein an isolation trench penetrating downwards into the substrate from the second field oxide layer is further arranged in the laterally diffused metal oxide semiconductor field effect transistor, the conductivity of a filler in the isolation trench is smaller than that of the substrate, the drift region and the channel region, and the first conduction type and the second conduction type are opposite conduction types; the channel region comprises a first channel region positioned between the first field oxide layer and the second field oxide layer and a second channel region positioned below the first field oxide layer and in the drift region, the source region comprises a first conduction type doping region and a second conduction type doping region, and the first conduction type doping region and the second conduction type doping region are arranged in the first channel region; the second channel region is a plurality of discrete structures, and the discrete structures are arranged more densely closer to the source region; the first channel region and the second channel region are manufactured and formed in the same step; the lateral diffusion metal oxide semiconductor field effect transistor is further provided with a pressure-resistant groove which extends downwards from the surface of the drift region on one side, far away from the source region, of the drain region, the conductivity of fillers in the pressure-resistant groove is smaller than those of the substrate, the drift region and the channel region, and the top of the pressure-resistant groove is arranged between the drain region and a third field oxide layer on one side, far away from the source region, of the drain region.
2. The LDMOS transistor of claim 1, wherein the filler in the isolation trench is polysilicon or an oxide layer.
3. The ldmos field effect transistor of claim 1 wherein said channel region is formed on a surface of said drift region, said isolation trench extends down through said drift region and into said substrate, said first conductivity type doped region is closer to said first field oxide layer than said second conductivity type doped region, and said ldmos field effect transistor further comprises a gate extending from above said first conductivity type doped region to above said first field oxide layer.
4. The ldmos field effect transistor of claim 1 further including a buried oxide layer in the drift region below the first field oxide layer.
5. The ldmos field effect transistor (mosfet) as claimed in claim 1 wherein said withstand voltage trench and said isolation trench are fabricated in the same step.
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CN112309865B (en) * 2019-08-01 2022-10-18 无锡华润上华科技有限公司 Lateral diffusion metal oxide semiconductor device and manufacturing method thereof
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