CN103915503A - Lateral high voltage MOS device and manufacturing method thereof - Google Patents
Lateral high voltage MOS device and manufacturing method thereof Download PDFInfo
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- 238000005516 engineering process Methods 0.000 claims description 30
- 238000000034 method Methods 0.000 claims description 27
- 238000005468 ion implantation Methods 0.000 claims description 25
- 238000001259 photo etching Methods 0.000 claims description 19
- 239000012535 impurity Substances 0.000 claims description 17
- 238000000407 epitaxy Methods 0.000 claims description 12
- 238000001459 lithography Methods 0.000 claims description 6
- 238000002347 injection Methods 0.000 abstract description 12
- 239000007924 injection Substances 0.000 abstract description 12
- 210000003850 cellular structure Anatomy 0.000 abstract 1
- 238000003475 lamination Methods 0.000 abstract 1
- 239000002184 metal Substances 0.000 description 26
- 238000002513 implantation Methods 0.000 description 13
- 230000008094 contradictory effect Effects 0.000 description 8
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- 230000011218 segmentation Effects 0.000 description 3
- 230000015556 catabolic process Effects 0.000 description 2
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- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
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- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
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- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
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- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
- H01L29/7823—Lateral DMOS transistors, i.e. LDMOS transistors with an edge termination structure
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Abstract
The invention relates to the technical field of semiconductor power devices, in particular to a lateral high voltage MOS device and a manufacturing method thereof. A cellular structure of the lateral high voltage MOS device comprises a first conductive type semiconductor substrate, a second conductive type semiconductor injection drift region, a source region and a drain region, wherein the second conductive type semiconductor injection drift region, the source region and the drain region are arranged on the first conductive type semiconductor substrates. A second conductive type semiconductor extending-out drift region is further arranged on the second conductive type semiconductor injection drift region, the source region and the drain region are respectively arranged on the upper end face of the second conductive type semiconductor extending-out drift region, and the second conductive type semiconductor is formed by a plurality of second conductive type semiconductor extending-out drift region bodies sequentially arranged from bottom to top in a lamination mode. The lateral high voltage MOS device has the advantages that on-resistance of the device is greatly reduced, and the conflict relation between the on-resistance and voltage resistance is relieved. The lateral high voltage MOS device is particularly applied to the field of lateral high voltage MOS devices.
Description
Technical field
The present invention relates to semiconductor power device technology field, relate to a kind of lateral MOS high tension apparatus and manufacture method thereof.
Background technology
Lateral high-voltage device is that high-voltage power integrated circuit develops requisite part, and high voltage power device requires to have high puncture voltage, low conducting resistance and low switching loss.Lateral high-voltage device is realized high puncture voltage, requires it to have long size and low doping content for bearing withstand voltage drift region, but in order to meet device low on-resistance, requires again to have high doping content as the drift region of current channel.At power LDMOS(Latral Double-diffused MOSFET) in device design, puncture voltage (Breakdown Voltage, BV) and conduction resistance (Specific on-resistance, R
on, sp) there is contradictory relation.Device is in the time of high-voltage applications, and conducting resistance sharply rises, and has limited the application of high tension apparatus in high-voltage power integrated circuit, especially requires the circuit of low conduction loss and little chip area.In order to overcome the problem of high conducting resistance, the people such as J.A.APPLES have proposed RESURF(Reduced SURface Field) reduction surface field technology, be widely used in high tension apparatus, although effectively reduced conducting resistance, the contradictory relation of puncture voltage and conducting resistance still needs further improvement.
Summary of the invention
To be solved by this invention, it is exactly the problem existing for above-mentioned traditional lateral high-voltage device, propose a kind ofly keeping high-breakdown-voltage in the situation that, can reducing greatly device conduction resistance, reduce transverse high-voltage MOS device and the manufacture method thereof of the power consumption of device.
The present invention solves the problems of the technologies described above adopted technical scheme: a kind of transverse high-voltage MOS device, as shown in Figure 2, its structure cell comprises the first conductive type semiconductor substrate, the second conductive type semiconductor being arranged in the first conductive type semiconductor substrate injects drift region and source region and drain region, it is characterized in that, inject on drift region and be also provided with the second conductive type semiconductor extension drift region at the second conductive type semiconductor, described source region and drain region are separately positioned on the second upper surface, conductive type semiconductor extension drift region, described the second conductive type semiconductor extension drift region is made up of multiple the second sub-drift regions of conductive type semiconductor extension that are cascading from bottom to top, injecting drift region and each the second sub-drift region of conductive type semiconductor extension at the second conductive type semiconductor is provided with 2 and falls a layer.
A manufacture method for transverse high-voltage MOS device, is characterized in that, comprises the following steps:
A. adopt photoetching and ion implantation technology, in the first conductive type semiconductor substrate, inject the second conductive type semiconductor impurity, diffuse to form the second conductive type semiconductor and inject drift region, adopt Twi-lithography and ion implantation technology, inject drift region at the second conductive type semiconductor and inject the first conductive type semiconductor impurity, diffuse to form 2 independently the first conductive type semiconductor inject and fall layer;
B. adopt epitaxy technique, inject epitaxial growth the second sub-drift region of conductive type semiconductor extension on drift region at the second conductive type semiconductor, adopt Twi-lithography and ion implantation technology, in the second sub-drift region of conductive type semiconductor extension, inject the first conductive type semiconductor impurity, form 2 the first separate conduction type extensions and fall a layer;
C. adopt epitaxy technique next layer second sub-drift region of conductive type semiconductor extension of epitaxial growth on the second sub-drift region of conductive type semiconductor extension in top device, adopt Twi-lithography and ion implantation technology, in lower one deck second sub-drift region of conductive type semiconductor extension of new growth, inject the first conductive type semiconductor impurity, form 2 the first separate conduction type extensions and fall layer, after repeating step c many times, enter steps d;
D. on the second sub-drift region of conductive type semiconductor extension on device top, make device source region and drain region.
Beneficial effect of the present invention is, greatly reduce the conducting resistance of device, alleviate conduction resistance and withstand voltage contradictory relation, compared with traditional lateral high-voltage device, lateral high-voltage device provided by the invention has less conducting resistance in the situation that of identical chips area.
Accompanying drawing explanation
Fig. 1 is the structural representation of traditional lateral high-voltage device;
Fig. 2 is the structural representation of the lateral high-voltage device of embodiment 1;
Fig. 3 is the structural representation of the lateral high-voltage device of embodiment 2;
Fig. 4 is the structural representation of the lateral high-voltage device of embodiment 3;
Fig. 5 is the structural representation of the lateral high-voltage device of embodiment 4;
Fig. 6 is the structural representation of the lateral high-voltage device of embodiment 5;
Fig. 7 is the structural representation of the lateral high-voltage device of embodiment 6;
Fig. 8 is the schematic flow sheet of the manufacture method of transverse high-voltage MOS device of the present invention;
Fig. 9 is the structural representation of the lateral high-voltage device of embodiment 7;
Figure 10 is the process flow diagram of the manufacture method of embodiment 7;
Figure 11 is the potential profile of traditional lateral high-voltage device while puncturing;
Figure 12 is the potential profile of the lateral high-voltage device of embodiment 7 while puncturing;
Figure 13 is in the time of gate source voltage Vgs=6V, traditional lateral high-voltage device and a kind of transverse high-voltage MOS device provided by the invention in the time of linear zone, the relation curve schematic diagram of drain-source current and drain-source voltage.
Embodiment
Below in conjunction with drawings and Examples, describe technical scheme of the present invention in detail:
Main technical schemes of the present invention, it is the structure that traditional drift region structure is made as to stack formation drift region, multilayer drift region, object is in the time of device ON state, and multiple drift regions provide many low-resistance current channels for device, thereby have greatly reduced the conducting resistance of device; When OFF state, in each drift region, fall a layer assisted depletion drift region, thereby improve the puncture voltage of device, alleviate conduction resistance and withstand voltage contradictory relation.
As shown in Figure 1, for traditional lateral high-voltage device section of structure, device is integrated on the first conductive type semiconductor substrate 1, comprises that the second conductive type semiconductor injection drift region 20, the first conductive type semiconductor tagma 3, the first conductive type semiconductor first inject and fall a layer 51, field oxide 5, the front medium 6 of metal, gate oxide 7, polygate electrodes 8, the second conductive type semiconductor drain region 9, the second conductive type semiconductor source region 10, the first conductive type semiconductor body contact zone 11, source metal 12, drain metal 13; First described conductive type semiconductor the first injection is fallen a layer 51 and is surrounded by the second conductive type semiconductor injection drift region 20; Between polygate electrodes 8, source metal 12 and drain metal 13, mutually isolate by medium 6 before metal.When OFF state, the first conductive type semiconductor first injects and falls a layer 51 and first conductive type semiconductor substrate 1 assisted depletion the second conductive type semiconductor injection drift region 20, improves device electric breakdown strength.
Embodiment 1:
As shown in Figure 2, this routine lateral high-voltage device is integrated on the first conductive type semiconductor substrate 1, comprise that the second conductive type semiconductor injects drift region 20, second conductive type semiconductor the first extension drift region 21, second conductive type semiconductor the second extension drift region 22, the second conductive type semiconductor i extension drift region 2i, the first conductive type semiconductor tagma 3, a layer 41 falls in first conductive type semiconductor the first extension, a layer 42 falls in first conductive type semiconductor the second extension, layer 4 (2i) falls in the first conductive type semiconductor 2i extension, the first conductive type semiconductor first injects and falls a layer 51, the first conductive type semiconductor second injects and falls a layer 52, field oxide 5, medium 6 before metal, gate oxide 7, polygate electrodes 8, the second conductive type semiconductor drain region 9, the second conductive type semiconductor source region 10, the first conductive type semiconductor body contact zone 11, source metal (12), drain metal (13), the first described conductive type semiconductor 2i-1 extension is fallen layer 4 (2i-1) and the first conductive type semiconductor 2i extension and is fallen layer 4 (2i) and surrounded by the second conductive type semiconductor i drift region 2i, field oxide 5 is positioned at the second 2i surface, conductive type semiconductor i drift region, and its top is medium 6 before metal, the first conductive type semiconductor tagma 3 is surrounded by the second conductive type semiconductor i drift region 2i, the second conductive type semiconductor drain region 9 is connected with drain metal 13, is surrounded by the second conductive type semiconductor i drift region 2i, the second conductive type semiconductor source region 10 is positioned at side by side 3 surfaces, the first conductive type semiconductor tagma, is connected with source metal 12 with the first conductive type semiconductor body contact zone 11, between polygate electrodes 8, source metal 13 and drain metal 14, mutually isolate by medium 6 before metal.。
This routine operation principle is: based on Implantation, in the first conductive type semiconductor substrate 1, form the second conductive type semiconductor device and inject drift region 20, adopt epitaxy technique to form second conductive type semiconductor the first drift region 21, second conductive type semiconductor the second drift region 22, the second conductive type semiconductor i drift region 2i, simultaneously, adopt ion implantation technology in drift region, to realize first conductive type semiconductor the first extension and fall a layer 41, a layer 42 falls in first conductive type semiconductor the second extension, layer 4 (2i) falls in the first conductive type semiconductor 2i extension, the first conductive type semiconductor first injects and falls a layer 51 and the first conductive type semiconductor second and inject and fall a layer 52.Compared with traditional lateral high-voltage device structure, a layer structure falls in multilayer has increased the concentration of the second conductive type semiconductor drift region.When ON state, the second conductive type semiconductor drift region of high concentration, for high tension apparatus provides a large amount of majority carriers, has formed multiple low-resistance current channels, greatly reduces break-over of device resistance, thereby reduces greatly process costs.When OFF state, drain metal 13 adds high pressure, the first conductive type semiconductor fall layer (41,42 ..., 4 (2i), 51,52) and first conductive type semiconductor substrate 1 assisted depletion the second conductive type semiconductor drift region (20,21 ..., 2i), improve the puncture voltage of device, alleviate conduction resistance and withstand voltage contradictory relation in lateral high-voltage device.Therefore,, in power integrated circuit application, under the condition of same output current ability, the area of high-voltage semi-conductor device is minimized.
Embodiment 2:
As shown in Figure 3, the place that this example is different from embodiment 1 is, last epitaxy technique is realized after the second conductive type semiconductor 2i extension drift region 4 (2i), only adopt a photoetching and ion implantation technology to realize the first conductive type semiconductor 2i-1 extension and fall layer 4 (2i-1), its operation principle and effect are identical with embodiment 1.
Embodiment 3:
As shown in Figure 4, the place that this example is different from embodiment 1 is, after realizing the second conductive type semiconductor drift region at every turn, only adopt a photoetching and ion implantation technology realize the first conductive type semiconductor first inject fall a layer 51, the first conductive type semiconductor extension fall a layer (41,43 ..., 4 (2i-1)), its operation principle and effect are identical with embodiment 1.
Embodiment 4:
As shown in Figure 5, the place that this example is different from embodiment 1 is, the first conductive type semiconductor inject fall layer (51,52) and the first conductive type semiconductor extension fall layer (41,42 ..., 4 (2i)) adopt segmentation window to inject, along with close to the second conductive type semiconductor drain region (9), injection window pitch reduces, and it is constant to inject window size, its operation principle and effect are identical with embodiment 1.
Embodiment 5:
As shown in Figure 6, the place that this example is different from embodiment 1 is, the first conductive type semiconductor inject fall layer (51,52) and the first conductive type semiconductor extension fall layer (41,42 ..., 4 (2i)) adopt segmentation window to inject, along with close to the second conductive type semiconductor drain region (9), injection window pitch is constant, increase and inject window size, its operation principle and effect are identical with embodiment 1.
Embodiment 6:
As shown in Figure 7, the place that this example is different from embodiment 1 is, field oxide 5 adopts shallow-trench isolation (STI) technology to realize, and its operation principle and effect are identical with embodiment 1.
As shown in Figure 8, be the schematic flow sheet of the manufacture method of lateral high-voltage device of the present invention, specifically comprise the following steps:
The 1st step: adopt photoetching and ion implantation technology, inject the second conductive type semiconductor impurity in the first conductive type semiconductor substrate 1, diffuse to form the second conductive type semiconductor and inject drift region 20; The resistivity of described the first conductive type semiconductor substrate 1 is 10～200 ohmcms, and the implantation dosage that the second conductive type semiconductor injects drift region 20 is 1E12cm
-2～1E13cm
-2;
The 2nd step: adopt photoetching and ion implantation technology, inject drift region 20 at the second conductive type semiconductor and inject the first conductive type semiconductor impurity, diffuse to form the first conductive type semiconductor first and inject and fall a layer 51 and the first conductive type semiconductor second and inject and fall a layer 52; Described the first conductive type semiconductor first injects and falls a layer 51 and the second conductive type semiconductor second and inject that to fall an implantation dosage for layer 52 be 1E11cm
-2～2E13cm
-2;
The 3rd step: adopt epitaxy technique, inject epitaxial growth second conductive type semiconductor the first extension drift region 21 on drift region 20 at the second conductive type semiconductor; The resistivity of described second conductive type semiconductor the first extension drift region 21 is 0.5～10 ohmcm;
The 4th step: adopt photoetching and ion implantation technology, in second conductive type semiconductor the first extension drift region 21, inject the first conductive type semiconductor impurity, diffuse to form that layer 41 falls in first conductive type semiconductor the first extension and a layer 42 falls in first conductive type semiconductor the second extension; Layer 41 and second conductive type semiconductor the second extension fall in described first conductive type semiconductor the first extension, and to fall an implantation dosage for layer 42 be 1E11cm
-2～2E13cm
-2;
……
2i+1 step: adopt epitaxy technique, at upper epitaxial growth the second conductive type semiconductor i extension drift region 2i of the second conductive type semiconductor i-1 extension drift region 2 (i-1); The resistivity of described the second conductive type semiconductor i extension drift region 2i is 0.5～10 ohmcm;
2i+2 step: adopt photoetching and ion implantation technology, in the second conductive type semiconductor i extension drift region 2i, inject the first conductive type semiconductor impurity, diffuse to form that layer 4 (2i-1) fall in the first conductive type semiconductor 2i-1 extension and layer 4 (2i) falls in the first conductive type semiconductor 2i extension; Layer 4 (2i) and the first conductive type semiconductor 2i extension fall in described the first conductive type semiconductor 2i extension, and to fall an implantation dosage of layer 4 (2i) be 1E11cm
-2～2E13cm
-2.
The source region of MOS device of the present invention and the manufacture method in drain region are:
2i+3 step: adopt photoetching and ion implantation technology, inject the first conductive type semiconductor impurity in the second conductive type semiconductor i drift region 2i, form the first conductive type semiconductor tagma 3; The implantation dosage in described the first conductive type semiconductor tagma 3 is 1E12cm
-2～5E13cm
-2;
2i+4 step: form field oxide 5;
2i+5 step: form the gate oxide 7 of device, the thickness of described gate oxide 7 is 7nm～100nm;
2i+6 step: form the polygate electrodes 8 of device, the square resistance of described polysilicon gate 8 is 10～40 ohms/square;
2i+7 step: adopt photoetching and ion implantation technology, form the second conductive type semiconductor drain region 9, the second conductive type semiconductor source region 10, the first conductive type semiconductor body contact zone 11 of device; The implantation dosage of described the second conductive type semiconductor drain region 9, the second conductive type semiconductor source region 10, the first conductive type semiconductor body contact zone 11 is 1E13cm
-2～2E16cm
-2;
2i+8 step: deposit forms the front medium 6 of metal;
2i+9 step: form source metal 12 and drain metal 13.
It should be noted that:
In (1) the 1st step, adopt photoetching and ion implantation technology in the first conductive type semiconductor substrate 1, to realize the second conductive type semiconductor and inject drift region 20, can reduce a step epitaxy technique and extension manufacturing cost.
(2) the last time after epitaxy technique, only adopt a photoetching and ion implantation technology in the second conductive type semiconductor i extension drift region 2i, realize the first conductive type semiconductor 2i-1 extension and fall layer 4 (2i-1) structure.
(3) form at every turn drift region (20,21 ..., 2i) afterwards, can also only adopt a photoetching and ion implantation technology realize the first conductive type semiconductor extension fall layer (51,41,43 ..., 4 (2i-1)).
(4) the first described conductive type semiconductor fall a layer (51,52,41 ..., 4 (2i)) can adopt segmentation window inject; Along with close to the second conductive type semiconductor drain region 9, fall layer and inject a window pitch and reduce, and it is constant to inject window size, or falling a layer, to inject window pitch constant, increases and inject window.
(5) field oxide 5 can adopt silicon selective oxidation (LOCOS) technology, also can adopt shallow-trench isolation (STI) technique to realize.
(6) can in the first conductive type semiconductor tagma 3, form the first conductive type semiconductor buried regions, between the first conductive type semiconductor tagma 3 and the second conductive type semiconductor i extension drift region 2i, this buried regions can be avoided the parasitic transistor conducting of source, improves the reliability of device.
Embodiment 7:
As shown in Figure 9, the transverse high-voltage MOS device section of structure that this is routine, device is integrated on the first conductive type semiconductor substrate 1, comprise that the second conductive type semiconductor injects drift region 20, second conductive type semiconductor the first extension drift region 21, the first conductive type semiconductor tagma 3, a layer 41 falls in first conductive type semiconductor the first extension, the first conductive type semiconductor first injects and falls a layer 51, field oxide 5, medium 6 before metal, gate oxide 7, polygate electrodes 8, the second conductive type semiconductor drain region 9, the second conductive type semiconductor source region 10, the first conductive type semiconductor body contact zone 11, source metal 12, drain metal 13.When ON state, the second conductive type semiconductor injection drift region 20 of high concentration and second conductive type semiconductor the first extension drift region 21, for high tension apparatus provides three low-resistance current channels, greatly reduce break-over of device resistance.When OFF state, drain metal 13 adds high pressure, a layer 41 falls in first conductive type semiconductor the first extension, a layer 51 is fallen in first conductive type semiconductor the first injection and first conductive type semiconductor substrate 1 assisted depletion the second conductive type semiconductor injects drift region 20 and second conductive type semiconductor the first extension drift region 21, improve the puncture voltage of device, alleviated conduction resistance and withstand voltage contradictory relation in lateral high-voltage device.
As shown in figure 10, be the manufacturing process of this routine device:
The 1st step: adopt Implantation and photoetching process, inject the second conductive type semiconductor impurity in the first conductive type semiconductor substrate 1, diffuse to form the second conductive type semiconductor and inject drift region 20; The resistivity of described the first conductive type semiconductor substrate 1 is 10～200 ohmcms, and the resistivity that the second conductive type semiconductor injects drift region 20 is 0.5～10 ohmcm;
The 2nd step: adopt photoetching and ion implantation technology, inject drift region 20 at the second conductive type semiconductor and inject the first conductive type semiconductor impurity, form first conductive type semiconductor the first injection and fall a layer 51; Described the first conductive type semiconductor first injects and falls an implantation dosage for layer 51 is 1E11cm
-2～2E13cm
-2;
The 3rd step: adopt epitaxy technique, inject epitaxial growth second conductive type semiconductor the first extension drift region 21 on drift region 20 at the second conductive type semiconductor; The resistivity of described second conductive type semiconductor the first extension drift region 21 is 0.5～10 ohmcm;
The 4th step: adopt photoetching and ion implantation technology, inject the first conductive type semiconductor impurity in second conductive type semiconductor the first extension drift region 21, form first conductive type semiconductor the first extension and fall a layer 41; It is 1E11cm that an implantation dosage for layer 41 falls in described first conductive type semiconductor the first extension
-2～2E13cm
-2;
Described transverse high-voltage MOS device, other processing steps of its preparation method are as follows:
The 5th step: adopt photoetching and ion implantation technology, inject the first conductive type semiconductor impurity in second conductive type semiconductor the first extension drift region 21, form the first conductive type semiconductor tagma 3; The implantation dosage in described the first conductive type semiconductor tagma 3 is 1E12cm
-2～5E13cm
-2;
The 6th step: form field oxide 5;
The 7th step: form the gate oxide 7 of device, the thickness of described gate oxide 7 is 7nm～100nm;
The 8th step: form the polygate electrodes 8 of device, the square resistance of described polysilicon gate 8 is 10～40 ohms/square;
The 9th step: adopt photoetching and ion implantation technology, form the second conductive type semiconductor drain region 9, the second conductive type semiconductor source region 10, the first conductive type semiconductor body contact zone 11 of device; The implantation dosage of described the second conductive type semiconductor drain region 9, the second conductive type semiconductor source region 10, the first conductive type semiconductor body contact zone 11 is 1E13cm
-2～2E16cm
-2;
The 10th step: deposit forms the front medium 6 of metal;
The 11st step: form source metal 12 and drain metal 13.
Figure 11 and Figure 12 are the potential profiles while adopting traditional lateral high-voltage device of two-dimentional process simulation software Tsuprem4 definition and a kind of transverse high-voltage MOS device provided by the invention to puncture, wherein, Figure 11 is the potential profile that traditional structure Fig. 1 is corresponding, and Figure 12 is the potential profile of embodiment 7 correspondences.The second conductive type semiconductor injects length 70um, the dosage 4.0E12cm of drift region 20
-2, energy 120Kev, traditional structure the first conductive type semiconductor first injects and falls a layer 51 dosage 2.7E12cm
-2, energy 1150Kev, structure of the present invention the first conductive type semiconductor first injects and falls a layer 51 dosage 3.2E12cm
-2, energy 1150Kev, 4 microns of second conductive type semiconductor the first extension drift region 21 resistivity 1.1 ohmcms, thickness, a layer 41 dosage 2E12cm fall in first conductive type semiconductor the first extension
-2, energy 1150Kev.Simulation architecture discovery, traditional lateral high-voltage device and lateral high-voltage device provided by the invention have all reached large puncture voltage, are respectively 801.3V and 801.8V.
Figure 13 is traditional lateral high-voltage device and a kind of transverse high-voltage MOS device provided by the invention that adopts two-dimentional process simulation software Tsuprem4 definition, in the time of gate source voltage Vgs=6V, and the relation curve schematic diagram of drain-source current and drain-source voltage.Wherein, dotted line is traditional lateral high-voltage device drain-source current and drain-source voltage relation curve, the drain-source current that solid line is a kind of transverse high-voltage MOS device provided by the invention and drain-source voltage relation curve.As seen from the figure, in the time of drain-source voltage Vds=10V, the electric current of traditional lateral high-voltage device is 43.5 μ A/ μ m; Simulation result shows that device current provided by the invention is 55.5 μ A/ μ m, and current capacity has improved 27.58% compared with traditional structure.Visible, transverse high-voltage MOS device provided by the invention, in keeping height withstand voltage, has lower conduction resistance, has therefore greatly alleviated the contradictory relation of high tension apparatus conduction resistance and puncture voltage.
The present invention by Implantation and epitaxy technique on the first conductive type semiconductor substrate 1, realize the second conductive type semiconductor inject drift region 20 and the second conductive type semiconductor extension drift region (21,22 ..., 2i), by photoetching and ion implantation technology, realize the first conductive type semiconductor inject fall layer (51,52) and the first conductive type semiconductor fall layer (41,42 ..., 4 (2i)).When ON state, the second conductive type semiconductor drift region, for device provides many low-resistance current channels, has greatly reduced the conducting resistance of device.When OFF state, layer and a first conductive type semiconductor substrate-assisted depletion second conductive type semiconductor drift region fall in the first conductive type semiconductor, improve the puncture voltage of device, alleviate conduction resistance and withstand voltage contradictory relation.Therefore, lateral high-voltage device provided by the invention has less conducting resistance (or having less chip area in the case of identical ducting capacity) in the situation that of identical chips area.
Claims (2)
1. a transverse high-voltage MOS device, its structure cell comprises the first conductive type semiconductor substrate, the second conductive type semiconductor being arranged in the first conductive type semiconductor substrate injects drift region and source region and drain region, it is characterized in that, inject on drift region and be also provided with the second conductive type semiconductor extension drift region at the second conductive type semiconductor, described source region and drain region are separately positioned on the second upper surface, conductive type semiconductor extension drift region, described the second conductive type semiconductor extension drift region is made up of multiple the second sub-drift regions of conductive type semiconductor extension that are cascading from bottom to top, injecting drift region and each the second sub-drift region of conductive type semiconductor extension at the second conductive type semiconductor is provided with 2 and falls a layer.
2. a manufacture method for transverse high-voltage MOS device, is characterized in that, comprises the following steps:
A. adopt photoetching and ion implantation technology, in the first conductive type semiconductor substrate, inject the second conductive type semiconductor impurity, diffuse to form the second conductive type semiconductor and inject drift region, adopt Twi-lithography and ion implantation technology, inject drift region at the second conductive type semiconductor and inject the first conductive type semiconductor impurity, diffuse to form 2 independently the first conductive type semiconductor inject and fall layer;
B. adopt epitaxy technique, inject epitaxial growth the second sub-drift region of conductive type semiconductor extension on drift region at the second conductive type semiconductor, adopt Twi-lithography and ion implantation technology, in the second sub-drift region of conductive type semiconductor extension, inject the first conductive type semiconductor impurity, form 2 the first separate conduction type extensions and fall a layer;
C. adopt epitaxy technique next layer second sub-drift region of conductive type semiconductor extension of epitaxial growth on the second sub-drift region of conductive type semiconductor extension in top device, adopt Twi-lithography and ion implantation technology, in lower one deck second sub-drift region of conductive type semiconductor extension of new growth, inject the first conductive type semiconductor impurity, form 2 the first separate conduction type extensions and fall layer, after repeating step c many times, enter steps d;
D. on the second sub-drift region of conductive type semiconductor extension on device top, make device source region and drain region.
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