CN102231390B - Vertical double-diffused metal oxide semiconductor power device with super junction structure - Google Patents
Vertical double-diffused metal oxide semiconductor power device with super junction structure Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 118
- 229910044991 metal oxide Inorganic materials 0.000 title claims abstract description 16
- 150000004706 metal oxides Chemical class 0.000 title claims abstract description 16
- 230000007704 transition Effects 0.000 claims abstract description 27
- 239000000463 material Substances 0.000 claims abstract description 26
- 230000001413 cellular effect Effects 0.000 claims description 22
- 239000003989 dielectric material Substances 0.000 claims description 18
- 239000002184 metal Substances 0.000 claims description 17
- 239000000758 substrate Substances 0.000 claims description 13
- 238000009792 diffusion process Methods 0.000 claims description 10
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 4
- 229920005591 polysilicon Polymers 0.000 claims description 4
- 230000005684 electric field Effects 0.000 abstract description 19
- 238000009826 distribution Methods 0.000 abstract description 10
- 230000015556 catabolic process Effects 0.000 abstract description 6
- 230000009286 beneficial effect Effects 0.000 abstract description 2
- 238000009827 uniform distribution Methods 0.000 abstract 1
- 230000000694 effects Effects 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
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Abstract
The invention relates to the technical field of semiconductor devices, in particular to a vertical double-diffused metal oxide semiconductor power device with a super junction structure. The vertical double-diffused metal oxide semiconductor power device comprises a cell region I, a transition region II and a terminal region III, wherein the transition region II surrounds the cell region, and the terminal region III surrounds the transition region. The vertical double-diffused metal oxide semiconductor power device is characterized in that an insulating medium material is arranged at the bottom of a second conduction type cylindrical semiconductor region in the cell region I. The invention has the beneficial effects that the distribution of an electric field is close to ideal uniform distribution, a breakdown voltage of a practical super junction structure device is increased and performances of the device are further improved according to the vertical double-diffused metal oxide semiconductor power device with the improved super junction structure.
Description
Technical field
The present invention relates to technical field of semiconductor device, relate in particular to a kind of longitudinal double diffusion metal oxide semiconductor power device of super-junction structure.
Background technology
Power device is widely used in fields such as Switching Power Supply, automotive electronics, Industry Control at present; Longitudinal double diffusion metal oxide semiconductor field effect transistor (Vertical Double-diffused MOSFET; Be called for short VDMOS); Compare with traditional bipolar power transistor and to have many premium properties; As input impedance is high, switching speed is fast, operating frequency is high, voltage control property is good, Heat stability is good, does not have characteristics such as second breakdown, be comparatively excellent power device.Especially the invention of super-junction structure VDMOS, it has overcome the contradiction of conventional power VDMOS conducting resistance and puncture voltage; It has changed conventional power VDMOS device and has relied on the withstand voltage structure of drift layer, adopts a kind of " super-junction structure "---the form that P type, N type silicon semiconductor material are alternately arranged in the drift region each other.This structure has been improved puncture voltage and the difficult situation about taking into account simultaneously of conducting resistance, both can improve puncture voltage, reduces conducting resistance again.Because this unique device structure of super-junction structure VDMOS makes its electrical property obviously be superior to conventional power VDMOS, therefore this technology is called the technical milestone of power metal oxide semiconductor field-effect transistor by people.
Be illustrated in figure 1 as the cellular structural representation of conventional power VDMOS device, N type epitaxial loayer is drawn through backplate, as drain electrode (Drain); P-body draws through surperficial P+, n+, as source electrode (Source); Epitaxial loayer between the P-body is provided with gate electrode, and has dielectric at interval between N type epitaxial loayer.When device is operated in off-state, source ground, drain electrode adds positive voltage, and institute's making alive is mainly born by the PN junction that the P-body/N extension forms; Along with alive increase, electric field increases; When the electric field peak reached breakdown electric field Ec, device just punctured; When Fig. 2 is a device breakdown shown in Figure 1 along the Electric Field Distribution at a-c place.Can be known that by Semiconductor Physics voltage is the integration of electric field, therefore, the area of the dash area among Fig. 2 is exactly the value of puncture voltage.
Be illustrated in figure 3 as the cellular structural representation of the POWER VD MOS device of super-junction structure; Under the ideal situation in theory, as shown in Figure 4 along the Electric Field Distribution at a-b-c place when it punctures, its electric field becomes evenly to distribute; Same, the area of dash area is exactly the value of its puncture voltage among Fig. 4.Because the value of breakdown electric field Ec is a basic fixed; Therefore; Comparison diagram 2 can be known with Fig. 4; Obviously greater than the area of dash area among Fig. 2, promptly under the same terms such as identical doping content, the puncture voltage of the POWER VD MOS device of super-junction structure can be higher than the puncture voltage of conventional power VDMOS device far away to the area of dash area among Fig. 4.
But, in actual at present technology,, can the influence of Electric Field Distribution output be made to reach ideal uniform electric field shown in Figure 4 owing to there is a kind of N+ substrate depletion effect, promptly can't reach desirable puncture voltage; Be embodied in, can produce a peak electric field with N type extension intersection (b place among Fig. 3) in P type cylindrical region bottom, thereby make puncture voltage to descend to some extent than ideal situation; The Electric Field Distribution of technology is as shown in Figure 5 at present, and the area of electric field dash area reduces than Fig. 4 to some extent among the figure, explains that puncture voltage is not enough to some extent.
Summary of the invention
The present invention is directed to the deficiency of prior art; A kind of longitudinal double diffusion metal oxide semiconductor power device of super-junction structure has been proposed; Through having increased by an insulative material region in second conduction type column semiconductor region bottom; Eliminate this N+ substrate depletion effect, eliminated the peak electric field of P type cylindrical region bottom with N type extension intersection (b place among Fig. 3).
The present invention realizes through following technical scheme:
A kind of longitudinal double diffusion metal oxide semiconductor power device of super-junction structure comprises cellular region I and the transition region II of encirclement cellular region and the termination environment III of surrounding transition region;
Cellular region I and transition region II and termination environment III bottom and top are provided with metal level I 10 and metal level II 15; Bottom metal layers I 10 is provided with the first conductive type semiconductor material substrate 1; The first conductive type semiconductor material substrate 1 is provided with to be provided with in the first conductive type semiconductor material drift layer, 2, the first conductive type semiconductor material drift layers 2 is interrupted the discontinuous second conduction type column semiconductor region 3;
Be provided with the second conductive type semiconductor district I 4 on the second conduction type column semiconductor region 3 in the cellular region I; And the second conductive type semiconductor district I 4 is positioned at the first conductive type semiconductor material drift layer 2; In the second conductive type semiconductor district I 4, be provided with the second conduction type heavily-doped semiconductor district I 8 and the first conduction type heavily-doped semiconductor district I 7; Be provided with dielectric material I 6 in the second conduction type heavily-doped semiconductor district I 8 and the first conduction type heavily-doped semiconductor district I 7 above with exterior domain; Be provided with polysilicon gate 5 in the dielectric material I 6, on the first conduction type heavily-doped semiconductor district I 7 and the second conduction type heavily-doped semiconductor district I 8, be connected metal level II 15;
Be provided with the second conductive type semiconductor district II 9 in the first conductive type semiconductor material drift layer 2 in the transition region II; And the second conductive type semiconductor district II 9 has covered second whole in the transition region II conduction type column semiconductor regions 3; Be provided with the second conduction type heavily-doped semiconductor district II 14 in the second conductive type semiconductor district II 9 in the transition region II; The second conduction type heavily-doped semiconductor district II 14 is arranged in the top of the second conduction type column semiconductor region 3 adjacent with the cellular region I of transition region II; Be provided with dielectric material II 13 on the surface of transition region II, II 14 surfaces, the second conduction type heavily-doped semiconductor district in the second conductive type semiconductor district II 9 are provided with contact hole and link to each other with metal level II 15;
In the III of termination environment, be provided with the first conduction type heavily-doped semiconductor district II 12 in the upper right corner of the first conductive type semiconductor material substrate drift layer 2, the III surface is provided with dielectric material II 13 in the termination environment;
The second conduction type column semiconductor region, 3 bottoms in the described cellular region I are provided with dielectric material area 11.
As preferably, described first conduction type is that the n type mixes.
As preferably, described second conduction type is that the p type mixes.
Beneficial effect of the present invention: the present invention improves the longitudinal double diffusion metal oxide semiconductor power device structure of super-junction structure; Make the even distribution of Electric Field Distribution near ideal situation; Improve the puncture voltage of actual super-junction structure device, further improve the performance of device.
Description of drawings
Fig. 1 is the cellular structural representation of traditional POWER VD MOS device;
When Fig. 2 is a device breakdown shown in Figure 1 along the Electric Field Distribution at a-c place in Fig. 1 structure;
Fig. 3 is the cellular structural representation of the POWER VD MOS device of super-junction structure;
Fig. 4 thinks under the situation for the resonable reason of device shown in Figure 3, when it punctures along the Electric Field Distribution at a-b-c place in Fig. 3 structure;
Fig. 5 is a device shown in Figure 3 under existing actual techniques, when it punctures along the Electric Field Distribution at a-b-c place in Fig. 3 structure;
Fig. 6 is for being the structural representation of POWER VD MOS device of the present invention
The 1-first conductive type semiconductor material substrate
The 2-first conductive type semiconductor material substrate drift layer
The 3-second conduction type column semiconductor region
The 4-second conductive type semiconductor district I
The 5-polysilicon gate
6-dielectric material I
The 7-first conduction type heavily-doped semiconductor district I
The 8-second conduction type heavily-doped semiconductor district I
The 9-second conductive type semiconductor district II
10-metal level I
11-dielectric material area
The 12-first conduction type heavily-doped semiconductor district II
13-dielectric material II
The 14-second conduction type heavily-doped semiconductor district II
15-metal level II
Embodiment
As shown in Figure 6, a kind of longitudinal double diffusion metal oxide semiconductor power device of super-junction structure comprises cellular region I and the transition region II of encirclement cellular region and the termination environment III of surrounding transition region;
Cellular region I and transition region II and termination environment III bottom and top are provided with metal level I 10 and metal level II 15; Bottom metal layers I 10 is provided with n type doped semiconductor materials substrate 1; N type doped semiconductor materials substrate 1 is provided with n type doped semiconductor materials drift layer 2, is provided with in the n type doped semiconductor materials drift layer 2 to be interrupted discontinuous p type doping column semiconductor region 3;
Be provided with p type doped semiconductor area I 4 on the p type doping column semiconductor region 3 in the cellular region I; And p type doped semiconductor area I 4 is positioned at n type doped semiconductor materials drift layer 2; In p type doped semiconductor area I 4, be provided with p type heavily-doped semiconductor district I 8 and n type heavily-doped semiconductor district I 7; Be provided with dielectric material I 6 in p type heavily-doped semiconductor district I 8 and n type heavily-doped semiconductor district I 7 above with exterior domain; Be provided with polysilicon gate 5 in the dielectric material I 6, on n type heavily-doped semiconductor district I 7 and p type heavily-doped semiconductor district I 8, be connected metal level II 15;
Be provided with p type doped semiconductor area II 9 in the n type doped semiconductor materials drift layer 2 in the transition region II; And p type doped semiconductor area II 9 has covered p type doping column semiconductor regions 3 whole in the transition region II; Be provided with p type heavily-doped semiconductor district II 14 in the p type doped semiconductor area II 9 in the transition region II; P type heavily-doped semiconductor district II 14 is arranged in the top of the p type doping column semiconductor region 3 adjacent with the cellular region I of transition region II; Be provided with dielectric material II 13 on the surface of transition region II, II 14 surfaces, p type heavily-doped semiconductor district in p type doped semiconductor area II 9 are provided with contact hole and link to each other with metal level II 15;
In the III of termination environment, be provided with n type heavily-doped semiconductor district II 12 in the upper right corner of n type doped semiconductor materials substrate drift layer 2, the III surface is provided with dielectric material II 13 in the termination environment;
P type doping column semiconductor region 3 bottoms in the described cellular region I are provided with the dielectric material.
Above said be specific embodiment of the present invention and the know-why used, if the change of doing according to conception of the present invention, when the function that it produced does not exceed spiritual that specification and accompanying drawing contain yet, must belong to protection scope of the present invention.
Claims (3)
1. the longitudinal double diffusion metal oxide semiconductor power device of a super-junction structure comprises cellular region I and the transition region II of encirclement cellular region and the termination environment III of surrounding transition region;
Cellular region I and transition region II and termination environment III bottom are provided with metal level I (10); And the top is provided with metal level II (15); Bottom metal layers I (10) is provided with the first conductive type semiconductor material substrate (1); The first conductive type semiconductor material substrate (1) is provided with the first conductive type semiconductor material drift layer (2), is provided with in the first conductive type semiconductor material drift layer (2) to be interrupted the discontinuous second conduction type column semiconductor region (3);
Be provided with the second conductive type semiconductor district I (4) on the second conduction type column semiconductor region (3) in the cellular region I; And the second conductive type semiconductor district I (4) is positioned at the first conductive type semiconductor material drift layer (2); In the second conductive type semiconductor district I (4), be provided with the second conduction type heavily-doped semiconductor district I (8) and the first conduction type heavily-doped semiconductor district I (7); Be provided with dielectric material I (6) in the second conduction type heavily-doped semiconductor district I (8) and the first conduction type heavily-doped semiconductor district I (7) with the exterior domain top; Be provided with polysilicon gate (5) in the dielectric material I (6), on the first conduction type heavily-doped semiconductor district I (7) and the second conduction type heavily-doped semiconductor district I (8), be connected metal level II (15);
Be provided with the second conductive type semiconductor district II (9) in the first conductive type semiconductor material drift layer (2) in the transition region II; And the second conductive type semiconductor district II (9) has covered second whole in the transition region II conduction type column semiconductor regions (3); Be provided with the second conduction type heavily-doped semiconductor district II (14) in the second conductive type semiconductor district II (9) in the transition region II; The second conduction type heavily-doped semiconductor district II (14) is arranged in the top of the second conduction type column semiconductor region (3) adjacent with the cellular region I of transition region II; Be provided with dielectric material II (13) on the surface of transition region II, second conduction type heavily-doped semiconductor district II (14) surface in the second conductive type semiconductor district II (9) is provided with contact hole and links to each other with metal level II (15);
In the III of termination environment, be provided with the first conduction type heavily-doped semiconductor district II (12) in the upper right corner of the first conductive type semiconductor material substrate drift layer (2), the III surface is provided with dielectric material II (13) in the termination environment;
It is characterized in that the second conduction type column semiconductor region (3) bottom in the described cellular region I is provided with dielectric material area (11).
2. the longitudinal double diffusion metal oxide semiconductor power device of a kind of super-junction structure according to claim 1 is characterized in that described first conduction type mixes for the n type.
3. the longitudinal double diffusion metal oxide semiconductor power device of a kind of super-junction structure according to claim 1 and 2 is characterized in that described second conduction type mixes for the p type.
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| CN201110163995A CN102231390B (en) | 2011-06-17 | 2011-06-17 | Vertical double-diffused metal oxide semiconductor power device with super junction structure |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103137660B (en) * | 2011-11-30 | 2015-10-14 | 上海华虹宏力半导体制造有限公司 | Super junction powder device terminal structure |
| CN103165670B (en) * | 2011-12-09 | 2015-08-19 | 上海华虹宏力半导体制造有限公司 | Super-junction device |
| CN103035528B (en) * | 2012-05-23 | 2015-08-19 | 上海华虹宏力半导体制造有限公司 | Super junction preparation technology method |
| CN102760770A (en) * | 2012-06-11 | 2012-10-31 | 电子科技大学 | Single particle irradiation-resistant super junction VDMOS device |
| CN103022134B (en) * | 2012-12-06 | 2015-09-09 | 电子科技大学 | A kind of horizontal high voltage power device of SOI of Ultra-low Specific conducting resistance |
| CN102969358B (en) * | 2012-12-06 | 2015-08-19 | 电子科技大学 | A kind of horizontal high voltage power semiconductor device |
| CN102969357B (en) * | 2012-12-06 | 2015-08-19 | 电子科技大学 | A kind of horizontal ultra-junction high-voltage power semiconductor device |
| CN108735801A (en) * | 2018-05-29 | 2018-11-02 | 电子科技大学 | A kind of superjunction power DMOS device |
| CN108598152B (en) * | 2018-05-29 | 2020-11-13 | 电子科技大学 | Super junction device terminal structure |
| CN110600534A (en) * | 2019-09-05 | 2019-12-20 | 曾爱平 | Power device with super junction structure and manufacturing method thereof |
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| CN101308848A (en) * | 2007-05-17 | 2008-11-19 | 株式会社电装 | Semiconductor device |
| CN101969073A (en) * | 2010-08-27 | 2011-02-09 | 东南大学 | Rapid superjunction longitudinal double-diffusion metal oxide semiconductor transistor |
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| US20080197381A1 (en) * | 2007-02-15 | 2008-08-21 | Nec Electronics Corporation | Semiconductor device and method for manufacturing same |
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| CN101308848A (en) * | 2007-05-17 | 2008-11-19 | 株式会社电装 | Semiconductor device |
| CN101969073A (en) * | 2010-08-27 | 2011-02-09 | 东南大学 | Rapid superjunction longitudinal double-diffusion metal oxide semiconductor transistor |
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