CN107845675B - Transverse double-diffusion metal oxide semiconductor field effect transistor - Google Patents
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 38
- 229910044991 metal oxide Inorganic materials 0.000 title claims abstract description 32
- 150000004706 metal oxides Chemical class 0.000 title claims abstract description 32
- 230000005669 field effect Effects 0.000 title claims abstract description 31
- 238000009792 diffusion process Methods 0.000 title abstract description 6
- 239000002184 metal Substances 0.000 claims abstract description 104
- 230000005684 electric field Effects 0.000 abstract description 12
- 230000015556 catabolic process Effects 0.000 description 9
- 230000000694 effects Effects 0.000 description 8
- 238000000034 method Methods 0.000 description 6
- 238000010586 diagram Methods 0.000 description 5
- 230000008859 change Effects 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 229920005591 polysilicon Polymers 0.000 description 4
- 230000003071 parasitic effect Effects 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- 230000008569 process Effects 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
- H01L29/7824—Lateral DMOS transistors, i.e. LDMOS transistors with a substrate comprising an insulating layer, e.g. SOI-LDMOS transistors
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
- H01L29/42368—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform
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Abstract
The invention discloses a transverse double-diffusion metal oxide semiconductor field effect transistor, which comprises: the source electrode metal is connected with a width-graded metal field plate, the width-graded metal field plate comprises a plurality of width-graded metal layers which are arranged along the width direction, and the width of each width-graded metal layer is gradually reduced along the direction from the source electrode to the drain electrode. The structure can enable the electric charges induced on the field plate to be distributed more uniformly in the length direction of the device, so that the electric field distribution on the surface of the device is more uniform, and the transverse voltage resistance of the device can be improved under the condition of ensuring the on-resistance of the device.
Description
Technical Field
The invention relates to the field of power semiconductor devices, in particular to a lateral double-diffused metal oxide semiconductor field effect transistor (LDMOS) suitable for high-voltage application.
Background
A lateral double diffused metal oxide semiconductor field effect transistor (LDMOS) is a lateral high voltage device of a double diffused metal oxide semiconductor field effect transistor Device (DMOS). The method has the advantages of high withstand voltage, large gain, low distortion and the like, and is more compatible with a CMOS (complementary metal oxide semiconductor) process, so that the method is widely applied to an intelligent power integrated circuit. The current design of the lateral double-diffused metal oxide semiconductor field effect transistor (LDMOS) is mainly used for reasonably alleviating the contradiction between breakdown voltage and on-resistance and ensuring higher stability.
A conventional lateral double-diffused metal oxide semiconductor Field effect transistor (LDMOS) structure is shown in fig. 1, and currently, research on a lateral double-diffused metal oxide semiconductor transistor mainly focuses on design of the concentration of a drift region of the lateral double-diffused metal oxide semiconductor transistor, and compromise between breakdown voltage and on-resistance is realized by reducing surface electric Field strength (RESURF) of a device through a buried layer technology, and by using technologies such as a resistive Field plate, a Super Junction, and gradual doping of the drift region.
When the lateral double-diffused metal oxide semiconductor field effect transistor is in a state of being turned off and resistant to voltage, the surface potential of the lateral double-diffused metal oxide semiconductor field effect transistor is gradually increased along the direction from the source electrode to the drain electrode, so that the electric charges induced on the traditional field plate are gradually increased, and the electric charges on the field plate are unevenly distributed.
In addition, to make bulk silicon devices have better functions, it is an important research topic to improve the breakdown voltage of the devices. The source electrode metal field plate is an important technology for improving the breakdown voltage of the device, but in the traditional field plate technology, because the edge effect exists at the tail end of the field plate, a large amount of charges are collected at the edge of the tail end of the field plate, so that the uniformity of the charge distribution on the field plate is poor, and the breakdown voltage of the device is reduced. Solving this problem will effectively raise the breakdown voltage of the device.
The prior art discloses a lateral double-diffused metal oxide semiconductor field effect transistor structure, wherein the tail end of a field plate is uniformly split into rectangular blocks, so that the source-drain capacitance of a device can be reduced, and the frequency characteristic of the device is improved. However, the field plate width in this technique is not graded, so the charge on the field plate is not uniformly distributed along the length direction, and cannot be perfectly balanced with the space charge in the drift region. Meanwhile, the tail ends of the field plate split blocks are aligned, and the edge effect of the tail ends of the field plates can cause a large amount of charges to be accumulated at the tail ends of the field plates, so that the electric field distribution on the surface of the device is uneven.
Disclosure of Invention
The invention aims to solve the problems and provides a lateral double-diffused metal oxide semiconductor field effect transistor, which enables a device to have more uniform surface electric field distribution and higher lateral voltage resistance by arranging a field plate with gradually changed width and changing the length of the field plate.
In order to achieve the purpose, the invention adopts the following technical scheme:
a lateral double diffused metal oxide semiconductor field effect transistor, comprising: the source electrode metal is connected with a width-graded metal field plate, the width-graded metal field plate comprises a plurality of width-graded metal layers which are arranged along the width direction, and the width of each width-graded metal layer is gradually reduced along the direction from the source electrode to the drain electrode.
Further, the field plate of graded width metal also includes: a bulk metal layer; one end of the blocky metal layer is connected with the source metal, and the other end of the blocky metal layer is connected with the width-graded metal layer.
Further, the bulk metal layer and the width-graded metal layer are integrally formed in one step.
Further, the lengths of the width-graded metal layers are different.
Further, the width-graded metal field plate includes a plurality of width-graded first metal layers arranged in a width direction and a plurality of width-graded second metal layers arranged in the width direction; the lengths of the width-graded first metal layer and the width-graded second metal layer are different.
Further, the width-graded first metal layers and the width-graded second metal layers are arranged in a staggered mode.
Further, a gap between the source metal and the drain metal is filled with a dielectric layer.
Furthermore, a field oxide layer is connected below the dielectric layer, and the sum of the thicknesses of the field oxide layer and the dielectric layer is larger than 1 μm.
Further, the amount of charge induced on the field plate is adjusted by adjusting the length of the graded-width metal layer or adjusting the grading speed of the width of the graded-width metal layer.
The invention further discloses a driving chip applied to a printer, a motor or a flat panel display, comprising: any one of the lateral double-diffused metal oxide semiconductor field effect transistors is adopted.
The invention has the beneficial effects that:
(1) the structure of the invention adopts the width-graded metal field plate, the width of the field plate is gradually reduced along the direction from the source electrode to the drain electrode, therefore, the parasitic capacitance between the field plate and the drift region is also gradually reduced along the direction from the source electrode to the drain electrode, the change trend is opposite to the change trend of the surface potential, and the nonuniformity of the charge distribution on the field plate caused by the gradual increase of the surface potential along the direction from the source electrode to the drain electrode is partially offset. Therefore, the induced charge distribution of the field plate of the device with the structure is more uniform, so that the whole drift region of the device obtains a uniform field plate effect, the device has uniform transverse electric field (namely, electric field in the length direction) distribution of the drift region, and the transverse voltage-resisting capability of the device is improved.
(2) The lengths of the first metal layer with the gradually-changed width and the second metal layer with the gradually-changed width in the structure are different, so that three positions are distributed on the edge of the tail end of the field plate in the length direction, and the edge effect distribution of the field plate is uniform. Therefore, the uniformity of charge distribution on the field plate of the device is improved, the distribution of a transverse electric field of a drift region of the device is more uniform, and the transverse voltage resistance of the device is improved.
(3) The width-graded metal field plate in the structure can increase the length of the field plate under the condition of not increasing the induced charge quantity, so that the structure can increase the depletion of a drift region of a device, thereby increasing the electric field distribution length of the device and improving the transverse voltage-resisting capability of the device.
(4) The structure of the invention only needs to be improved on the layout, does not need to add extra process steps, and does not bring the increase of the process cost.
Drawings
FIG. 1 is a schematic diagram of a conventional lateral double diffused metal oxide semiconductor field effect transistor structure;
FIG. 2 is a schematic diagram of a lateral double diffused metal oxide semiconductor field effect transistor structure according to the present invention;
FIG. 3 is a surface lateral electric field distribution diagram of a lateral double-diffused metal oxide semiconductor field effect transistor of a conventional structure and a lateral double-diffused metal oxide semiconductor field effect transistor provided by the invention in a device breakdown state;
FIG. 4 is a surface lateral electric field distribution diagram of a lateral double-diffused metal oxide semiconductor field effect transistor of a conventional structure and a lateral double-diffused metal oxide semiconductor field effect transistor provided by the invention in a device breakdown state;
FIG. 5 is a diagram of simulation results of the drain current of a conventional LDMOS transistor and a LDMOS transistor according to the present invention varying with the drain voltage in the off state of the gate;
the semiconductor device comprises a P-type semiconductor substrate, a buried oxide layer, an N-type drift region, a P-type well, a P-type contact region, a N-type source region, a field oxide layer, a drain region, a gate oxide layer, a polysilicon gate, a dielectric layer, a drain metal layer, a source electrode metal layer, a drain electrode metal layer, a source electrode metal layer.
Detailed Description
The invention is further described with reference to the following figures and specific embodiments.
The invention discloses a transverse double-diffusion metal oxide semiconductor field effect transistor, which comprises: the semiconductor device comprises a P-type semiconductor substrate 1, a buried oxide layer 2 arranged above the P-type semiconductor substrate 1, an N-type drift region 3 and a P-type well 4 arranged above the buried oxide layer 2; a P-type contact region 5 and an N-type source region 6 are arranged above the P-type well 4, and a field oxide layer 7 and an N-type drain region 8 are arranged above the N-type drift region 3; a gate oxide layer 9 is arranged above the N-type drift region 3 and the P-type well 4, one end of the gate oxide layer 9 is abutted against the boundary of the N-type source region 6, and the other end of the gate oxide layer is abutted against the boundary of the field oxide layer 7; a polysilicon gate 10 is arranged above the gate oxide layer 9, and the polysilicon gate 10 extends to the upper part of the field oxide layer 7; connecting drain metal 12 above the N-type drain region 8 and connecting source metal 13 above the P-type contact region 5 and the N-type source region 6; a graded width metal field plate 14 is connected to the source metal 13.
The width-graded metal field plate 14 includes: a bulk metal layer 140 and a plurality of width-graded metal layers arranged along the width direction, wherein the width of each width-graded metal layer is gradually reduced along the direction from the source electrode to the drain electrode. The bulk metal layer 140 has one end connected to the source metal 13 and the other end connected to the graded-width metal layer.
As an embodiment, the lengths of the graded-width metal layers may be different.
In the lateral double-diffused mosfet structure, the number of the width-graded metal layers, the length of each width-graded metal layer, and the gradient speed of the width may be set as required.
The width-graded metal layer of the present embodiment includes a plurality of width-graded first metal layers 141 arranged in the width direction and a plurality of width-graded second metal layers 142 arranged in the width direction, as shown in fig. 2; but not limited thereto, other forms of the structure of the graded metal layer are also within the scope of the present invention.
As shown in fig. 2, the width-graded metal field plate 14 includes a block metal layer 140, a plurality of width-graded first metal layers 141 arranged in the width direction, and a plurality of width-graded second metal layers 142 arranged in the width direction; the bulk metal layer 140 has one end connected to the source metal 13 and the other end connected to the first metal layer and the second metal layer.
In fig. 2, the width-graded first metal layer 141 and the width-graded second metal layer 142 are alternately arranged, and the widths of the width-graded first metal layer 141 and the width-graded second metal layer 142 are gradually reduced along a direction from the source to the drain. The length of the width-graded first metal layer 141 is smaller than the length of the width-graded second metal layer 142.
The width of the field plate is gradually reduced along the direction from the source electrode to the drain electrode, so that the parasitic capacitance between the field plate and the drift region is also gradually reduced along the direction from the source electrode to the drain electrode, and the change trend of the parasitic capacitance is opposite to the change trend of the surface potential, so that the nonuniformity of charge distribution on the field plate caused by the gradual increase of the surface potential along the direction from the source electrode to the drain electrode is partially offset. As shown in fig. 3, the distribution of the average charge on the field plate of the inventive structure along the length direction is significantly improved compared to the conventional structure.
Due to the edge effect at the end of the field plate, a large amount of charges are collected at the edge of the end of the field plate, so that the uniformity of the charge distribution on the field plate is poor. The lengths of the first metal layer 141 with the gradually-varied width and the second metal layer 142 with the gradually-varied width in the structure of the invention are different, so that the edge of the tail end of the field plate is distributed at three positions in the length direction, and the edge effect distribution of the field plate is uniform. As shown in fig. 3, the average charge density peak caused by the field plate edge effect on the field plate of the structure of the present invention is distributed at three positions, which becomes more uniform. Referring to fig. 4, the uniformity of the surface electric field distribution of the inventive structure is greatly improved due to the improved uniformity of the charge density on the field plate of the inventive structure.
As an embodiment, the bulk metal layer 140, the graded-width first metal layer 141, and the graded-width second metal layer 142 are formed in one piece, which can save design and manufacturing costs.
As an implementation manner, a dielectric layer 11 is arranged on the surfaces of a part of the P-type well 4, the P-type contact region 5, the N-type source region 6, the polysilicon gate 10, the N-type drain region 8 and a part of the field oxide layer 7; preferably, the sum of the thicknesses of the field oxide layer 7 and the dielectric layer 11 is greater than 1 μm, so that a better uniform charge distribution effect can be obtained.
It should be noted that the amount of charge induced on the width-graded metal field plate 14 in the structure of the present invention can be adjusted not only by the length of the field plate, but also by changing the gradient speed of the width. Therefore, the width-graded metal field plate 14 in the structure can increase the length of the field plate under the condition of not increasing the induced charge quantity, so that the structure can increase the depletion of a drift region of the device, thereby increasing the electric field distribution length of the device and improving the lateral voltage-resisting capability of the device. Referring to fig. 5, under the condition that other parameters such as the concentration of the drift region are the same, the maximum breakdown voltage obtained by the structure of the invention is obviously higher than that obtained by the traditional structure.
It should be noted that, the above description of a lateral double-diffused metal oxide semiconductor field effect transistor is performed with respect to the structure of an N-type device, and for the structure of a P-type device, the field plate structure with a graded width according to the present invention may also be adopted, and the specific embodiments are the same as above, and are not described herein again.
The invention further discloses a driving chip applied to a printer, a motor or a flat panel display, wherein the transverse double-diffusion metal oxide semiconductor field effect transistor is adopted in the chip.
The invention further discloses a printer, a motor or a flat panel display, and the devices all adopt the driving chip comprising the transverse double-diffusion metal oxide semiconductor field effect transistor disclosed by the invention.
Although the embodiments of the present invention have been described with reference to the accompanying drawings, it is not intended to limit the scope of the present invention, and it should be understood by those skilled in the art that various modifications and variations can be made without inventive efforts by those skilled in the art based on the technical solution of the present invention.
Claims (9)
1. A lateral double diffused metal oxide semiconductor field effect transistor, comprising: the source electrode comprises source electrode metal and drain electrode metal opposite to the source electrode metal, and is characterized in that a width graded metal field plate is connected to the source electrode metal and comprises a plurality of width graded metal layers arranged along the width direction, the width of each width graded metal layer is gradually reduced along the direction from the source electrode to the drain electrode, and the lengths of the width graded metal layers are different.
2. The ldmos field effect transistor of claim 1 wherein said field plate of graded width further comprises: a bulk metal layer; one end of the blocky metal layer is connected with the source metal, and the other end of the blocky metal layer is connected with the width-graded metal layer.
3. The lateral double diffused metal oxide semiconductor field effect transistor of claim 2 wherein the bulk metal layer and the graded width metal layer are a one-step integral body.
4. The ldmos field effect transistor of claim 1 wherein the width graded metal field plate includes a plurality of width graded first metal layers arranged in a width direction and a plurality of width graded second metal layers arranged in the width direction; the lengths of the width-graded first metal layer and the width-graded second metal layer are different.
5. The LDMOS transistor of claim 4, wherein the first metal layers are staggered with respect to the second metal layers.
6. The ldmosfet of claim 1 wherein a gap between the source metal and the drain metal is filled with a dielectric layer.
7. The lateral double-diffused metal oxide semiconductor field effect transistor of claim 6 wherein a field oxide layer is connected under the dielectric layer, the sum of the thicknesses of the field oxide layer and the dielectric layer being greater than 1 μm.
8. The lateral double diffused metal oxide semiconductor field effect transistor of claim 1 wherein the amount of charge induced on the field plate is adjusted by adjusting the length of the graded metal layer or adjusting the rate of the grading of the metal layer width.
9. A driver chip for use in a printer, motor or flat panel display, comprising: use of any of the laterally double diffused metal oxide semiconductor field effect transistors as claimed in claims 1 to 8.
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| US10665712B2 (en) * | 2018-09-05 | 2020-05-26 | Monolithic Power Systems, Inc. | LDMOS device with a field plate contact metal layer with a sub-maximum size |
| CN112447843A (en) * | 2019-09-02 | 2021-03-05 | 无锡华润上华科技有限公司 | Field plate and lateral diffusion metal oxide semiconductor device |
| CN112382658B (en) * | 2020-08-28 | 2021-08-24 | 电子科技大学 | Low gate charge device with stepped discrete shield trenches and method of making the same |
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| DE2852621C4 (en) * | 1978-12-05 | 1995-11-30 | Siemens Ag | Insulating layer field-effect transistor with a drift path between the gate electrode and drain zone |
| DE69415987T2 (en) * | 1994-11-08 | 1999-06-24 | St Microelectronics Srl | Integrated arrangement with a structure to protect against high electric fields |
| JP2010045130A (en) * | 2008-08-11 | 2010-02-25 | Nec Electronics Corp | Semiconductor device and method for producing the same |
| US8754469B2 (en) * | 2010-10-26 | 2014-06-17 | Texas Instruments Incorporated | Hybrid active-field gap extended drain MOS transistor |
| KR102122365B1 (en) * | 2014-12-12 | 2020-06-12 | 삼성전자주식회사 | semiconductor device |
| CN105742365A (en) * | 2016-04-14 | 2016-07-06 | 东莞电子科技大学电子信息工程研究院 | Radio-frequency LDMOS transistor and manufacturing method thereof |
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Effective date of registration: 20211116 Address after: 250101 Room 101, building 15, strategic emerging industry base, Jinan hi tech Zone, No. 2966, Chunhui Road, Jinan hi tech Zone, Shandong Province Patentee after: Jinan Banyi Electronics Co., Ltd Address before: 250022 No. 336, nanxinzhuang West Road, Jinan City, Shandong Province Patentee before: Jinan University |
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