CN102832237A - Trough-type semiconductor power device - Google Patents
Trough-type semiconductor power device Download PDFInfo
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- CN102832237A CN102832237A CN2012102264541A CN201210226454A CN102832237A CN 102832237 A CN102832237 A CN 102832237A CN 2012102264541 A CN2012102264541 A CN 2012102264541A CN 201210226454 A CN201210226454 A CN 201210226454A CN 102832237 A CN102832237 A CN 102832237A
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Abstract
The invention discloses a trough-type semiconductor power device and relates to the technical field of the trough-type semiconductor power device. The trough-type semiconductor power device comprises a substrate layer and an active layer, wherein a grating is formed in the active layer; the grating extends to the active layer longitudinally; a ladder-type medium groove is formed between a contact region and a drain region; one end of the ladder-type medium groove with bigger width is closer to the substrate layer; the medium groove is contacted the drain region and the contact region; and the dielectric coefficient of the medium in the medium groove is less than that of the active layer. The trough-type semiconductor power device has the advantages: 1, the voltage resistance of the device is improved drastically; 2, due to the grating, the effective longitudinal expansion conduction region of the device and the auxiliary depletion drift region of the medium groove are increased, therefore, the specific on resistance is reduced so as to reduce power consumption; the area of the isolation groove is saved because the grating is used as the medium isolation groove; and 3, because the medium groove folds the drift region and the charge accumulation area at a medium groove interface is the drain region or contact region, the device size is narrowed drastically.
Description
Technical field
The present invention relates to trench semiconductor power device technology field; Exactly relate to a kind of (Silicon-on-insulator) MOSFET lateral (Metal-Oxide-Semiconductor Field-Effect-Transistor, metal-oxide semiconductor fieldeffect transistor) device that is used for power integrated circuit or radio-frequency power integrated circuit.
Background technology
SOI introduces dielectric buried layer between top layer semiconductor (being called active layer) and substrate layer (can be semiconductor or dielectric), with semiconductor device or circuit production in active layer.Usually adopt isolation channel 30 to isolate between integrated circuit mesohigh device, the low-voltage circuit, then isolate (as shown in Figure 1) between active layer 3 and the substrate layer 1 by dielectric layer 2.Therefore; With body silicon (semiconductor) compared with techniques, it is little that the SOI technology has ghost effect, and leakage current is little; Integrated level is high, capability of resistance to radiation strong and do not have advantage such as controllable silicon self-locking effect, obtains extensive concern and application in fields such as high speed, high temperature, low-power consumption and radioresistances.
The key of SOI power integrated circuit technology is the effective isolation that realizes between high withstand voltage, low-power consumption and high voltage unit and the low voltage unit.The SOI transversal device; Like LDMOSFET (Lateral Double-diffused Metal-Oxide-Semiconductor Field-Effect-Transistor LDMOSFET; The lateral double diffusion metal oxide field-effect transistor) is convenient to the core devices that integrated and relatively low conducting resistance becomes the SOI power integrated circuit because of it, in application such as plasma panel, motor driven, automotive electronics, portable power source management product and PC, gains great popularity.Simultaneously; Compare to VDMOSFET (Vertical Double-diffused Metal-Oxide-Semiconductor Field-Effect-Transistor VDMOS; The vertical DMOS field-effect transistor); The switching speed that (Silicon-on-insulator) MOSFET lateral is higher makes it be widely used in RF application.
For conventional LDMOSFET device, drift region length increases with the rising of device electric breakdown strength is dull.This not only makes, and the chip area of device (or circuit) increases, cost increases, and is unfavorable for miniaturization.Even more serious is, the conducting resistance of device increases with the increase of drift region length (or device withstand voltage) that (relational expression of conducting resistance and device withstand voltage can be expressed as: Ron ∝ BV
2.5, wherein BV is a device withstand voltage, Ron is a conducting resistance), the increase of conducting resistance causes power consumption sharply to increase, and devices switch speed also decreases.
Compare with the MOSFET of planar gate structure, have the MOSFET of slot grid structure, can increase packaging density on the one hand, thereby improve gully density and current density.The length of the raceway groove of groove gate MOSFET does not receive the restriction of photoetching process on the other hand, and raceway groove can be done shortlyer, thereby reduces conducting resistance.More than 2 MOSFET electric current ability to bears that all increase slot grid structure.Moreover the groove gate MOSFET can be avoided JFET (Junction Field-Effect-Transistor, junction field effect transistor) effect and latch up effect.
In order to overcome the problem that conventional LDMOSFET above-mentioned exists, the researcher utilizes the advantage of groove gate MOSFET in the industry, has proposed the SOI LDMOSFET device architecture based on the groove technology.Document (Won-So Son; Young-Ho Sohn; Sie-Young Choi; [Effects of a trench under the gate in high voltage RESURF LDMOSFET for SOI power integrated circuits] Solid-State Electronics 48 (2004) 1629 – 1635) proposition has the RESURF LDMOSFET of groove, and its device architecture is as shown in Figure 2.This device is with near the drift region between the drain region oxide groove 31 introducing gate electrode G ends.When doping content was too high, oxide groove 31 reduced the high electric field of silicon face under the gate electrode G end, avoided puncturing in advance here, and reduced the surface field peak value at edge, drain region, thereby on the basis that reduces conducting resistance, improve device withstand voltage.Length is 16 μ m to this device in the drift region, the highest withstand voltage 356V of reaching when dielectric buried layer 2 is respectively 3 μ m and 8 μ m with active layer 3 thickness.Its experimental result of document report is withstand voltage to be 352V, and conduction resistance is about 18.8 m Ω cm
2The LDMOSFET of this class formation is when 250V, and conduction resistance is about 9 m Ω cm
2It is thus clear that the effect of this structure reduction drift region length and conduction resistance is very limited.
Document Naoto Fujishima and C. Andre T. Salama; [A trench lateral power MOSFET using self-aligned trench bottom contact holes] IEDM 1997; Among the 359-362 drain electrode D and gate electrode G are designed in the groove of same notch cuttype shape, and the latter half of groove (near the drain region) sidewall has thick oxide layers 32.Be referred to as the grooved lateral direction power MOSFET (Trench Lateral Power MOSFET with Trench Bottom Drain Contact) that trench bottom has drain contact in the literary composition, be called TLPM/D MOSFET, device architecture is as shown in Figure 3.United States Patent (USP) (US 7005352B2; 2006.2.28; [trench-type MOSFET having a reduced device pitch and on-resistance]) source electrode S and gate electrode G are designed in same groove, be called TLPM/S MOSFET, structure is as shown in Figure 4.More than two kinds of structures all be to adopt trench structure to reduce lateral device dimensions (or chip area); And then reduce the conducting resistance of device and keep higher withstand voltage; The former is more suitable for the grooved low-resistance MOSFET of the withstand voltage 80V of being higher than; The latter is more suitable for the grooved low-resistance small size MOSFET of the withstand voltage 80V of being lower than, and technology is simpler than the former.But for the withstand voltage TLPM/D MOSFET that surpasses 100V, thick oxide layers 32 thickness of groove lower part increase on the one hand, have weakened the advantage of reduction of device lateral dimension; On the other hand, the degree of depth of groove is produced on technology difficulty increase in the same dark and narrow groove with withstand voltage increase with drain electrode and gate electrode.More than two kinds of structures all need drain electrode and gate electrode or source electrode and gate electrode are produced in the same groove; Its technology difficulty increases with the withstand voltage raising degree of depth of the groove (increase), and the effect that this structure reduces lateral device dimensions weakens with withstand voltage rising.United States Patent (USP) (US 2007/0298562A1; 2007.12.27; [method of manufacturing a semiconductor integrated circuit device]) TLPM/S device above-mentioned is used for integrated circuit; But must adopt PN junction to isolate and shallow-trench isolation between each device in the integrated circuit, and with the source electrode of high-voltage MOSFET and gate designs in same groove, technology is complicacy.
Summary of the invention
For solving existing technical problem in the above-mentioned prior art; The present invention proposes a kind of trench semiconductor power device; Adopt the present invention; The conducting resistance that has solved the existing device of conventional LDMOSFET device increase along with the increase of the length of drift region cause chip area to increase and be unfavorable for the technical problem of miniaturization and cost increase; Simultaneously, also solved latch up effect and planar gate structure be unfavorable for isolating, shorten device size with and the JFET effect brought, and channel length receives the technical problem of photoetching process restriction; SOI LDMOSFET device, TLPM/S MOSFET and the big technical problem of the existing technology difficulty of TLPM/D MOSFET have also been solved based on the groove technology.
The present invention realizes through adopting following proposal:
A kind of trench semiconductor power device comprises substrate layer and active layer, is formed with the groove grid in the said active layer, and the groove grid are made up of gate medium and the electric conducting material that is enclosed in the gate medium, and the exit of electric conducting material is a gate electrode, it is characterized in that:
Said groove grid vertically extend in the active layer at least, and the groove grid contact with the source region with the tagma respectively, and the source region covers the top in tagma fully, on the active layer surface of groove grid one side source region, body contact zone and drain region are set in order;
Said source region contacts with the body contact zone, and the vertical degree of depth in said tagma is more than or equal to the said body contact zone degree of depth; The vertical degree of depth of groove grid is more than or equal to the vertical degree of depth in tagma;
Between body contact zone and drain region, be formed with the media slot of notch cuttype, bigger that end of the media slot width of notch cuttype is more near substrate layer, and media slot contacts with the body contact zone with the drain region respectively; The dielectric coefficient of media slot medium is less than the dielectric coefficient of active layer material, and the vertical degree of depth of media slot is less than the thickness of active layer and greater than the degree of depth in said tagma;
Said drain region exit is a drain electrode, and the common exit of said source region and body contact zone is the source electrode.
The present invention also comprises the dielectric buried layer that is arranged between substrate layer and the active layer, and said groove grid vertically pass active layer up to dielectric buried layer.
Said ladder media slot is to form afterwards through the part medium that etching is removed in the media slot, and said body contact zone forms through deposit polysilicon filling notch cuttype groove.
The ladder number of the media slot of said notch cuttype is more than or equal to 1.
Said drain region is positioned at the center of trench semiconductor power device, and the groove grid are positioned at the periphery of trench semiconductor power device.
The structure that is upper-thin-lower-thick on said groove grid are vertical.
The transverse width of said dielectric buried layer is less than or equal to the transverse width of groove grid to the drain region.
The trench semiconductor power device forms the semiconductor device of the lateral MOS control of N raceway groove or P raceway groove.
The media slot of said notch cuttype is an inverted T shape.
Compared with prior art, the beneficial effect that the present invention reached is following:
One, among the present invention, be formed with the groove grid in the active layer, the groove grid vertically extend in the active layer at least; Such frame mode; It is withstand voltage that thereby the distribution that can regulate electric field improves, and expanded the vertically effective conductive region in drift region, greatly reduces conducting resistance and power consumption; Compare with the prior art that adopts planar gate; Can increase packaging density on the one hand, thereby improve gully density and current density, the length of the raceway groove of groove gate MOSFET does not receive the restriction of photoetching process on the other hand; Raceway groove can be done shortlyer; Thereby the reduction conducting resistance, more than 2 MOSFET electric current ability to bears that all increase slot grid structure, moreover; The groove gate MOSFET can be avoided JFET (Junction Field-Effect-Transistor, junction field effect transistor) effect and latch up effect.
Between body contact zone and drain region, be formed with the media slot of notch cuttype, thereby the distribution that just can regulate electric field improves withstand voltage; And bigger that end of the media slot width of notch cuttype is more near substrate layer, thereby can form a large amount of electric charges accumulation at media slot ladder place, further improves the voltage endurance of device; Adopt the form of this media slot, the drift region is folded media slot and the electric charge accumulating region at media slot ladder place also is drain region or body contact zone, dwindled lateral device dimensions, and then reduce conduction resistance and chip cost, and increase switching speed.
The dielectric coefficient of medium is lower than the dielectric coefficient of active layer in the media slot, and this has reduced gate electrode-electric leakage interelectrode capacitance, has improved the switching frequency and the power output of device, is particularly useful for the application of RF application.
The drain region exit is a drain electrode, and the common exit of source region and body contact zone is the source electrode, and source electrode and gate electrode need not to be made in the media slot, has therefore reduced technology difficulty.
Two, the present invention also comprises the dielectric buried layer that is arranged between substrate layer and the active layer; Said groove grid vertically pass active layer up to dielectric buried layer; Such technical scheme; During the high pressure cut-off state, the high potential that gate medium will come from the drain region at device center ends in the groove grid, avoids the influence of high potential to low-voltage circuit beyond the groove grid.Therefore, the grid groove is simultaneously also as the dielectric isolation groove, and this has not only saved the area of dielectric isolation groove, and need not adopt special technological process to make the dielectric isolation groove as conventional high voltage integrated circuit, has simplified power integrated circuit technology, has practiced thrift cost.
Three, among the present invention, the ladder number of the media slot of said notch cuttype adopts multi-ladder to optimize Electric Field Distribution more than or equal to 1, and device withstand voltage improves, but conducting resistance slightly rises.
Four, among the present invention, the drain region is positioned at the center of trench semiconductor power device, and the groove grid are positioned at the periphery of trench semiconductor power device, can further improve withstand voltage, more high speed, low-power consumption, low cost, so that realize high and low pressure cell isolation in the integrated circuit.
Five, among the present invention, be the structure of upper-thin-lower-thick on the groove grid are vertical, this slot grid structure helps improving the withstand voltage of device.
Six, among the present invention, the transverse width of dielectric buried layer is during less than the width of substrate layer, and it is withstand voltage that the device substrate layer has been participated in, and makes the thermal diffusivity of device obtain obvious improvement.
Seven, among the present invention, the media slot of said notch cuttype is that inverted T shape is best frame mode, because the ladder place of the both sides of the media slot of inverted T shape all forms a large amount of electric charge accumulation, has further improved the voltage endurance of device.
Description of drawings
Fig. 1 is conventional SOI technology high voltage integrated circuit cross-sectional view.
Fig. 2 is the SOI RESURF LDMOSFET device architecture sketch map with groove.
Fig. 3 is a TLPM/D MOSFET structural representation.
Fig. 4 is a TLPM/S MOSFET structural representation.
Fig. 5 is the SOI (Silicon-on-insulator) MOSFET lateral cellular structure cutaway view that N raceway groove media slot is etched into inverted T shape.
Fig. 6 is the SOI (Silicon-on-insulator) MOSFET lateral cellular structure cutaway view that N raceway groove media slot is etched into a notch cuttype.
Fig. 7 is the SOI (Silicon-on-insulator) MOSFET lateral cellular structure cutaway view that N raceway groove media slot is etched into two notch cuttypes.
Fig. 8 is the SOI (Silicon-on-insulator) MOSFET lateral device cellular structure cutaway view that the N raceway groove media slot of gate medium upper-thin-lower-thick is etched into a notch cuttype.
Fig. 9 is a P channel SOI (Silicon-on-insulator) MOSFET lateral device cellular structure cutaway view.
Figure 10 is the body silicon (Silicon-on-insulator) MOSFET lateral cellular structure cutaway view that N raceway groove media slot is etched into inverted T shape.
Figure 11 is that a kind of media slot that has in the face of claiming structure is etched into notch cuttype SOI (Silicon-on-insulator) MOSFET lateral device cellular structural representation (xz plane);
AA ' is along the x direction, and BB ' vertically is the y direction along the z direction; Device architecture is to cross the yz plane symmetry of BB '.
Figure 12 is that a kind of media slot with axially symmetric structure is etched into notch cuttype SOI (Silicon-on-insulator) MOSFET lateral device cellular structural representation (xz plane);
AA ' is along the x direction; Vertically be the y direction; Device is a symmetry axis with the y axle of crossing drain electrode D center.
Figure 13 is a relatively sketch map (half cellular) of two-dimentional electric current line distribution.
Figure 14 is a relatively sketch map (half cellular) of two-dimentional equipotential lines distribution.
Figure 15 is that the present invention is used for integrated circuit, the isolation sketch map of high pressure SOI (Silicon-on-insulator) MOSFET lateral device and low-voltage circuit.
Reference numeral:
1, substrate layer; 2, dielectric layer; 3, active layer; 4, gate medium; 5, electric conducting material; 61, media slot; 6, fill medium in the media slot; 7, drain region; 8, be the grid groove; 9, tagma; 10, body contact zone; 11, source region; 21, groove gate electrode; 30, dielectric isolation groove; 31, oxide groove; 32, thick oxide layers; 33, high-tension circuit zone; 34, low-voltage circuit zone; S, source electrode; D, be drain electrode; G, be gate electrode.
Embodiment
Below in conjunction with accompanying drawing and embodiment, describe technical scheme of the present invention in detail.
Technical scheme of the present invention makes full use of the groove grid, and media slot and introduce the accumulation of a large amount of electric charges at the interface in media slot reaches a kind of electric property of trench semiconductor power device has been carried out comprehensive improvement and raising.Describe for ease, a kind of trench semiconductor power device some places of the present invention also abbreviate device as.
Fig. 5 shows the N raceway groove and has an inverted T shape media slot SOI trench semiconductor power device cellular cutaway view.This routine device comprises:
Vertical semiconductor substrate layer 1, dielectric buried layer 2 and active layer 3 from bottom to top;
Form the media slot 61 of inverted T shape between said body contact zone 10 and the drain region 7, said media slot 61 contacts with body contact zone 10 with drain region 7 respectively; The dielectric coefficient of said media slot 61 medium is less than the dielectric coefficient of active layer material, and said media slot 61 vertical degree of depth are less than the thickness of semiconductor active layer 3 and greater than the degree of depth in said tagma 9;
Said drain region 7 exits are drain electrode D, and the common exit of said source region 11 and body contact zone 10 is source electrode S.
The introducing of slot grid structure has increased the effectively vertically conductive area of device, thereby reduces conduction resistance greatly.The contact zone on media slot both sides is in different potentials, and forming inversion layer has a large amount of electric charge accumulation to strengthen the electric field in the medium, fills dielectric coefficient simultaneously in the media slot and is lower than 11.9 medium, also helps improving critical breakdown electric field.Introduce media slot and not only improved device withstand voltage, and reduced the lateral dimension of device or chip, thereby reduce conducting resistance and power consumption, and therefore practice thrift cost.Shown in Fig. 5 is the N channel SOI trench semiconductor power device that a ladder media slot 61 is arranged.The device technology of this planform realizes that more easily device has best symmetry.
Compare with embodiment 1, this routine device is to adopt the media slot that has a ladder, and all the other structures are identical with embodiment 1, and are as shown in Figure 6.Compare with structure shown in Figure 5, device adopts the notch cuttype media slot in this example, and withstand voltage having a little descends.
Compare with embodiment 2, this routine device is to adopt the media slot that two or more ladders are arranged, and all the other structures are identical with embodiment 2, and are as shown in Figure 7.Compare with structure shown in Figure 6, device adopts multi-ladder to optimize Electric Field Distribution in this example, and device withstand voltage improves, but conducting resistance slightly rises.
This routine device gate medium 4 vertically becomes the structure of upper-thin-lower-thick, and is as shown in Figure 8.The structure of this groove grid 8 helps improving device withstand voltage.
Embodiment 5
See Fig. 9, this routine device is the P channel SOI trench semiconductor power device with a ladder media slot 61.The material conduction type of this routine device active layer 3, source region 11, drain region 7, tagma 9 and body contact zone 10 and N channel SOI trench semiconductor power device (Fig. 5～shown in Figure 8) are just in time to instead.
The structure of embodiment 1-embodiment 4 all is applicable to P channel SOI trench semiconductor power device.But the material conduction type of P channel SOI trench semiconductor power device active layer 3, source region 11, drain region 7, tagma 9 and body contact zone 10 and N channel SOI trench semiconductor power device (Fig. 5～shown in Figure 8) are just in time to instead.
Figure 10 shows the body silicon trench semiconductor power device cellular cutaway view that the N raceway groove has an inverted T shape media slot.This routine device comprises:
Vertical semiconductor substrate layer 1 and active layer 3 from bottom to top;
Form the media slot 61 of inverted T shape between said body contact zone 10 and the drain region 7, said media slot 61 contacts with body contact zone 10 with drain region 7 respectively; The dielectric coefficient of said media slot 61 medium is less than the dielectric coefficient of active layer material, and said media slot 61 vertical degree of depth are less than the thickness of semiconductor active layer 3 and greater than the degree of depth in said tagma 9;
Said drain region 7 exits are drain electrode D, and the common exit of said source region 11 and body contact zone 10 is source electrode S.
The introducing of slot grid structure has increased the effectively vertically conductive area of device, thereby reduces conduction resistance greatly.The contact zone on media slot both sides is in different potentials, and forming inversion layer has a large amount of electric charge accumulation to strengthen the electric field in the medium, fills dielectric coefficient simultaneously in the media slot and is lower than 11.9 medium, also helps improving critical breakdown electric field.Introduce media slot and not only improved device withstand voltage, and reduced the lateral dimension of device or chip, thereby reduce conducting resistance and power consumption, and therefore practice thrift cost.Shown in Figure 10 is the N channel SOI trench semiconductor power device that a ladder media slot 61 is arranged.The device technology of this planform realizes that more easily device has best symmetry.
Embodiment 7
Referring to shown in Figure 11, this is that a kind of media slot in the face of the title structure is the trench semiconductor power device cellular laying out pattern sketch map of notch cuttype or inverted T shape.This figure is the xz plane graph, and wherein AA ' is along the x direction, and BB ' vertically is the y direction along the z direction.The plane of symmetry of this device was the yz plane of BB '.This figure comprises the domain of media slot 61 and groove grid 8, also has the domain of metal electrode: groove gate electrode 21, gate electrode G, source electrode S and drain electrode D.On this laying out pattern, the acting source region of electricity, drain region, groove grid 8; Media slot 61; Figures is bar shaped, and drain electrode D is positioned at the device center among the figure, and drain electrode D both sides are media slot 61; Media slot 61 outsides are source electrode S, and groove grid 8 are arranged in the device outermost so that realize integrated circuit high and low pressure cell isolation.Electric conducting material among the figure in the groove grid 8 is drawn by groove gate electrode 21, and exit is the gate electrode G of device.Gate electrode G and source electrode S have adopted habitual interdigitated configuration.
The trench semiconductor power device cellular laying out pattern figure that it is notch cuttype or inverted T shape that Figure 12 shows a kind of media slot with axially symmetric structure, i.e. xz plane graph, wherein AA ' is along the x direction.This figure is that example is described axially symmetric structure with the circular pattern.Drain region D is positioned at the device center, is separated by media slot 61 with source region b.Device is a symmetry axis with the y axle of crossing drain electrode D center.Electric conducting material in the groove grid 8 of device outermost draw end slot gate electrode 21, finally be the gate electrode G of device.Groove grid 8 are arranged in the device outermost so that realize integrated circuit high and low pressure cell isolation.
The most suitable active device owing to integrated circuit of SOI trench semiconductor power device of the present invention is especially for power integrated circuit and radio-frequency power integrated circuit.
The device that above-mentioned several kinds of embodiment of the present invention describe can adopt material device or the integrated circuit as source layer 3 such as Si, SiC, SiGe, GaAs or GaN, and this different materials technology maturation is drawn materials conveniently.Can satisfy different components or circuit performance requirement.
If active layer material adopts Si, the electric conducting material 5 of recommendation and be polysilicon to the media slot deposit packing material of etching.
As industry medium commonly used, media slot medium 6 is SiO
2, maybe can adopt dielectric coefficient to be lower than SiO
2And critical breakdown electric field is higher than the medium of 3 times of Si critical breakdown electric fields, like SiOF, CDO or SiCOF etc.Because SiO
2Dielectric coefficient 3.9 is lower than the relative dielectric coefficient 11.9 of Si relatively, and in media slot a large amount of electric charge accumulation is arranged at the interface, so strengthened the electric field of medium in the media slot, improves device withstand voltage, selects for use relative dielectric coefficient to be lower than SiO
2And the medium that critical breakdown electric field is higher than 3 times of Si critical breakdown electric fields more helps improving withstand voltage.The low-k of media slot 61 medium 6 also helps and reduces device grid-drain capacitance, improves devices switch speed.
The selection of gate medium 4 also can be adopted SiO
2, or dielectric coefficient is higher than SiO
2And critical breakdown electric field and SiO
2Equal or higher medium: like Si
3N
4, AlN, Al
2O
3Or HfO
2Deng.Gate medium adopts higher dielectric coefficient, can strengthen the control ability of gate voltage to the grid electric charge, increases mutual conductance.Perhaps at identical grid structure MIS (Metal-Insulator-Semiconductor; Semiconductor formation MIS structure under gate electrode-gate medium-gate medium) under the electric capacity; Can gate medium be made significantly thicker; Reduce tunnel current, avoid tunneling effect, the stability of enhance device or chip and reliability.
Technical scheme of the present invention does not almost require backing material, can be n type or p type, semiconductor material, even can be the dielectric material, or with dielectric buried layer be with a kind of dielectric material.
Figure 13 is that (the current strength difference of 2 adjacent current lines is 5 * 10 in two-dimentional electric current line distribution
-7A/ μ m).13a represents the SOI trench semiconductor power device with groove grid and inverted T shape media slot disclosed by the invention; The 13b representative has the media slot (Silicon-on-insulator) MOSFET lateral of planar gate and inverted T shape; 13c representative has planar gate and not with the (Silicon-on-insulator) MOSFET lateral of notch cuttype media slot; 13d represents conventional planar gate LDMOSFET (slotless grid and media slot).In the conventional SOI LDMOSFET device of Figure 13 d, the electric current device surface thin layer of only flowing through, effectively conductive area is less, does not have media slot simultaneously to drift region concentration optimization, and conduction resistance is bigger.Comparison diagram 13c and 13d can know that the introducing of media slot has improved the concentration of drift region, thereby reduce conduction resistance greatly.Therefore, the conduction resistance of device is from the 95m Ω .cm of Figure 13 d
2Be reduced to 11m Ω .cm
2Comparison diagram 13a and 13b can know, although media slot 61 has occupied conductive region bigger in the drift region, therefore the drift region concentration of optimizing increase; The groove grid have been optimized the concentration of drift region, expand the JFET effect of current channel area and deletion, so technology of the present invention conduction resistance under the situation of identical size of devices is reduced to 2.1m Ω .cm
2
Figure 14 is a relatively sketch map (half cellular) of two-dimentional equipotential lines distribution.14a represents the SOI trench semiconductor power device with groove grid and inverted T shape media slot disclosed by the invention; The (Silicon-on-insulator) MOSFET lateral that the 14b representative has planar gate and inverted T shape media slot; 14c representative has planar gate and not with the (Silicon-on-insulator) MOSFET lateral of inverted T shape media slot; 14d represents conventional planar gate LDMOSFET (slotless grid and media slot).The voltage difference of 2 adjacent equipotential liness is 5V among the figure, and three kinds of structure puncture voltages are respectively 149V, 132V, 58V, 19V.Comparison diagram 14a and 14b can know, the introducing of slot grid structure makes withstand voltagely brings up to 149V from the 132V with planar gate and inverted T shape media slot (Silicon-on-insulator) MOSFET lateral; Comparison diagram 14b and 14c can know, introduce inverted T shape in the media slot and make withstand voltage 58V bring up to 132V, have improved more than 1 times.Comparison diagram 14c and 14d can know that media slot makes withstand voltage 19V bring up to 58V, has improved near 3 times.
To sum up, technology of the present invention improves device withstand voltage and the reduction of device lateral dimension on the one hand greatly, and what play a major role is media slot 61, and the modulation of a large amount of electric charge accumulation and 8 pairs of electric fields of groove grid is arranged in inverted T shape media slot both sides at the interface; On the other hand, groove grid 8 have increased effectively vertically conductive area of device, reduce conduction resistance greatly; Simultaneously, the concentration of drift region has been improved in media slot assisted depletion drift region, significantly reduces conduction resistance, and then reduces power consumption; Moreover media slot has reduced grid-drain capacitance, improves the frequency and the power output of device.
Figure 15 is that the present invention is used for integrated circuit, the isolation sketch map of high tension apparatus and potential circuit.Can find out; Adopt technical scheme of the present invention; Need not form special isolation channel (like 30 among Fig. 1) between high tension apparatus and the low-voltage circuit, groove grid of the present invention itself just have perfect buffer action, and this technology has reduced the manufacturing cost and the technology difficulty of integrated circuit; Around the grid groove, form P+ zone ground connection, effect is equivalent to a shunt capacitance, has avoided noise jamming.
Present embodiment has the following advantages: the first, device withstand voltage improves greatly, and it mainly acts on is groove grid and media slot and a large amount of electric charges of accumulating at the interface in media slot; The second, the groove grid have increased vertical conductive region of device efficient extn and media slot assisted depletion drift region, make conduction resistance reduce, and then reduce power consumption, and the grid groove has been saved the area of isolation channel also as the dielectric isolation groove simultaneously; Three, media slot has folded the drift region and also has been drain region or body contact zone at media slot electric charge accumulating region at the interface, has dwindled device size greatly.Device of the present invention have high pressure, at a high speed, low-power consumption, low-cost with just with integrated advantage, be particularly suitable for power integrated circuit and RF IC.
Claims (9)
1. a trench semiconductor power device comprises substrate layer and active layer, is formed with the groove grid in the said active layer, and the groove grid are made up of gate medium and the electric conducting material that is enclosed in the gate medium, and the exit of electric conducting material is a gate electrode; It is characterized in that:
Said groove grid vertically extend in the active layer at least, and the groove grid contact with the source region with the tagma respectively, and the source region covers the top in tagma fully; Active layer surface in groove grid one side is provided with source region, body contact zone and drain region in order; Said source region contacts with the body contact zone, and the vertical degree of depth in said tagma is more than or equal to the said body contact zone degree of depth; The vertical degree of depth of groove grid is more than or equal to the vertical degree of depth in tagma;
Between body contact zone and drain region, be formed with the media slot of notch cuttype, bigger that end of the media slot width of notch cuttype is more near substrate layer, and media slot contacts with the body contact zone with the drain region respectively; The dielectric coefficient of media slot medium is less than the dielectric coefficient of active layer material; The vertical degree of depth of media slot is less than the thickness of active layer and greater than the degree of depth in said tagma;
Said drain region exit is a drain electrode, and the common exit of said source region and body contact zone is the source electrode.
2. a kind of trench semiconductor power device according to claim 1 is characterized in that: also comprise the dielectric buried layer that is arranged between substrate layer and the active layer, said groove grid vertically pass active layer up to dielectric buried layer.
3. a kind of trench semiconductor power device according to claim 1 and 2; It is characterized in that: said notch cuttype media slot is to form after removing the part medium of media slot both sides through etching, and said body contact zone fills through the deposit polysilicon that inverted ladder-shaped groove forms.
4. a kind of trench semiconductor power device according to claim 1 and 2 is characterized in that: the ladder number of the media slot of said notch cuttype is more than or equal to 1.
5. a kind of trench semiconductor power device according to claim 1 and 2, it is characterized in that: said drain region is positioned at the center of trench semiconductor power device, and the groove grid are positioned at the periphery of trench semiconductor power device.
6. a kind of trench semiconductor power device according to claim 5 is characterized in that: the structure that is upper-thin-lower-thick on said groove grid are vertical.
7. a kind of trench semiconductor power device according to claim 1 and 2 is characterized in that: the transverse width of said dielectric buried layer is less than or equal to the transverse width of groove grid to the drain region.
8. a kind of trench semiconductor power device according to claim 1 is characterized in that: the trench semiconductor power device forms the semiconductor device of the lateral MOS control of N raceway groove or P raceway groove.
9. a kind of trench semiconductor power device according to claim 1 is characterized in that: the media slot of stating notch cuttype is an inverted T shape.
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| CN103928522A (en) * | 2014-04-10 | 2014-07-16 | 电子科技大学 | Groove-shaped accumulation layer MOSFET device |
| CN104253050B (en) * | 2014-04-10 | 2016-12-21 | 电子科技大学 | A kind of manufacture method of grooved lateral MOSFET device |
| CN108780808A (en) * | 2016-02-10 | 2018-11-09 | 株式会社电装 | Semiconductor device |
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