CN102832237B - Trough-type semiconductor power device - Google Patents
Trough-type semiconductor power device Download PDFInfo
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- CN102832237B CN102832237B CN201210226454.1A CN201210226454A CN102832237B CN 102832237 B CN102832237 B CN 102832237B CN 201210226454 A CN201210226454 A CN 201210226454A CN 102832237 B CN102832237 B CN 102832237B
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Abstract
The invention discloses a trough-type semiconductor power device and relates to the technical field of the trough-type semiconductor power device. The trough-type semiconductor power device comprises a substrate layer and an active layer, wherein a grating is formed in the active layer; the grating extends to the active layer longitudinally; a ladder-type medium groove is formed between a contact region and a drain region; one end of the ladder-type medium groove with bigger width is closer to the substrate layer; the medium groove is contacted the drain region and the contact region; and the dielectric coefficient of the medium in the medium groove is less than that of the active layer. The trough-type semiconductor power device has the advantages: 1, the voltage resistance of the device is improved drastically; 2, due to the grating, the effective longitudinal expansion conduction region of the device and the auxiliary depletion drift region of the medium groove are increased, therefore, the specific on resistance is reduced so as to reduce power consumption; the area of the isolation groove is saved because the grating is used as the medium isolation groove; and 3, because the medium groove folds the drift region and the charge accumulation area at a medium groove interface is the drain region or contact region, the device size is narrowed drastically.
Description
Technical field
The present invention relates to trench type semiconductor power device technical field, exactly relate to a kind of (Silicon-on-insulator) MOSFET lateral (Metal-Oxide-Semiconductor Field-Effect-Transistor, metal-oxide semiconductor fieldeffect transistor) device for power integrated circuit or radio-frequency power integrated circuit.
Background technology
SOI introduces dielectric buried layer between top layer semiconductors (being called active layer) and substrate layer (can be semiconductor or dielectric), by semiconductor device or circuit production in active layer.Usually adopt isolation channel 30 to isolate between integrated circuit mesohigh device, low-voltage circuit, then undertaken isolating (as shown in Figure 1) by dielectric layer 2 between active layer 3 and substrate layer 1.Therefore, compared with body silicon (semiconductor) technology, it is little that SOI technology has ghost effect, and leakage current is little, integrated level is high, capability of resistance to radiation is strong and without advantages such as controllable silicon self-locking effects, obtain extensive concern and application in fields such as high speed, high temperature, low-power consumption and radioresistances.
The key of SOI power integrated circuit technique realizes high withstand voltage, low-power consumption and the effective isolation between high voltage unit and low voltage unit.SOI transversal device, as LDMOSFET(Lateral Double-diffused Metal-Oxide-Semiconductor Field-Effect-Transistor LDMOSFET, lateral double diffusion metal oxide field-effect transistor) core devices of SOI power integrated circuit is become because it is convenient to integrated and relatively low conducting resistance, gain great popularity in the application such as plasma panel, motor driving, automotive electronics, portable power source management product and PC.Simultaneously, compare to VDMOSFET(Vertical Double-diffused Metal-Oxide-Semiconductor Field-Effect-Transistor VDMOS, vertical DMOS field-effect transistor), the switching speed that (Silicon-on-insulator) MOSFET lateral is higher, makes it be widely used in RF application.
For conventional LDMOSFET device, drift region length is with the rising monotone increasing of device electric breakdown strength.This not only makes, and the chip area of device (or circuit) increases, cost increases, and is unfavorable for miniaturization.More seriously, the conducting resistance of device increases with the increase of drift region length (or device withstand voltage) that (relational expression of conducting resistance and device withstand voltage can be expressed as: Ron ∝ BV
2.5, wherein BV is device withstand voltage, and Ron is conducting resistance), the increase of conducting resistance causes power consumption sharply to increase, and devices switch speed also decreases.
Compared with the MOSFET of planar gate structure, there is the MOSFET of slot grid structure, can packaging density be increased on the one hand, thus improve gully density and current density.The length of the raceway groove of Grooved-gate MOSFET’s is not by the restriction of photoetching process on the other hand, and raceway groove can do shorter, thus reduce conducting resistance.Above 2 MOSFET current carrying capability all increasing slot grid structure.Moreover Grooved-gate MOSFET’s can avoid JFET (Junction Field-Effect-Transistor, junction field effect transistor) effect and latch up effect.
In order to overcome conventional LDMOSFET Problems existing above-mentioned, researcher utilizes the advantage of Grooved-gate MOSFET’s in the industry, proposes the SOI LDMOSFET device architecture based on groove technology.Document (Won-So Son, Young-Ho Sohn, Sie-Young Choi, [Effects of a trench under the gate in high voltage RESURF LDMOSFET for SOI power integrated circuits] Solid-State Electronics 48 (2004) 1629 – 1635) the RESURF LDMOSFET with groove is proposed, its device architecture is as shown in Figure 2.This device is introduced by oxide groove 31 near gate electrode G end until drift region between drain region.When doping content is too high, oxide groove 31 reduces the high electric field of silicon face under gate electrode G end, avoids puncturing in advance herein, and reduces the peak surface electric field at edge, drain region, thus improves device withstand voltage on the basis reducing conducting resistance.This device is 16 μm at drift region length, and the highest withstand voltage when dielectric buried layer 2 and active layer 3 thickness are respectively 3 μm and 8 μm reaches 356V.The document reports that its experimental result is withstand voltage for 352V, and conduction resistance is about 18.8 m Ω cm
2.The LDMOSFET of this class formation is when 250V, and conduction resistance is about 9 m Ω cm
2.Visible, the effect that this structure reduces drift region length and conduction resistance is very limited.
Document Naoto Fujishima and C. Andre T. Salama, [A trench lateral power MOSFET using self-aligned trench bottom contact holes] IEDM 1997, in 359-362, drain electrode D and gate electrode G is designed in the groove of same notch cuttype shape, and the latter half of groove (near drain region) sidewall has thick oxide layers 32.Be referred to as the grooved lateral direction power MOSFET (Trench Lateral Power MOSFET with Trench Bottom Drain Contact) that trench bottom has drain contact in literary composition, be called TLPM/D MOSFET, device architecture as shown in Figure 3.United States Patent (USP) (US 7005352B2,2006.2.28, [trench-type MOSFET having a reduced device pitch and on-resistance]) source electrode S and gate electrode G is designed in same groove, be called TLPM/S MOSFET, structure is as shown in Figure 4.Above two kinds of structures are all adopt trench structure to reduce lateral device dimensions (or chip area), and then reduce the conducting resistance of device and keep higher withstand voltage, the former is more suitable for the withstand voltage grooved low-resistance MOSFET higher than 80V, the latter is more suitable for the withstand voltage grooved low-resistance small size MOSFET lower than 80V, and technique is simpler compared with the former.But for the withstand voltage TLPM/D MOSFET more than 100V, thick oxide layers 32 thickness of groove lower part increases on the one hand, weakens the advantage of reduction of device lateral dimension; On the other hand, drain electrode and gate electrode, with withstand voltage increase, are produced on technology difficulty in same dark and narrow groove and increase by the degree of depth of groove.Above two kinds of structures all need drain electrode and gate electrode or source electrode and gate electrode to be produced in same groove, its technology difficulty increases with withstand voltage raising (degree of depth of groove increases), and the effect of this structure reduction lateral device dimensions weakens with withstand voltage rising.United States Patent (USP) (US 2007/0298562A1,2007.12.27, [method of manufacturing a semiconductor integrated circuit device]) TLPM/S device above-mentioned is used for integrated circuit, but PN junction isolation and shallow-trench isolation must be adopted between each device in integrated circuit, and by the source electrode of high-voltage MOSFET and gate designs in same groove, technique is more complicated.
Summary of the invention
For solving technical problem existing in above-mentioned prior art, the present invention proposes a kind of trench type semiconductor power device, adopt the present invention, the conducting resistance solving the device existing for conventional LDMOSFET device increases caused chip area and increases and be unfavorable for the technical problem that miniaturized and cost increases along with the increase of the length of drift region, simultaneously, also solve latch up effect and planar gate structure to be unfavorable for isolation, to shorten device size and its JFET effect brought, and channel length is by the technical problem of photoetching process restriction; Also solve based on the large technical problem of the technology difficulty existing for the SOI LDMOSFET device of groove technology, TLPM/S MOSFET and TLPM/D MOSFET.
The present invention realizes by adopting following proposal:
A kind of trench type semiconductor power device, comprises substrate layer and active layer, is formed with groove grid in described active layer, and groove grid are made up of gate medium and the electric conducting material be enclosed in gate medium, and the exit of electric conducting material is gate electrode, it is characterized in that:
Described groove grid longitudinally at least extend in active layer, groove grid respectively with tagma and source contact, source region covers the top in tagma completely, arranges source region, body contact zone and drain region in turn in the active layer surface of groove grid side;
Described source region contacts with body contact zone, and the longitudinal degree of depth in described tagma is more than or equal to the described body contact zone degree of depth; The longitudinal degree of depth of groove grid is more than or equal to the longitudinal degree of depth in tagma;
Between body contact zone and drain region, be formed with the media slot of notch cuttype, larger that one end of the media slot width of notch cuttype is closer to substrate layer, and media slot contacts with body contact zone with drain region respectively; The dielectric coefficient of media slot medium is less than the dielectric coefficient of active layer material, and the longitudinal degree of depth of media slot is less than the thickness of active layer and is greater than the degree of depth in described tagma;
Described drain region exit is drain electrode, and the common exit of described source region and body contact zone is source electrode.
The present invention also comprises the dielectric buried layer be arranged between substrate layer and active layer, described groove grid longitudinally through active layer until dielectric buried layer.
Described ladder media slot is by being formed after the certain media in etching removal media slot, and described body contact zone is formed by depositing polysilicon filling notch cuttype groove.
The step number of the media slot of described notch cuttype is more than or equal to 1.
Described drain region is positioned at the center of trench type semiconductor power device, and groove grid are positioned at the periphery of trench type semiconductor power device.
Described groove grid are the upper structure in upper-thin-lower-thick longitudinally.
The transverse width of described dielectric buried layer is less than or equal to the transverse width of groove grid to drain region.
The semiconductor device that the lateral MOS that trench type semiconductor power device forms N raceway groove or P raceway groove controls.
The media slot of described notch cuttype is inverted T shape.
Compared with prior art, the beneficial effect that reaches of the present invention is as follows:
One, in the present invention, be formed with groove grid in active layer, groove grid longitudinally at least extend in active layer, such frame mode, the distribution of electric field can be regulated thus improve withstand voltage, extending drift region longitudinally effective conductive region, greatly reduce conducting resistance and power consumption; Compared with adopting the prior art of planar gate, packaging density can be increased on the one hand, thus improve gully density and current density, the length of the raceway groove of Grooved-gate MOSFET’s is not by the restriction of photoetching process on the other hand, raceway groove can do shorter, thus reduction conducting resistance, above 2 MOSFET current carrying capability all increasing slot grid structure, moreover, Grooved-gate MOSFET’s can avoid JFET (Junction Field-Effect-Transistor, junction field effect transistor) effect and latch up effect.
Between body contact zone and drain region, be formed with the media slot of notch cuttype, just can regulate the distribution of electric field thus improve withstand voltage; And larger that one end of the media slot width of notch cuttype is closer to substrate layer, thus can form a large amount of charge accumulated at media slot ladder place, improve the voltage endurance of device further; Adopt the form of this media slot, media slot makes drift region fold and in the Ye Shi drain region, electric charge accumulating region at media slot ladder place or body contact zone, reduces lateral device dimensions, and then reduces conduction resistance and chip cost, and increases switching speed.
In media slot, the dielectric coefficient of medium is lower than the dielectric coefficient of active layer, it reduces gate electrode-electric leakage interelectrode capacitance, improves switching frequency and the power output of device, be particularly useful for the application of RF application.
Drain region exit is drain electrode, and the common exit of source region and body contact zone is source electrode, source electrode and gate electrode without the need to being made in media slot, because this reducing technology difficulty.
Two, the present invention also comprises the dielectric buried layer be arranged between substrate layer and active layer, described groove grid longitudinally through active layer until dielectric buried layer, such technical scheme, during high-pressure stop state, within the high potential in the drain region coming from device center is ended at groove grid by gate medium, avoid high potential on the impact of low-voltage circuit beyond groove grid.Therefore, grid groove is simultaneously also as medium isolation channel, and this not only saves the area of medium isolation channel, and does not need as conventional high-pressure integrated circuit, adopts specialized processes flow process to make medium isolation channel, simplifies power integrated circuit technique, saved cost.
Three, in the present invention, the step number of the media slot of described notch cuttype is more than or equal to 1, and adopt multi-ladder to optimize Electric Field Distribution, device withstand voltage improves, but conducting resistance slightly rises.
Four, in the present invention, drain region is positioned at the center of trench type semiconductor power device, and groove grid are positioned at the periphery of trench type semiconductor power device, can improve withstand voltage, more high speed, low-power consumption, low cost further, to realize high and low pressure cell isolation in integrated circuit.
Five, in the present invention, groove grid are the upper structure in upper-thin-lower-thick longitudinally, and this slot grid structure is conducive to improving the withstand voltage of device.
Six, in the present invention, when the transverse width of dielectric buried layer is less than the width of substrate layer, device substrate layer be take part in withstand voltage, make the thermal diffusivity of device obtain obvious improvement.
Seven, in the present invention, the media slot of described notch cuttype is inverted T shape is best frame mode, because the ladder place of the both sides of the media slot of inverted T shape all forms a large amount of charge accumulated, further increases the voltage endurance of device.
Accompanying drawing explanation
Fig. 1 is conventional SOI technology high voltage integrated circuit cross-sectional view.
Fig. 2 is the SOI RESURF LDMOSFET device architecture schematic diagram with groove.
Fig. 3 is TLPM/D MOSFET structure schematic diagram.
Fig. 4 is TLPM/S MOSFET structure schematic diagram.
Fig. 5 is the SOI (Silicon-on-insulator) MOSFET lateral structure cell cutaway view that N raceway groove media slot is etched into inverted T shape.
Fig. 6 is the SOI (Silicon-on-insulator) MOSFET lateral structure cell cutaway view that N raceway groove media slot is etched into a notch cuttype.
Fig. 7 is the SOI (Silicon-on-insulator) MOSFET lateral structure cell cutaway view that N raceway groove media slot is etched into two notch cuttypes.
Fig. 8 is the SOI lateral MOSFET device structure cell cutaway view that the N raceway groove media slot of gate medium upper-thin-lower-thick is etched into a notch cuttype.
Fig. 9 is P channel SOI lateral MOSFET device structure cell cutaway view.
Figure 10 is the body silicon (Silicon-on-insulator) MOSFET lateral structure cell cutaway view that N raceway groove media slot is etched into inverted T shape.
Figure 11 is that a kind of media slot with face symmetrical structure is etched into notch cuttype SOI lateral MOSFET device structure cell schematic diagram (xz plane);
In the x-direction, BB ' in the z-direction, is longitudinally y direction to AA '; Device architecture is to cross the yz plane symmetry of BB '.
Figure 12 is that a kind of media slot with axially symmetric structure is etched into notch cuttype SOI lateral MOSFET device structure cell schematic diagram (xz plane);
AA ' in the x-direction; Longitudinally be y direction; Device is to cross the y-axis at drain electrode D center for symmetry axis.
Figure 13 is that schematic diagram (half cellular) is compared in the distribution of Two-dimensional current line, wherein: Figure 13 a represents the SOI trench type semiconductor power device with groove grid and inverted T shape media slot disclosed by the invention; Figure 13 b representative has the media slot (Silicon-on-insulator) MOSFET lateral of planar gate and inverted T shape; Figure 13 c representative has planar gate and the (Silicon-on-insulator) MOSFET lateral not with notch cuttype media slot; Figure 13 d represents conventional plane grid LDMOSFET (slotless grid and media slot).
Figure 14 is that schematic diagram (half cellular) is compared in the distribution of two-dimentional equipotential lines, wherein: Figure 14 a represents the SOI trench type semiconductor power device with groove grid and inverted T shape media slot disclosed by the invention; Figure 14 b representative has the (Silicon-on-insulator) MOSFET lateral of planar gate and inverted T shape media slot; Figure 14 c representative has planar gate and the (Silicon-on-insulator) MOSFET lateral not with inverted T shape media slot; Figure 14 d represents conventional plane grid LDMOSFET (slotless grid and media slot).
Figure 15 be the present invention in integrated circuit, the isolation schematic diagram of high pressure SOI lateral MOSFET device and low-voltage circuit.
Reference numeral:
1, substrate layer; 2, dielectric layer; 3, active layer; 4, gate medium; 5, electric conducting material; 61, media slot; 6, filled media in media slot; 7, drain region; 8, be grid groove; 9, tagma; 10, body contact zone; 11, source region; 21, groove gate electrode; 30, medium isolation channel; 31, oxide groove; 32, thick oxide layers; 33, high-tension circuit region; 34, low-voltage circuit region; S, source electrode; D, be drain electrode; G, be gate electrode.
Embodiment
Below in conjunction with drawings and Examples, describe technical scheme of the present invention in detail.
Technical scheme of the present invention, makes full use of groove grid, media slot and introduce a large amount of charge accumulated in media slot interface, reaches and has carried out synthesis improvement and raising to a kind of electric property of trench type semiconductor power device.For convenience of description, a kind of trench type semiconductor power device some places of the present invention are also referred to as device.
Embodiment 1
Fig. 5 shows N raceway groove with an inverted T shape media slot SOI trench type semiconductor power device cellular cutaway view.This routine device comprises:
Longitudinal semiconductor substrate layer 1, dielectric buried layer 2 and active layer 3 from bottom to top;
Form groove grid 8 in described active layer, described groove grid are made up of the electric conducting material 5 of gate medium 4 and encirclement thereof, and described electric conducting material exit is gate electrode G; It is characterized in that, described groove grid longitudinally through semiconductor active layer 3 until dielectric buried layer 2; Described groove grid contact with source region 11 with tagma 9 respectively, and source region 11 covers the top in tagma 9 completely; On the semiconductor active layer surface of groove grid side, there is source region 11, body contact zone 10 and drain region 7 in turn; Described source region 11 contacts with body contact zone 10, and the longitudinal degree of depth in described tagma 9 is more than or equal to described body contact zone 10 degree of depth; The longitudinal degree of depth of groove grid is more than or equal to the longitudinal degree of depth in tagma 9;
Form the media slot 61 of inverted T shape between described body contact zone 10 and drain region 7, described media slot 61 contacts with body contact zone 10 with drain region 7 respectively; The dielectric coefficient of described media slot 61 medium is less than the dielectric coefficient of active layer material, and the longitudinal degree of depth of described media slot 61 is less than the thickness of semiconductor active layer 3 and is greater than the degree of depth in described tagma 9;
Described drain region 7 exit is drain electrode D, and the common exit of described source region 11 and body contact zone 10 is source electrode S.
The introducing of slot grid structure increases effective longitudinal conductive area of device, thus greatly reduces conduction resistance.The contact zone on media slot both sides is in different potentials, and forming inversion layer has a large amount of charge accumulated to enhance electric field in medium, fills dielectric coefficient lower than the medium of 11.9 simultaneously, be also conducive to improving critical breakdown electric field in media slot.Introduce media slot and not only increase device withstand voltage, and reduce the lateral dimension of device or chip, thus reduce conducting resistance and power consumption, and therefore cost-saving.Shown in Fig. 5 is the N channel SOI trench type semiconductor power device having a ladder media slot 61.The device technology of this planform more easily realizes, and device has best symmetry.
Embodiment 2
Compared with embodiment 1, this routine device adopts the media slot with a ladder, and all the other structures are identical with embodiment 1, as shown in Figure 6.Compared with structure shown in Fig. 5, in this example, device adopts notch cuttype media slot, and withstand voltage having declines a little.
Embodiment 3
Compared with embodiment 2, this routine device adopts the media slot having two or more ladders, and all the other structures are identical with embodiment 2, as shown in Figure 7.Compared with structure shown in Fig. 6, in this example, device adopts multi-ladder to optimize Electric Field Distribution, and device withstand voltage improves, but conducting resistance slightly rises.
Embodiment 4
This routine device gate dielectric 4 longitudinally becomes the structure of upper-thin-lower-thick, as shown in Figure 8.The structure of this groove grid 8 is conducive to improving device withstand voltage.
Embodiment 5
See Fig. 9, this routine device is the P channel SOI trench type semiconductor power device with a ladder media slot 61.The materials conductive type of this routine device active layer 3, source region 11, drain region 7, tagma 9 and body contact zone 10 and N channel SOI trench type semiconductor power device (shown in Fig. 5 ~ Fig. 8) are just in time to instead.
The structure of embodiment 1-embodiment 4 is all applicable to P channel SOI trench type semiconductor power device.But the materials conductive type of P channel SOI trench type semiconductor power device active layer 3, source region 11, drain region 7, tagma 9 and body contact zone 10 and N channel SOI trench type semiconductor power device (shown in Fig. 5 ~ Fig. 8) are just in time to instead.
Embodiment 6
Figure 10 shows the body silicon trench type semiconductor power device cellular cutaway view of N raceway groove with an inverted T shape media slot.This routine device comprises:
Longitudinally semiconductor substrate layer 1 from bottom to top and active layer 3;
Form groove grid 8 in described active layer, described groove grid are made up of the electric conducting material 5 of gate medium 4 and encirclement thereof, and described electric conducting material exit is gate electrode G; Described groove grid contact with source region 11 with tagma 9 respectively, and source region 11 covers the top in tagma 9 completely; On the semiconductor active layer surface of groove grid side, there is source region 11, body contact zone 10 and drain region 7 in turn; Described source region 11 contacts with body contact zone 10, and the longitudinal degree of depth in described tagma 9 is more than or equal to described body contact zone 10 degree of depth; The longitudinal degree of depth of groove grid is more than or equal to the longitudinal degree of depth in tagma 9;
Form the media slot 61 of inverted T shape between described body contact zone 10 and drain region 7, described media slot 61 contacts with body contact zone 10 with drain region 7 respectively; The dielectric coefficient of described media slot 61 medium is less than the dielectric coefficient of active layer material, and the longitudinal degree of depth of described media slot 61 is less than the thickness of semiconductor active layer 3 and is greater than the degree of depth in described tagma 9;
Described drain region 7 exit is drain electrode D, and the common exit of described source region 11 and body contact zone 10 is source electrode S.
The introducing of slot grid structure increases effective longitudinal conductive area of device, thus greatly reduces conduction resistance.The contact zone on media slot both sides is in different potentials, and forming inversion layer has a large amount of charge accumulated to enhance electric field in medium, fills dielectric coefficient lower than the medium of 11.9 simultaneously, be also conducive to improving critical breakdown electric field in media slot.Introduce media slot and not only increase device withstand voltage, and reduce the lateral dimension of device or chip, thus reduce conducting resistance and power consumption, and therefore cost-saving.Shown in Figure 10 is the N channel SOI trench type semiconductor power device having a ladder media slot 61.The device technology of this planform more easily realizes, and device has best symmetry.
Embodiment 7
Shown in Figure 11, the trench type semiconductor power device cellular laying out pattern schematic diagram of this to be the media slot of a kind of symmetrical structure be notch cuttype or inverted T shape.This figure is xz plane graph, and wherein AA ' in the x-direction, and BB ' in the z-direction, is longitudinally y direction.The plane of symmetry of this device was the yz plane of BB '.This figure comprises the domain of media slot 61 and groove grid 8, also has the domain of metal electrode: groove gate electrode 21, gate electrode G, source electrode S and drain electrode D.On this laying out pattern, the source region that electricity works, drain region, groove grid 8, media slot 61, be bar shaped in figure, in figure, drain electrode D is positioned at device center, and drain electrode D both sides are media slot 61, be source electrode S outside media slot 61, groove grid 8 are arranged in device outermost to realize integrated circuit high and low pressure cell isolation.Electric conducting material in figure middle slot grid 8 is drawn by groove gate electrode 21, and exit is the gate electrode G of device.Gate electrode G and source electrode S have employed usual interdigitated configuration.
Figure 12 shows the trench type semiconductor power device cellular laying out pattern figure that a kind of media slot with axially symmetric structure is notch cuttype or inverted T shape, i.e. xz plane graph, wherein AA ' in the x-direction.This figure describes axially symmetric structure for circular pattern.Drain region D is positioned at device center, is separated by media slot 61 with source region b.Device is to cross the y-axis at drain electrode D center for symmetry axis.The extraction end slot gate electrode 21 of the electric conducting material in the groove grid 8 of device outermost is finally the gate electrode G of device.Groove grid 8 are arranged in device outermost to realize integrated circuit high and low pressure cell isolation.
The most applicable active device due to integrated circuit of SOI trench type semiconductor power device of the present invention, especially for power integrated circuit and radio-frequency power integrated circuit.
The device that above-mentioned several embodiment of the present invention describes, Si, SiC, SiGe, GaAs or GaN etc. can be adopted as the material making devices of active layer 3 or integrated circuit, and this different materials technology maturation, draws materials conveniently.Different components or circuit performance requirement can be met.
If active layer material adopts Si, the electric conducting material 5 of recommendation and the media slot deposit packing material to etching are polysilicon.
As the medium that industry is conventional, media slot medium 6 is SiO
2, dielectric coefficient maybe can be adopted lower than SiO
2and critical breakdown electric field is higher than the medium of Si critical breakdown electric field 3 times, as SiOF, CDO or SiCOF etc.Due to SiO
2relative dielectric coefficient 3.9 lower than Si relative dielectric coefficient 11.9, and has a large amount of charge accumulated in media slot interface, so enhance the electric field of medium in media slot, improves device withstand voltage, selects relative dielectric coefficient lower than SiO
2and critical breakdown electric field is more conducive to improving withstand voltage higher than the medium of Si critical breakdown electric field 3 times.The low-k of media slot 61 medium 6, also helps reduction device gate-drain capacitance, improves devices switch speed.
The selection of gate medium 4, also can adopt SiO
2, or dielectric coefficient is higher than SiO
2and critical breakdown electric field and SiO
2equal or higher medium: as Si
3n
4, AlN, Al
2o
3or HfO
2deng.Gate medium adopts higher dielectric coefficient, can strengthen the control ability of gate voltage to grid electric charge, increases mutual conductance.Or at identical grid structure MIS(Metal-Insulator-Semiconductor, semiconductor under gate electrode-gate medium-gate medium forms MIS structure) under electric capacity, gate medium can be made significantly thicker, reduce tunnel current, avoid tunneling effect, the Stability and dependability of enhance device or chip.
Technical scheme of the present invention, to backing material almost not requirement, can be N-shaped or p-type semiconductor material, can be even insulating dielectric materials, or be same dielectric material with dielectric buried layer.
Figure 13 is that (the current strength difference of 2 adjacent current lines is 5 × 10 to the distribution of Two-dimensional current line
-7a/ μm).13a represents the SOI trench type semiconductor power device with groove grid and inverted T shape media slot disclosed by the invention; 13b representative has the media slot (Silicon-on-insulator) MOSFET lateral of planar gate and inverted T shape; 13c representative has planar gate and the (Silicon-on-insulator) MOSFET lateral not with notch cuttype media slot; 13d represents conventional plane grid LDMOSFET (slotless grid and media slot).In the conventional SOI LDMOSFET device of Figure 13 d, electric current only flows through device surface thin layer, and effective conductive area is less, simultaneously without media slot to drift region concentration optimization, conduction resistance is larger.Comparison diagram 13c and 13d is known, and the introducing of media slot improves the concentration of drift region, thus greatly reduces conduction resistance.Therefore, the conduction resistance of device is from the 95m Ω .cm of Figure 13 d
2be reduced to 11m Ω .cm
2.Comparison diagram 13a and 13b is known, although media slot 61 occupies conductive region larger in drift region, therefore the drift region concentration optimized increase; Groove grid optimize the concentration of drift region, expand the JFET effect of current channel area and deletion, so the technology of the present invention conduction resistance when identical size of devices is reduced to 2.1m Ω .cm
2.
Figure 14 is that schematic diagram (half cellular) is compared in the distribution of two-dimentional equipotential lines.14a represents the SOI trench type semiconductor power device with groove grid and inverted T shape media slot disclosed by the invention; 14b representative has the (Silicon-on-insulator) MOSFET lateral of planar gate and inverted T shape media slot; 14c representative has planar gate and the (Silicon-on-insulator) MOSFET lateral not with inverted T shape media slot; 14d represents conventional plane grid LDMOSFET (slotless grid and media slot).In figure, the voltage difference of 2 adjacent equipotential liness is 5V, and three kinds of structure puncture voltages are respectively 149V, 132V, 58V, 19V.Comparison diagram 14a and 14b is known, and the introducing of slot grid structure makes the withstand voltage 132V from having planar gate and inverted T shape media slot (Silicon-on-insulator) MOSFET lateral bring up to 149V; Comparison diagram 14b and 14c is known, introduces inverted T shape and makes withstand voltage 58V bring up to 132V, improve more than 1 times in media slot.Comparison diagram 14c and 14d is known, and media slot makes withstand voltage 19V bring up to 58V, improves close to 3 times.
To sum up, technology of the present invention makes device withstand voltage greatly improve and reduction of device lateral dimension on the one hand, and what play a major role is media slot 61, has the modulation of a large amount of charge accumulated and groove grid 8 pairs of electric fields in interface, inverted T shape media slot both sides; On the other hand, groove grid 8 increase the effective longitudinal conductive area of device, greatly reduce conduction resistance; Meanwhile, media slot assisted depletion drift region, improves the concentration of drift region, significantly reduces conduction resistance, and then reduces power consumption; Moreover media slot reduces grid-drain capacitance, improve frequency and the power output of device.
Figure 15 be the present invention in integrated circuit, the isolation schematic diagram of high tension apparatus and potential circuit.Can find out, adopt technical scheme of the present invention, do not need between high tension apparatus and low-voltage circuit to form special isolation channel (as 30 in Fig. 1), groove grid of the present invention inherently have perfect buffer action, and this technology reduces manufacturing cost and the technology difficulty of integrated circuit; Formation P+ local ground around grid groove, effect is equivalent to a shunt capacitance, avoids noise jamming.
The present embodiment has the following advantages: the first, device withstand voltage improves greatly, its Main Function be groove grid and media slot and a large amount of electric charges in the accumulation of media slot interface; The second, groove grid increase device and effectively expand longitudinal conductive region and media slot assisted depletion drift region, and conduction resistance is reduced, and then reduce power consumption, and grid groove is also as medium isolation channel simultaneously, saves the area of isolation channel; Three, media slot is folded drift region and in the Ye Shi drain region, electric charge accumulating region of media slot interface or body contact zone, greatly reduces device size.Device of the present invention have high pressure, at a high speed, low-power consumption, low cost and just with integrated advantage, be particularly suitable for power integrated circuit and radio frequency integrated circuit.
Claims (9)
1. a trench type semiconductor power device, comprises substrate layer and active layer, is formed with groove grid in described active layer, and groove grid are made up of gate medium and the electric conducting material be enclosed in gate medium, and the exit of electric conducting material is gate electrode; It is characterized in that:
Described groove grid longitudinally at least extend in active layer, groove grid respectively with tagma and source contact, source region covers the top in tagma completely; In the active layer surface of groove grid side, source region, body contact zone and drain region are set in turn; Described source region contacts with body contact zone, and the longitudinal degree of depth in described tagma is more than or equal to the described body contact zone degree of depth; The longitudinal degree of depth of groove grid is more than or equal to the longitudinal degree of depth in tagma;
Between body contact zone and drain region, be formed with the media slot of notch cuttype, larger that one end of the media slot width of notch cuttype is closer to substrate layer, and media slot contacts with body contact zone with drain region respectively; The dielectric coefficient of media slot medium is less than the dielectric coefficient of active layer material; The longitudinal degree of depth of media slot is less than the thickness of active layer and is greater than the degree of depth in described tagma;
Described drain region exit is drain electrode, and the common exit of described source region and body contact zone is source electrode.
2. a kind of trench type semiconductor power device according to claim 1, is characterized in that: also comprise the dielectric buried layer be arranged between substrate layer and active layer, described groove grid longitudinally through active layer until dielectric buried layer.
3. a kind of trench type semiconductor power device according to claim 1 and 2, it is characterized in that: described notch cuttype media slot be by etching remove media slot both sides certain media after formed, described body contact zone by depositing polysilicon fill inverted ladder-shaped groove formed.
4. a kind of trench type semiconductor power device according to claim 1 and 2, is characterized in that: the step number of the media slot of described notch cuttype is more than or equal to 1.
5. a kind of trench type semiconductor power device according to claim 1 and 2, it is characterized in that: described drain region is positioned at the center of trench type semiconductor power device, groove grid are positioned at the periphery of trench type semiconductor power device.
6. a kind of trench type semiconductor power device according to claim 5, is characterized in that: described groove grid are the upper structure in upper-thin-lower-thick longitudinally.
7. a kind of trench type semiconductor power device according to claim 2, is characterized in that: the transverse width of described dielectric buried layer is less than or equal to the transverse width of groove grid to drain region.
8. a kind of trench type semiconductor power device according to claim 1, is characterized in that: the semiconductor device that the lateral MOS that trench type semiconductor power device forms N raceway groove or P raceway groove controls.
9. a kind of trench type semiconductor power device according to claim 1, is characterized in that: the media slot stating notch cuttype is inverted T shape.
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| CN104253050B (en) * | 2014-04-10 | 2016-12-21 | 电子科技大学 | A kind of manufacture method of grooved lateral MOSFET device |
| JP6634860B2 (en) * | 2016-02-10 | 2020-01-22 | 株式会社デンソー | Semiconductor device |
| US10962694B2 (en) * | 2018-11-02 | 2021-03-30 | Viavi Solutions Inc. | Stepped structure optical filter |
| CN110416306A (en) * | 2019-07-01 | 2019-11-05 | 长沙理工大学 | One kind having ladder separate gate L-type slot transversal device |
| CN112820648B (en) * | 2020-12-31 | 2023-08-01 | 扬州扬杰电子科技股份有限公司 | Gallium nitride metal oxide semiconductor transistor and preparation method thereof |
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