CN104253050B - A kind of manufacture method of grooved lateral MOSFET device - Google Patents
A kind of manufacture method of grooved lateral MOSFET device Download PDFInfo
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- 238000000034 method Methods 0.000 title claims abstract description 33
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 17
- 239000004065 semiconductor Substances 0.000 claims abstract description 55
- 238000005530 etching Methods 0.000 claims abstract description 5
- 238000002347 injection Methods 0.000 claims abstract description 3
- 239000007924 injection Substances 0.000 claims abstract description 3
- 239000012535 impurity Substances 0.000 claims description 22
- 239000002210 silicon-based material Substances 0.000 claims description 22
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 16
- 239000000758 substrate Substances 0.000 claims description 16
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 15
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 14
- 239000000463 material Substances 0.000 claims description 13
- 210000000746 body region Anatomy 0.000 claims description 9
- 238000001259 photo etching Methods 0.000 claims description 9
- 229920002120 photoresistant polymer Polymers 0.000 claims description 9
- 239000002184 metal Substances 0.000 claims description 8
- 230000003647 oxidation Effects 0.000 claims description 7
- 238000007254 oxidation reaction Methods 0.000 claims description 7
- 239000000377 silicon dioxide Substances 0.000 claims description 7
- 235000012239 silicon dioxide Nutrition 0.000 claims description 7
- 230000015556 catabolic process Effects 0.000 claims description 5
- 238000000151 deposition Methods 0.000 claims description 5
- 238000002161 passivation Methods 0.000 claims description 5
- 238000002360 preparation method Methods 0.000 claims description 5
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 claims description 4
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 claims description 4
- 230000008021 deposition Effects 0.000 claims description 4
- 230000005684 electric field Effects 0.000 claims description 4
- 238000009792 diffusion process Methods 0.000 claims description 3
- 238000009413 insulation Methods 0.000 claims description 3
- 229910000147 aluminium phosphate Inorganic materials 0.000 claims description 2
- 238000009826 distribution Methods 0.000 claims description 2
- 241000790917 Dioxys <bee> Species 0.000 claims 1
- 229910003978 SiClx Inorganic materials 0.000 claims 1
- 239000007943 implant Substances 0.000 claims 1
- 238000000926 separation method Methods 0.000 claims 1
- 230000015572 biosynthetic process Effects 0.000 abstract 1
- 230000005669 field effect Effects 0.000 description 4
- 229910044991 metal oxide Inorganic materials 0.000 description 3
- 150000004706 metal oxides Chemical class 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000008094 contradictory effect Effects 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 238000000280 densification Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
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- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
- H01L29/0646—PN junctions
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
- H01L29/7824—Lateral DMOS transistors, i.e. LDMOS transistors with a substrate comprising an insulating layer, e.g. SOI-LDMOS transistors
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Abstract
The manufacture method of a kind of grooved lateral MOSFET device, belongs to power semiconductor manufacturing technology field.The present invention is by etching deep trouth, thermally grown formation insulating medium layer, deposit semiconductor layer, planarization semiconductor layer, angle-tilt ion injection, high temperature knot, deposit dielectric and planarization dielectric, eventually form the critical process step such as active area and electrode, it is achieved that the technique manufacture of a kind of grooved horizontal semiconductor device.The technique of the present invention has the advantage that first, the present invention can be formed in groove two side two kinds of different doping types, narrow and high concentration extend to the P post region bottom media slot or N post district, be conducive to improving the pressure of device, reduce conducting resistance and reduce lateral device dimensions；Second, it is not necessary to complicated mask, reduce process costs；3rd, it is to avoid the impact that media slot is filled and body district, body contact area and source region and drain region are produced by planarization.
Description
Technical field
The invention belongs to power semiconductor manufacturing technology field, relate to MOSFET (Metal Oxide
Semiconductor field effect transistor, metal-oxide semiconductor fieldeffect transistor) device, especially
It is LDMOD (Lateral Double-diffusion Metal Oxide Semiconductor field effect
Transistor, lateral double diffused metal-Oxide-Semiconductor Field effect transistor) manufacture method of device.
Background technology
Power MOSFET is many electronic conductions type device, and its key parameter is pressure and compares conducting resistance.The raising that it is pressure
Require increase and the reduction of drift doping concentration of drift region length.But, drift region concentration reduces, and can cause conducting resistance
Increase；Drift region length increases, and has both increased conducting resistance, also increases the area of device, thus increases than conducting resistance.Passing
In the power MOSFET of system, ratio conducting resistance Ron,sp(than conducting resistance=conducting resistance × device area) is according to pressure BV's
Relational expression Ron,sp∝BV2.5Sharply increase.Above deficiency limits power MOSFET application in high voltage integrated circuit, especially
It it is the application in the circuit requiring low-loss and little chip area.
In order to reduce the size of power device, and improving its performance, groove structure is introduced in power device, forms grooved
Power device.Slot type power device is the important component part of Power Electronic Circuit, breakdown voltage height, leakage when cut-off state
Electric current is little；When conducting state less than conducting resistance.Use groove structure can significantly shorten lateral device dimensions, reduce device
Shared chip area.To sum up, slot type power device has become as the power device of main flow.
Commonly use extension in semiconductor processing, deposit, spread and the processing step such as ion implanting.Wherein, extension work
Skill can be accurately controlled the thickness of generated semiconductor layer, extension generated for single-crystal semiconductor layer.Deposit is for technique
Require low, low cost, and also owing to deposit is temperature required relatively low, the most therefore deposition speed is usually used in generating thicker quasiconductor
Layer.Spread, low cost low for technological requirement.Ion implanting can accurately control doping content and penetration depth, and adulterates
Uniformity preferable.Additionally ion implanting have produce single ionic bundle, use low temperature process, injection ion can pass thin
Film and without advantages such as solid solubility limits.Angle-tilt ion injects advantage groove wall doping to uniqueness: can be at groove two
Sidewall formed two kinds of different doping types, narrow and high concentration extend to the P post region bottom media slot or N post district.
Summary of the invention
The present invention combines commonly used several processing steps in existing semiconductor technology, proposes a kind of grooved (Silicon-on-insulator) MOSFET lateral
The manufacture method of device.
The present invention realizes by using following technical proposals；
The manufacture method of a kind of grooved lateral MOSFET device, comprises the following steps:
Step 1: material prepares.Prepare SOI material (as shown in Figure 1a) or body silicon materials (as shown in Figure 1 b), described
SOI material includes substrate layer 1, dielectric buried layer 2 and active layer 3, and wherein dielectric buried layer 2 is between substrate layer 1 and active layer 3,
The conduction type of substrate layer 1 does not limits, and the conduction type of active layer 3 is the first conduction type；Described body silicon materials include substrate layer 1
With active layer 2, wherein the conduction type of substrate layer 1 is the second conduction type, and the conduction type of active layer 3 is the first conductive-type
Type.
Step 2: use SOI material or active layer 3 superficial growth of body silicon materials that thermal oxidation technology prepared in step 1
Layer of oxide layer 41, then at oxide layer 41 surface deposition Si3N4Layer 42, smears photoresist 43 and carries out photoetching (as shown in Figure 2)；
Step 3: by step 2 gained photoetching window, first etch Si3N4Layer 42 and oxide layer 41, be then etched with active layer
3 to set depth, forms the first groove, then removes photoresist (as shown in Figure 3)；
Step 4: use thermal oxidation technology to isolate as medium in step 3 gained the first trench wall growth layer of oxide layer
4 (as shown in Figure 4) of layer；
Step 5: deposit the polycrystalline silicon material of the first conduction type in the first groove after forming buffer layer 4, and
Ensure that the polycrystalline silicon material of the first conduction type is full of the first groove (as shown in Figure 5)；
Step 6: with Si3N4The polycrystalline silicon material of the first conduction type that step 5 is deposited by layer 42 as etch stop layer
Carry out planarization process (as shown in Figure 6)；
Step 7: etch the polycrystalline silicon material of the first conduction type to setting in the setting width of distance the first trenched side-wall
Depthkeeping degree, forms auxiliary semiconductor layer 5b (as shown in Figure 7) of the first conduction type at buffer layer 4 along flute wall surfaces；
Step 8: the first conduction type assists the side of semiconductor layer 5b use angle-tilt ion to inject and knot is formed
Auxiliary semiconductor layer 5a (as shown in Figure 8) of the second conduction type；
Step 9: forming auxiliary semiconductor layer 5b and the auxiliary semiconductor layer of the second conduction type of the first conduction type
Fill dielectric 6 in the first groove after 5a, and ensure that dielectric 6 is full of the first groove (as shown in Figure 9)；
Step 10: the dielectric 6 being filled step 9 carries out planarization process, and removes Si3N4Layer 42 and oxide layer
41, finally make dielectric 6 surface flush (as shown in Figure 10) with active layer 3 surface；
Step 11: active layer 3 intermediate ion in the auxiliary semiconductor layer 5a side near the second conduction type injects second
Conductive type impurity, and knot forms the second conductivity type body region 7 (as shown in figure 11)；
Step 12: near side ion implanting first conduction type of buffer layer 4 in the second conductivity type body region 7
Impurity, and knot forms the first conduction type heavy doping source region 9a；Simultaneously at the auxiliary semiconductor layer near the first conduction type
Active layer 3 intermediate ion of 5b side injects the first conductive type impurity, and knot forms the first conduction type heavy doping drain region 9b；
And inject the first conductive type impurity at the auxiliary semiconductor layer 5b surface ion of the first conduction type, and knot forms first
Cut-off region, conduction type heavy doping field 11 (as shown in figure 12)；
Step 13: the side ion implanting of the first conduction type heavy doping source region 9a in the second conductivity type body region 7
Two conductive type impurities, and knot forms the second conduction type heavy doping body contact area 8；Simultaneously in the auxiliary of the second conduction type
Semiconductor layer 5a surface ion injects the second conductive type impurity, and knot forms the second conduction type grid end ohmic contact regions
10a (as shown in figure 13)；
Step 14: the preparation of each electrode and surface passivation technology, forms complete device (as shown in figure 14)；Device completes
After, the exit of the first conduction type heavy doping source region 9a and the second conduction type heavy doping body contact area 8 all with metal source S
Being connected, the exit of the first conduction type heavy doping drain region 9b is connected with metal-drain D, the second conduction type grid end Ohmic contact
The exit of district 10a is connected with metal gates G.
Further, the buffer layer 4 that step 4 is formed in step 3 gained the first trench wall growth oxide layer is permissible
It is higher than the dielectric of silicon dioxide for silicon dioxide or dielectric coefficient, and critical breakdown electric field is more than 30V/ μm.
Further, angle-tilt ion described in step 8 injects the direction referring to ion implanting and active layer 3 surface normal side
Being 0～30 degree to angle, concrete angle depends on the depth-to-width ratio of the first groove；First groove depth-to-width ratio is the biggest, and angle-tilt ion is noted
Enter angle the least；Angle-tilt ion injects the impurity of the second conduction type should select the impurity that diffusion coefficient is little, in order to control second
The transverse width of conduction type auxiliary semiconductor layer 5a and concentration distribution.
Further, when step 9 fills dielectric 6 in the first groove, the medium that the mode owing to depositing grows is not
And thermally grown medium densification, high temperature density can be selected, in the case of dielectric is thicker in the first groove, need to use
The mode repeatedly deposited is filled；The dielectric 6 filled is insulation Jie that silicon dioxide or dielectric coefficient are less than silicon dioxide
Matter, and critical breakdown electric field is more than 30V/ μm.
Further, the specific operation process of step 10 is: remove the insulation at top initially with chemical-mechanical planarization
Medium 6, until exposing Si3N4Layer 42, then uses strong phosphoric acid to remove Si3N4Layer 42, is then used by hydrofluoric acid rinse to remove oxygen
Change layer 41, so that dielectric 6 surface flushes with active layer 3 surface.
The grooved lateral MOSFET device using process of the present invention to be formed has following advantage.
First, the present invention can form two kinds of different doping types, the extending to of narrow and high concentration in media slot two side
P post region bottom media slot or N post district, be conducive to improving the pressure of device, reduce conducting resistance and reduce the horizontal chi of device
Very little；Second, it is not necessary to complicated mask, reduce process costs；3rd, it is to avoid media slot is filled and planarization is to body district, body
The impact that contact area and source region and drain region produce.Device prepared by this method is applied and is controlled significantly alleviate on device at MOS
Pressure and than the contradictory relation between conducting resistance.
Accompanying drawing explanation
The generalized section of Fig. 1 a, SOI material.
Fig. 1 b, the generalized section of body silicon materials.
Fig. 2, form oxide layer and Si in active layer surface3N4Masking layer is also smeared the section after photoresist carries out photoetching and is shown
It is intended to.
Fig. 3, longitudinally etching, form the generalized section of the first groove.
Fig. 4, first trench wall formed buffer layer generalized section.
Fig. 5, on buffer layer, deposit the generalized section of the polysilicon layer of the first conduction type.
Fig. 6, polysilicon layer surface planarize after generalized section.
Fig. 7, polysilicon layer longitudinally etching forms the generalized section of the first conduction type auxiliary semiconductor layer.
Fig. 8, angle-tilt ion are injected and knot forms the second conduction type and assists the generalized section of semiconductor layer.
Fig. 9, in the first groove, fill the generalized section of dielectric.
Figure 10, dielectric surface is planarized after generalized section.
Figure 11, ion implanting form body district, and the generalized section of knot.
Figure 12, ion implanting knot form source region, the section signal of the cut-off region, field of drain region and the first conduction type
Figure.
Figure 13, ion implanting knot form body contact area and the generalized section of grid end ohmic contact regions.
The preparation of Figure 14, each electrode and surface passivation technology, the generalized section forming complete device (normally works and needs
External diode).
Figure 15, top longitudinally etching in the first conduction type side of auxiliary semiconductor layer, form cuing open of the second groove
Face schematic diagram.
Figure 16, ion implanting form source region, drain region and form the cut-off region, field of the first conduction type at the second groove
Generalized section.
Figure 17, to the second trench fill second conductive type semiconductor layer and planarize after formed drain terminal contact area section
Schematic diagram.
Figure 18, ion implanting knot form body contact area and the generalized section of grid end ohmic contact regions.
The preparation of Figure 19, each electrode and surface passivation technology, the generalized section forming complete device (can be the most normal
Work).
Reference:
1 is substrate layer；2 is dielectric buried layer；3 is active layer；3a is N-type drift region；4 is buffer layer；5a is second
Conduction type auxiliary semiconductor layer；5b is the first conduction type auxiliary semiconductor layer；6 is media slot；7 is the second conduction type body
District；8 is the second conduction type heavy doping body contact area；9a is the first conduction type heavy doping source region；9b is the first conduction type
Heavy doping drain region；10a is the second conduction type grid end ohmic contact regions；10b is the second conduction type drain terminal contact area；11 is
One cut-off region, conduction type heavy doping field；41 is the oxide layer on active layer 3 surface；42 is the Si on oxide layer 41 surface3N4Shelter
Layer；D1 is diode；S is metal source；D is metal-drain；G is metal gates.
Detailed description of the invention
Embodiment 1
As a kind of better embodiment of the present invention, the invention discloses a kind of novel having outside deep trouth and groove and have
The manufacture method of N-channel horizontal slot type power MOSFET of the auxiliary semiconductor layer of two kinds of different conduction-types, specifically include as
Lower step:
Step 1: material prepares.Prepare SOI material (as shown in Figure 1a) or body silicon materials (as shown in Figure 1 b), described
SOI material includes substrate layer 1, dielectric buried layer 2 and active layer 3, and wherein dielectric buried layer 2 is between substrate layer 1 and active layer 3,
The conduction type of substrate layer 1 does not limits, and the conduction type of active layer 3 is the first conduction type；Described body silicon materials include substrate layer 1
With active layer 2, wherein the conduction type of substrate layer 1 is the second conduction type, and the conduction type of active layer 3 is the first conductive-type
Type.
Step 2: use SOI material or active layer 3 superficial growth of body silicon materials that thermal oxidation technology prepared in step 1
Layer of oxide layer 41, then at oxide layer 41 surface deposition Si3N4Layer 42, smears photoresist 43 and carries out photoetching (as shown in Figure 2)；
Step 3: by step 2 gained photoetching window, first etch Si3N4Layer 42 and oxide layer 41, be then etched with active layer
3 to set depth, forms the first groove, then removes photoresist (as shown in Figure 3)；
Step 4: use thermal oxidation technology to isolate as medium in step 3 gained the first trench wall growth layer of oxide layer
4 (as shown in Figure 4) of layer；
Step 5: deposit the polycrystalline silicon material of the first conduction type in the first groove after forming buffer layer 4, and
Ensure that the polycrystalline silicon material of the first conduction type is full of the first groove (as shown in Figure 5)；
Step 6: with Si3N4The polycrystalline silicon material of the first conduction type that step 5 is deposited by layer 42 as etch stop layer
Carry out planarization process (as shown in Figure 6)；
Step 7: etch the polycrystalline silicon material of the first conduction type to setting in the setting width of distance the first trenched side-wall
Depthkeeping degree, forms auxiliary semiconductor layer 5b (as shown in Figure 7) of the first conduction type at buffer layer 4 along flute wall surfaces；
Step 8: the first conduction type assists the side of semiconductor layer 5b use angle-tilt ion to inject and knot is formed
Auxiliary semiconductor layer 5a (as shown in Figure 8) of the second conduction type；
Step 9: forming auxiliary semiconductor layer 5b and the auxiliary semiconductor layer of the second conduction type of the first conduction type
Fill dielectric 6 in the first groove after 5a, and ensure that dielectric 6 is full of the first groove (as shown in Figure 9)；
Step 10: the dielectric 6 being filled step 9 carries out planarization process, and removes Si3N4Layer 42 and oxide layer
41, finally make dielectric 6 surface flush (as shown in Figure 10) with active layer 3 surface；
Step 11: active layer 3 intermediate ion in the auxiliary semiconductor layer 5a side near the second conduction type injects second
Conductive type impurity, and knot forms the second conductivity type body region 7 (as shown in figure 11)；
Step 12: near side ion implanting first conduction type of buffer layer 4 in the second conductivity type body region 7
Impurity, and knot forms the first conduction type heavy doping source region 9a；Simultaneously at the auxiliary semiconductor layer near the first conduction type
Active layer 3 intermediate ion of 5b side injects the first conductive type impurity, and knot forms the first conduction type heavy doping drain region 9b；
And inject the first conductive type impurity at the auxiliary semiconductor layer 5b surface ion of the first conduction type, and knot forms first
Cut-off region, conduction type heavy doping field 11 (as shown in figure 12)；
Step 13: the side ion implanting of the first conduction type heavy doping source region 9a in the second conductivity type body region 7
Two conductive type impurities, and knot forms the second conduction type heavy doping body contact area 8；Simultaneously in the auxiliary of the second conduction type
Semiconductor layer 5a surface ion injects the second conductive type impurity, and knot forms the second conduction type grid end ohmic contact regions
10a (as shown in figure 13)；
Step 14: the preparation of each electrode and surface passivation technology, forms complete device (as shown in figure 14)；Device completes
After, the exit of the first conduction type heavy doping source region 9a and the second conduction type heavy doping body contact area 8 all with metal source S
Being connected, the exit of the first conduction type heavy doping drain region 9b is connected with metal-drain D, the second conduction type grid end Ohmic contact
The exit of district 10a is connected with metal gates G.
As shown in figure 14, the grooved lateral MOSFET device technique that the present embodiment manufactures is simple, it is not necessary to complicated mask,
Low cost.But the proper device operation being made up of embodiment 1 needs external diode d1.
Embodiment 2
This example propose a kind of need not that external circuits just can normally work novel have outside deep trouth and groove there are two kinds
The manufacture method of the N-channel horizontal slot type power MOSFET of the auxiliary semiconductor layer of different conduction-types.This example and embodiment 1 phase
More specific also need to increase following processing step:
(1) step A is being increased described in embodiment 1 between step 11 and step 12: in active layer 3 superficial growth one layer oxidation
Layer, smear photoresist, the auxiliary semiconductor layer 5b of the first conduction type is exposed in photoetching, then etches the auxiliary of the first conduction type
Semiconductor layer 5b is until set depth, to form the second groove (as shown in figure 15)；
(2) step B is being increased described in embodiment 1 between step 12 and step 13: fill in step A gained the second groove
P-type semiconductor, and its surface is planarized and removes removing oxide layer so that it is surface flushes with active layer 3 surface to be formed
Second conduction type drain terminal contact area 10b (as shown in figure 17).
Compared with Example 1, embodiment 2 adds 2 step process, makes device be integrated with external diode, it is not necessary to external
Diode just can normally work.
Claims (6)
1. a manufacture method for grooved lateral MOSFET device, comprises the following steps:
Step 1: material prepares；Preparing SOI material or body silicon materials, described SOI material includes substrate layer (1), dielectric buried layer
(2) and active layer (3), wherein dielectric buried layer (2) is positioned between substrate layer (1) and active layer (3), the conductive-type of substrate layer (1)
Type does not limits, and the conduction type of active layer (3) is the first conduction type；Described body silicon materials include substrate layer (1) and active layer
(3), wherein the conduction type of substrate layer (1) is the second conduction type, and the conduction type of active layer (3) is the first conduction type；
Step 2: use SOI material or active layer (3) superficial growth one of body silicon materials that thermal oxidation technology prepared in step 1
Layer oxide layer (41), then at oxide layer (41) surface deposition Si3N4Layer (42), smears photoresist (43) and carries out photoetching；
Step 3: by step 2 gained photoetching window, first etch Si3N4Layer (42) and oxide layer (41), be then etched with active layer
(3) to set depth, form the first groove, then remove photoresist；
Step 4: use thermal oxidation technology in step 3 gained the first trench wall growth layer of oxide layer as buffer layer
(4)；
Step 5: deposit the polycrystalline silicon material of the first conduction type in the first groove after forming buffer layer (4), and protect
The polycrystalline silicon material demonstrate,proving the first conduction type is full of the first groove；
Step 6: with Si3N4The polycrystalline silicon material of the first conduction type that step 5 is deposited by layer (42) as etch stop layer enters
Row planarization processes；
Step 7: the polycrystalline silicon material etching the first conduction type in the setting width of distance the first trenched side-wall is deep to setting
Degree, forms the auxiliary semiconductor layer (5b) of the first conduction type at buffer layer (4) along flute wall surfaces；
Step 8: use angle-tilt ion to inject the side of the auxiliary semiconductor layer (5b) of the first conduction type and knot forms the
The auxiliary semiconductor layer (5a) of two conduction types；
Step 9: forming auxiliary semiconductor layer (5b) and the auxiliary semiconductor layer of the second conduction type of the first conduction type
(5a) fill dielectric (6) in the first groove after, and ensure that dielectric (6) is full of the first groove；
Step 10: the dielectric (6) being filled step 9 carries out planarization process, and removes Si3N4Layer (42) and oxide layer
(41) dielectric (6) surface, is finally made to flush with active layer (3) surface；
Step 11: active layer (3) intermediate ion in auxiliary semiconductor layer (5a) side near the second conduction type injects second
Conductive type impurity, and knot forms the second conductivity type body region (7)；
Step 12: near side ion implanting first conduction type of buffer layer (4) in the second conductivity type body region (7)
Impurity, and knot forms the first conduction type heavy doping source region (9a)；Simultaneously at the auxiliary quasiconductor near the first conduction type
Active layer (3) intermediate ion of layer (5b) side injects the first conductive type impurity, and knot forms the first conduction type heavy doping
Drain region (9b)；And inject the first conductive type impurity at auxiliary semiconductor layer (5b) surface ion of the first conduction type, and
Knot forms the first cut-off region, conduction type heavy doping field (11)；
Step 13: the side ion implanting of the first conduction type heavy doping source region (9a) in the second conductivity type body region (7)
Two conductive type impurities, and knot forms the second conduction type heavy doping body contact area (8)；Simultaneously auxiliary at the second conduction type
Help semiconductor layer (5a) surface ion to inject the second conductive type impurity, and knot forms the second conduction type grid end Ohmic contact
District (10a)；
Step 14: the preparation of each electrode and surface passivation technology, forms complete device；After device completes, the first conduction type
Heavy doping source region (9a) is all connected with metal source (S) with the exit of the second conduction type heavy doping body contact area (8), and first
The exit in conduction type heavy doping drain region (9b) is connected with metal-drain (D), the second conduction type grid end ohmic contact regions
(10a) exit is connected with metal gates (G).
The manufacture method of grooved lateral MOSFET device the most according to claim 1, it is characterised in that in step 11 and step
Between rapid 12 increase step A: active layer (3) superficial growth layer of oxide layer, smear photoresist, the first conductive-type is exposed in photoetching
The auxiliary semiconductor layer (5b) of type, then etches the auxiliary semiconductor layer (5b) of the first conduction type to set depth, to be formed
Second groove；Step B is increased: in step A gained the second groove, fill P-type semiconductor between step 12 and step 13, and
Its surface is planarized and removes removing oxide layer so that it is surface flushes to form the second conduction type with active layer 3 surface
Drain terminal contact area (10b).
The manufacture method of grooved lateral MOSFET device the most according to claim 1 and 2, it is characterised in that step 4 is in step
The buffer layer (4) that rapid 3 gained the first trench walls growth oxide layers are formed is that silicon dioxide or dielectric coefficient are higher than dioxy
The dielectric of SiClx, and critical breakdown electric field is more than 30V/ μm.
The manufacture method of grooved lateral MOSFET device the most according to claim 1 and 2, it is characterised in that institute in step 8
State angle-tilt ion injection and refer to that the direction of ion implanting and active layer (3) surface normal angular separation are 0～30 degree, concrete angle
Depend on the depth-to-width ratio of the first groove；First groove depth-to-width ratio is the biggest, and angle-tilt ion implant angle is the least；Angle-tilt ion injects the
The impurity of two conduction types should select the impurity that diffusion coefficient is little, in order to controls the second conduction type auxiliary semiconductor layer (5a)
Transverse width and concentration distribution.
The manufacture method of grooved lateral MOSFET device the most according to claim 1 and 2, it is characterised in that step 9 is
When filling dielectric (6) in one groove, the medium grown due to the mode of deposit is fine and close not as good as thermally grown medium, selects height
Temperature density, in the case of in the first groove, dielectric is thicker, needs to use the mode repeatedly deposited to fill；That is filled is exhausted
Edge medium (6) is the dielectric that silicon dioxide or dielectric coefficient are less than silicon dioxide, and critical breakdown electric field is more than 30V/ μm.
The manufacture method of grooved lateral MOSFET device the most according to claim 1 and 2, it is characterised in that step 10
Specific operation process is: remove the dielectric (6) at top initially with chemical-mechanical planarization, until exposing Si3N4Layer
(42), strong phosphoric acid is then used to remove Si3N4Layer (42), is then used by hydrofluoric acid rinse to remove oxide layer (41), so that insulation
Medium (6) surface flushes with active layer (3) surface.
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| CN101257047A (en) * | 2008-04-03 | 2008-09-03 | 北京大学 | High pressure resistant lateral direction bilateral diffusion MOS transistor |
| CN102832237A (en) * | 2012-07-03 | 2012-12-19 | 电子科技大学 | Trough-type semiconductor power device |
| CN103050540A (en) * | 2012-12-20 | 2013-04-17 | 电子科技大学 | Low-specific on-resistance lateral power device employing high-dielectric constant groove structure |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101257047A (en) * | 2008-04-03 | 2008-09-03 | 北京大学 | High pressure resistant lateral direction bilateral diffusion MOS transistor |
| CN102832237A (en) * | 2012-07-03 | 2012-12-19 | 电子科技大学 | Trough-type semiconductor power device |
| CN103050540A (en) * | 2012-12-20 | 2013-04-17 | 电子科技大学 | Low-specific on-resistance lateral power device employing high-dielectric constant groove structure |
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